X24321S8-2.5T1 [XICOR]
EEPROM, 4KX8, Serial, CMOS, PDSO8, PLASTIC, SOIC-8;
| 型号： | X24321S8-2.5T1 |
| 厂家： | 
XICOR INC. |
| 描述： | EEPROM, 4KX8, Serial, CMOS, PDSO8, PLASTIC, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总14页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32K
4K x 8 Bit
X24321
400 KHz 2-Wire Serial E2PROM
DESCRIPTION
FEATURES
• 1.8V to 3.6V, 2.5V to 5.5V and 4.5V to 5.5V Power
Supply Operation
• Low Power CMOS
—Active read current less than 1mA
—Active write current less than 3mA
—Standby current less than 1µA
• 400KHz Fast Mode 2-Wire Serial Interface
—Down to 1.8V
The X24321 is a CMOS Serial E2PROM Memory,
internally organized 4K x 8. The device features a
serial interface and software protocol allowing opera-
tion on a simple two wire bus. The bus operates at
400KHz all the way down to 1.8V.
Three device select inputs (S –S ) allow up to eight
0
2
devices to share a common two wire bus.
—Schmitt trigger input noise suppression
—Output slope control for ground bounce noise
elimination
• Internally Organized 4K x 8 Bit
• 32 Byte Page Write Mode
—Minimizes total write time per byte
• Hardware Write Protect
• Bidirectional Data Transfer Protocol
• Self-Timed Write Cycle
Hardware Write Protection is provided through a Write
Protect (WP) input pin on the X24321. When the WP
pin is HIGH, the upper quadrant of the Serial E2PROM
array is protected against any nonvolatile write
attempts.
Xicor Serial E2PROM Memories are designed and
tested for applications requiring extended endurance.
Inherent data retention is greater than 100 years.
—Typical write cycle time of 5ms
• High Reliability
—Endurance: 1,000,000 cycles
—Data retention: 100 years
• 8-Lead SOIC
BLOCK DIAGRAM
Data Register
Serial E2PROM Data
and Address (SDA)
Y Decode Logic
Command
SCL
Page
Decode
Logic
Decode
and
Control
Logic
E2PROM
Array
4K x 8
S
2
Device
Write
Select
Logic
Protect
Logic
S
S
1
0
Write Voltage
Control
WP
Xicor, Inc. 2000 Patents Pending
7040 10/27/00 EP
Characteristics subject to change without notice. 1 of 14
X24321
PIN DESCRIPTIONS
Serial Clock (SCL)
PIN CONFIGURATION
8-Lead SOIC
The SCL input is used to clock all data into and out of
the device.
S
S
S
0
1
2
1
2
8
7
V
CC
WP
X24321
3
4
6
5
SCL
SDA
Serial Data (SDA)
V
SS
SDA is a bidirectional pin used to transfer data into and
out of the device. It is an open drain output and may be
wire-ORed with any number of open drain or open col-
lector outputs.
DEVICE OPERATION
The device supports a bidirectional, bus oriented pro-
tocol. The protocol defines any device that sends data
onto the bus as a transmitter, and the receiving device
as the receiver. The device controlling the transfer is a
master and the device being controlled is the slave.
The master will always initiate data transfers, and pro-
vide the clock for both transmit and receive operations.
Therefore, the device will be considered a slave in all
applications.
An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to the Pull-
up resistor selection graph at the end of this data
sheet.
Device Select (S , S , S )
0
1
2
The device select inputs (S , S , S ) are used to set
0
1
2
the first three bits of the 8-bit slave address. This
allows up to eight devices to share a common bus.
These inputs can be static or actively driven. If used
Clock and Data Conventions
statically they must be tied to V or V
as appropri-
SS
CC
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions. Refer
to Figures 1 and 2.
ate. If actively driven, they must be driven with CMOS
levels.
Write Protect (WP)
The Write Protect input controls the Hardware Write
Protect feature. When held LOW, Hardware Write Pro-
tection is disabled and the device can be written nor-
mally. When this input is held HIGH, Write Protection is
enabled, and nonvolatile writes are disabled to the
upper quadrant of the E2PROM array.
Start Condition
All commands are preceded by the start condition,
which is a HIGH to LOW transition of SDA when SCL is
HIGH. The device continuously monitors the SDA and
SCL lines for the start condition and will not respond to
any command until this condition has been met.
PIN NAMES
Symbol
Description
Device Select Inputs
Serial Data
S , S , S
0
1
2
SDA
SCL
WP
Serial Clock
Write Protect
Ground
V
SS
V
Supply Voltage
CC
Characteristics subject to change without notice. 2 of 14
X24321
Figure 1. Data Validity
SCL
SDA
Data Stable
Data
Change
Figure 2. Definition of Start and Stop
SCL
SDA
START Bit
STOP Bit
Stop Condition
The device will respond with an acknowledge after rec-
ognition of a start condition and its slave address. If
both the device and a Write Operation have been
selected, the device will respond with an acknowledge
after the receipt of each subsequent byte.
All communications must be terminated by a stop con-
dition, which is a LOW to HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the device into the standby power mode after a read
sequence. A stop condition can only be issued after
the transmitting device has released the bus.
In the read mode the device will transmit eight bits of
data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no
stop condition is generated by the master, the device
will continue to transmit data. If an acknowledge is not
detected, the device will terminate further data trans-
missions. The master must then issue a stop condition
to return the device to the standby power mode and
place the device into a known state.
Acknowledge
Acknowledge is a software convention used to indicate
successful data transfer. The transmitting device, either
master or slave, will release the bus after transmitting
eight bits. During the ninth clock cycle the receiver will
pull the SDA line LOW to acknowledge that it received
the eight bits of data. Refer to Figure 3.
Figure 3. Acknowledge Response From Receiver
SCL From
1
Master
8
9
Data Output
From Transmitter
Data Output
From Receiver
START
Acknowledge
Characteristics subject to change without notice. 3 of 14
X24321
DEVICE ADDRESSING
Figure 4. Device Addressing
Following a start condition, the master must output the
address of the slave it is accessing.The first four bits of
the Slave Address Byte are the device type identifier
bits. These must equal “1010”. The next 3 bits are the
Device Type
Identifier
Device
Select
1
0
1
0
S
2
S
1
S
R/W
0
device select bits S , S , and S . This allows up to 8
0
1
2
devices to share a single bus.These bits are compared
SLAVE ADDRESS BYTE
to the S , S , and S device select input pins. The last
0
1
2
bit of the Slave Address Byte defines the operation to
be performed. When the R/W bit is a one, then a Read
Operation is selected. When it is zero then a Write
Operation is selected. Refer to Figure 4. After loading
the Slave Address Byte from the SDA bus, the device
compares the device type bits with the value “1010”
and the device select bits with the status of the device
select input pins. If the compare is not successful, no
acknowledge is output during the ninth clock cycle and
the device returns to the standby mode.
High Order Address
0
0
0
A0 A11 A10 A9 A8
ADDRESS BYTE 1
Low Order Address
The byte address is either supplied by the master or
obtained from an internal counter, depending on the
operation. When required, the master must supply the
two Address Bytes as shown in Figure 4.
A7
A6
A4 A3
A2 A1
A0
A5
ADDRESS BYTE 0
The internal organization of the E2PROM array is 128
pages by 32 bytes per page. The page address is par-
tially contained in the Address Byte 1 and partially in
bits 7 through 5 of the Address Byte 0. The specific
byte address is contained in bits 4 through 0 of the
Address Byte 0. Refer to Figure 4.
D7 D6 D5
D4 D3
D2 D1 D0
DATA BYTE
Characteristics subject to change without notice. 4 of 14
X24321
WRITE OPERATIONS
Byte Write
Page Write Operation
The device executes a thirty-two byte Page Write
Operation. For a Page Write Operation, the device
requires the Slave Address Byte, Address Byte 1, and
Address Byte 0. Address Byte 0 must contain the first
byte of the page to be written. Upon receipt of Address
Byte 0, the device responds with an acknowledge, and
waits for the first eight bits of data. After receiving the 8
bits of the first data byte, the device again responds
with an acknowledge. The device will respond with an
acknowledge after the receipt of each of 31 more
bytes. Each time the byte address is internally incre-
mented by one, while page address remains constant.
When the counter reaches the end of the page, the
master terminates the data loading by issuing a stop
condition, which causes the device to begin the nonvol-
atile write cycle. All inputs are disabled until completion
of the nonvolatile write cycle. The SDA pin is at high
impedance. Refer to Figure 6 for the address, acknowl-
edge, and data transfer sequence.
For a Byte Write Operation, the device requires the
Slave Address Byte, the Word Address Byte 1, and the
Word Address Byte 0, which gives the master access
to any one of the bytes in the array. Upon receipt of the
Word Address Byte 0, the device responds with an
acknowledge, and waits for the first eight bits of data.
After receiving the 8 bits of the data byte, the device
again responds with an acknowledge. The master then
terminates the transfer by generating a stop condition,
at which time the device begins the internal write cycle
to the nonvolatile memory. While the internal write
cycle is in progress the device inputs are disabled and
the device will not respond to any requests from the
master.The SDA pin is at high impedance. See Figure5.
Figure 5. Byte Write Sequence
S
Signals From
The Master
S
T
A
R
T
Word Address
Word Address
Byte 0
Slave
Address
T
O
P
Byte 1
Data
SDA Bus
S 1 0 1 0
0
P
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Figure 6. Page Write Sequence
S
Signals From
T
Slave
Address
S
T
O
P
Word Address
Byte 1
Word Address
Byte 0
The Master
A
Data
R
T
SDA Bus
S 1 0 1 0
0
P
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Characteristics subject to change without notice. 5 of 14
X24321
Acknowledge Polling
READ OPERATIONS
The maximum write cycle time can be significantly
reduced using Acknowledge Polling. To initiate
Acknowledge Polling, the master issues a start condi-
tion followed by the Slave Address Byte for a write or
read operation. If the device is still busy with the non-
volatile write cycle, then no ACK will be returned. If the
device has completed the nonvolatile write operation,
an ACK will be returned and the host can then proceed
with the read or write operation. Refer to Figure 7.
Read operations are initiated in the same manner as
write operations with the exception that the R/W bit of
the Slave Address Byte is set to one. There are three
basic read operations: Current Address Reads, Ran-
dom Reads, and Sequential Reads.
Current Address Read
Internally, the device contains an address counter that
maintains the address of the last byte read or written,
incremented by one. After a read operation from the
last address in the array, the counter will “roll over” to
the first address in the array. After a write operation to
the last address in a given page, the counter will “roll
over” to the first address of the same page.
Figure 7. Acknowledge Polling Sequence
Byte Load Completed
By Issuing STOP.
Enter ACK Polling
Upon receipt of the Slave Address Byte with the R/W bit
set to one, the device issues an acknowledge and then
transmits the byte at the current address. The master
terminates the read operation when it does not respond
with an acknowledge during the ninth clock and then
issues a stop condition. Refer to Figure 8 for the
address, acknowledge, and data transfer sequence.
Issue
START
Issue Slave
Address Byte
(Read or Program)
Issue STOP
It should be noted that the ninth clock cycle of the read
operation is not a “don’t care.” To terminate a read
operation, the master must either issue a stop condi-
tion during the ninth cycle or hold SDA HIGH during
the ninth clock cycle and then issue a stop condition.
No
ACK
Returned?
Figure 8. Current Address Read Sequence
Yes
S
Signals From
The Master
Nonvolatile
T
A
R
T
S
T
Slave
Address
Write
Cycle Complete.
Continue
No
O
P
SDA Bus
S 1 0 1 0
1
P
Sequence?
A
C
K
Signals From
The Slave
Yes
Data
Continue Normal
Read or Program
Issue STOP
Command Sequence
PROCEED
Characteristics subject to change without notice. 6 of 14
X24321
Random Read
from the device. The master terminates the read oper-
ation by not responding with an acknowledge and then
issuing a stop condition. Refer to Figure 9 for the
address, acknowledge, and data transfer sequence.
Random read operation allows the master to access
any memory location in the array. Prior to issuing the
Slave Address Byte with the R/W bit set to one, the
master must first perform a “Dummy” write operation.
The master issues the start condition and the Slave
Address Byte with the R/W bit low, receives an
acknowledge, then issues Address Byte 1, receives
another acknowledge, then issues Address Byte 0 con-
taining the address of the byte to be read. After the
device acknowledges receipt of Address Byte 0, the
master issues another start condition and the Slave
Address Byte with the R/W bit set to one. This is fol-
lowed by an acknowledge and then eight bits of data
The device will perform a similar operation called “Set
Current Address” if a stop is issued instead of the sec-
ond start shown in Figure 9. The device will go into
standby mode after the stop and all bus activity will be
ignored until a start is detected. The effect of this oper-
ation is that the new address is loaded into the address
counter, but no data is output by the device.
The next Current Address Read operation will read
from the newly loaded address.
Figure 9. Random Read Sequence
S
S
Signals From
The Master
T
A
R
T
A
R
Address
Byte 1
Address
Byte 0
Slave
Address
Slave
Address
S
T
O
P
T
T
SDA Bus
1
S 1 0 1 0
0
S
P
A
C
K
A
C
K
A
C
K
A
C
K
Signals From
The Slave
Data
Sequential Read
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments
through all byte addresses, allowing the entire memory
contents to be read during one operation. At the end of
the address space the counter “rolls over” to address
0000h and the device continues to output data for each
acknowledge received. Refer to Figure 10 for the
acknowledge and data transfer sequence.
Sequential reads can be initiated as either a current
address read or random read.The first byte is transmit-
ted as with the other modes; however, the master now
responds with an acknowledge, indicating it requires
additional data. The device continues to output data for
each acknowledge received. The master terminates
the read operation by not responding with an acknowl-
edge and then issuing a stop condition.
Figure 10. Sequential Read Sequence
Signals From
The Master
A
C
K
A
C
K
A
C
K
S
T
O
P
Slave
Address
SDA Bus
1
P
A
C
K
Signals From
The Slave
Data
(1)
Data
(2)
Data
(n–1)
Data
(n)
Characteristics subject to change without notice. 7 of 14
X24321
ABSOLUTE MAXIMUM RATINGS
COMMENT
Temperature under bias X24321...........–65 to +135°C
Storage Temperature.............................–65 to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and the functional operation
of the device at these or any other conditions above
those indicated in the operational sections of this spec-
ification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
Voltage on any pin with respect to V .......–1V to +7V
SS
D.C. output current ............................................... 5mA
Lead temperature (soldering, 10 seconds).........300°C
RECOMMENDED OPERATING CONDITIONS
Temperature
Commercial
Industrial
Min.
0°C
Max.
+70°C
+85°C
Supply Voltage
X24321
Limits
4.5V to 5.5V
2.5V to 5.5V
1.8V to 3.6V
–40°C
X24321–2.5
X24321–1.8
D.C. OPERATING CHARACTERISTICS
Limits
Unit
s
Symbol
Parameter
Min.
Max.
Test Conditions
SCL = V X 0.1/V X 0.9 Levels
I
I
V
V
Supply Current (Read)
Supply Current (Write)
1
3
mA
mA
CC1
CC2
CC
CC
CC
@ 400KHz, SDA = Open, All Other
Inputs = V or V – 0.3V
CC
SS
CC
(1)
I
I
V
Standby Current
Standby Current
3
1
µA
µA
SCL = SDA = V – 0.3V, All Other Inputs
CC
SB1
SB2
CC
CC
= V or V – 0.3V, V = 5V ± 10%
SS
CC
CC
(1)
V
SCL = SDA = V – 0.1V, All Other Inputs
CC
= V or V – 0.1V, V = 1.8V
SS
CC
CC
I
Input Leakage Current
Output Leakage Current
Input LOW Voltage
10
10
µA
µA
V
V
V
= V to V
SS
CC
LI
IN
I
= V to V
SS
CC
LO
OUT
(2)
V
–0.5
V
x 0.3
lL
CC
(2)
V
Input HIGH Voltage
Output LOW Voltage
V
x 0.7
V
+ 0.5
V
IH
CC
CC
V
0.4
V
I
= 3mA
OL
OL
(3)
V
Hysteresis of Schmitt Trigger
Inputs
V
x 0.05
= 5V
V
hys
CC
CAPACITANCE T = +25°C, f = 1MHz, V
A
CC
Symbol
Parameter
Max.
Units
pF
Test Conditions
(3)
I/O
C
Input/Output Capacitance (SDA)
8
6
V
= 0V
= 0V
I/O
(3)
IN
C
Input Capacitance (S , S , S , SCL,WP)
pF
V
IN
0
1
2
Notes: (1) Must perform a stop command prior to measurement.
(2) V min. and V max. are for reference only and are not 100% tested.
IL
IH
(3) This parameter is periodically sampled and not 100% tested.
Characteristics subject to change without notice. 8 of 14
X24321
A.C. CONDITIONS OF TEST
EQUIVALENT A.C. LOAD CIRCUIT
Input pulse levels
V
x 0.1 to V x 0.9
CC
CC
5V
Input rise and fall times
Input and output timing levels
10ns
V
X 0.5
CC
1.53KΩ
Output
100pF
A.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.)
Read & Program Cycle Limits
Symbol
Parameter
Min.
0
Max. Units
f
SCL Clock Frequency
400
KHz
ns
SCL
T
Noise Suppression Time
50
I
Constant at SCL, SDA Inputs
t
SCL LOW to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
0.1
1.2
0.9
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
ns
ns
AA(6)
t
BUF
t
t
0.6
HD:STA
t
Clock LOW Period
1.2
LOW
t
Clock HIGH Period
0.6
HIGH
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
0.6
SU:STA
HD:DAT
t
0
t
Data In Setup Time
100
SU:DAT
(5)
(5)
t
SDA and SCL Rise Time
20+0.1XC
20+0.1XC
0.6
300
300
R
b
b
t
SDA and SCL Fall Time
F
t
Stop Condition Setup Time
Data Out Hold Time
SU:STO
t
50
DH
(5)
t
Output Fall Time
20 + 0.1C
250
OF
b
POWER-UP TIMING(4)
Symbol
Parameter
Max.
Units
t
Power-up to Read Operation
Power-up to Write Operation
1
5
ms
ms
PUR
t
PUW
Notes: (4) t
and t
are the delays required from the time V is stable until the specified operation can be initiated. These parameters
CC
PUR
PUW
are periodically sampled and not 100% tested.
(5) C = total capacitance of one bus line in pF
b
(6) t = 1.1µs Max below V = 2.5V.
AA
CC
Characteristics subject to change without notice. 9 of 14
X24321
Bus Timing
t
t
t
R
t
HIGH
LOW
F
SCL
t
t
t
t
t
SU:STO
SU:STA
HD:STA
SU:DAT
HD:DAT
SDA In
t
t
t
BUF
AA
DH
SDA Out
Program Cycle Limits
Symbol
Parameter
Min.
Typ.(7)
Max.
Units
(8)
WR
T
Program Cycle Time
5
10
ms
Notes: (7) Typical values are for T = 25°C and nominal supply voltage (5V).
A
(8) t
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
WR
time the device requires to automatically complete the nonvolatile write operation.
The program cycle time is the time from a valid stop condition of a program sequence to the end of the internal
erase/program cycle. During the program cycle, the X24321 bus interface circuits are disabled, SDA is allowed to
remain HIGH, and the device does not respond to its slave address.
Bus Timing
SCL
ACK
SDA
8th Bit
Word n
t
WR
Stop
START
Condition
Condition
Characteristics subject to change without notice. 10 of 14
X24321
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
SYMBOL TABLE
WAVEFORM
INPUTS
OUTPUTS
120
V
I
CC MAX
R
=
=1.8KΩ
MIN
Must be
steady
Will be
steady
100
80
OL MIN
t
R
R
=
MAX
May change
from Low to
High
Will change
from Low to
High
C
BUS
Max.
Resistance
60
40
20
May change
from High to
Low
Will change
from High to
Low
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
Min.
Resistance
0
N/A
Center Line
is High
Impedance
0
100 120
20
40
60
80
Bus Capacitance (pF)
Characteristics subject to change without notice. 11 of 14
X24321
PACKAGING INFORMATION
8-Lead Plastic Small Outline Gull Wing Package Type S
0.150 (3.80) 0.228 (5.80)
0.158 (4.00) 0.244 (6.20)
Pin 1 Index
Pin 1
0.014 (0.35)
0.019 (0.49)
0.188 (4.78)
0.197 (5.00)
(4X) 7°
0.053 (1.35)
0.069 (1.75)
0.004 (0.19)
0.010 (0.25)
0.050 (1.27)
0.010 (0.25)
0.050"Typical
X 45°
0.020 (0.50)
0.050"
Typical
0° - 8°
0.0075 (0.19)
0.010 (0.25)
0.250"
0.016 (0.410)
0.037 (0.937)
0.030"
Typical
8 Places
FOOTPRINT
NOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)
Characteristics subject to change without notice. 12 of 14
X24321
Ordering Information
X24321
X
X
-X
V
Range
Device
CC
Blank = 5V ±10%
2.5 = 2.5V to 5.5V
1.8 = 1.8V to 3.6V
Temperature Range
Blank = 0 to +70°C
I = –40 to +85°C
Package
X24321
S8= 8-Lead SOIC
Characteristics subject to change without notice. 13 of 14
X24321
Part Mark Convention
Blank = 8-Lead SOIC
X24321
X
X
Blank = 4.5V to 5.5V, 0 to +70°C
I = 4.5V to 5.5V, –40 to +85°C
AE = 2.5V to 5.5V, 0 to +70°C
AF = 2.5V to 5.5V, –40 to +85°C
AG = 1.8V to 3.6V, 0 to +70°C
AH = 1.8V to 3.6V, –40 to +85°C
LIMITED WARRANTY
Devices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express,
statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes
no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and
without notice.
Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, or licenses are implied.
TRADEMARK DISCLAIMER:
Xicor and the Xicor logo are registered trademarks of Xicor, Inc. AutoStore, Direct Write, Block Lock, SerialFlash, MPS, and XDCP are also trademarks of Xicor, Inc. All
others belong to their respective owners.
U.S. PATENTS
Xicor products are covered by one or more of the following U.S. Patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846;
4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084,667; 5,153,880; 5,153,691; 5,161,137;
5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. Foreign patents and additional patents pending.
LIFE RELATED POLICY
In situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and
correction, redundancy and back-up features to prevent such an occurence.
Xicor’s products are not authorized for use in critical components in life support devices or systems.
1.
Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to
perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.
2.
A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
Characteristics subject to change without notice. 14 of 14
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