SUM50N03 [VISHAY]
SPICE Device Model SUM50N03-13LC; SPICE器件模型SUM50N03-13LC
| 型号： | SUM50N03 |
| 厂家： | 
VISHAY |
| 描述： | SPICE Device Model SUM50N03-13LC |
| 文件： | 总3页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPICE Device Model SUM50N03-13LC
Vishay Siliconix
N-Channel 30-V (D-S) 175°C MOSFET with Sense Terminal
CHARACTERISTICS
• N-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the n-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0 to 10V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to
model the gate charge characteristics while avoiding convergence
difficulties of the switched Cgd model. All model parameter values
are optimized to provide a best fit to the measured electrical data
and are not intended as an exact physical interpretation of the
device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 71918
09-Jun-04
www.vishay.com
1
SPICE Device Model SUM50N03-13LC
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Simulated
Data
Measured
Data
Parameter
Symbol
Test Conditions
Unit
Static
Gate Threshold Voltage
On-State Drain Currenta
VGS(th)
ID(on)
1.8
V
A
V
DS = VGS, ID = 250 µA
VDS = 5 V, VGS = 10 V
VGS = 10 V, ID = 25 A
434
0.010
0.016
0.018
0.014
0.90
0.010
0.016
0.018
0.014
1.3
VGS = 10 V, ID = 25 A, TJ = 125°C
VGS = 10 V, ID = 25 A, TJ = 175°C
VGS = 4.5 V, ID = 24 A
Drain-Source On-State Resistancea
rDS(on)
Ω
Forward Voltagea
VSD
IS = 50 A, VGS = 0 V
V
Dynamicb
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Chargec
Gate-Source Chargec
Gate-Drain Chargec
Turn-On Delay Timec
Rise Timec
Ciss
Coss
Crss
Qg
2009
367
111
34
1960
380
180
35
VGS = 0 V, VDS = 25 V, f = 1 MHz
pF
nC
VDS = 15 V, VGS = 10 V, ID = 50 A
Qgs
Qgd
td(on)
tr
7.6
5.6
23
7.6
5.6
10
19
93
V
DD = 15 V, RL = 0.30 Ω
Turn-Off Delay Timec
Fall Timec
td(off)
tf
8
30
I
D ≅ 50 A, VGEN = 10 V, RG = 2.5 Ω
ns
10
10
Reverse Recovery Time
trr
29
35
IF = 50,A di/dt = 100 A/µs
Notes
a.
b.
c.
Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
Guaranteed by design, not subject to production testing.
Independent of operating temperature.
www.vishay.com
2
Document Number: 71918
09-Jun-04
SPICE Device Model SUM50N03-13LC
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 71918
09-Jun-04
www.vishay.com
3
相关型号：
SUM50N03-13LC-E3
TRANSISTOR 50 A, 30 V, 0.013 ohm, N-CHANNEL, Si, POWER, MOSFET, ROHS COMPLIANT, D2PAK-5, FET General Purpose Power
VISHAY
SUM50N06-16L-E3
TRANSISTOR 50 A, 60 V, 0.022 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-263AB, ROHS COMPLIANT, TO-263, 3 PIN, FET General Purpose Power
VISHAY
SUM50UFSMSS
Rectifier Diode, 1 Element, 0.4A, 5000V V(RRM), Silicon, HERMETIC SEALED, SMS, 2 PIN
SSDI
SUM50UFSMSTXV
Rectifier Diode, 1 Element, 0.4A, 5000V V(RRM), Silicon, HERMETIC SEALED, SMS, 2 PIN
SSDI
©2020 ICPDF网 联系我们和版权申明