SI9750CY-T1-E3 [VISHAY]

In-Rush Current Limit MOSFET Driver; 浪涌电流限制MOSFET驱动器


型号：	SI9750CY-T1-E3
厂家：	VISHAY
描述：	In-Rush Current Limit MOSFET Driver 浪涌电流限制MOSFET驱动器驱动器 MOSFET驱动器驱动程序和接口接口集成电路光电二极管
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Si9750

Vishay Siliconix

In-Rush Current Limit MOSFET Driver

FEATURES

D 2.9- to 13-V Input Operating Range

D Microprocessor RESET

D Integrated High-Side Driver for N-Channel MOSFET

D Programmable di/dt Current

DESCRIPTION

The Si9750 current limit MOSFET interface IC is designed to

operate between a power source and a load using a low

on-resistance power MOSFET with a sense terminal or in

conjunction with a low ohmic sense resistor. The Si9750

current limiter prevents source and load transients during hot

swap and power-on with programmable dv/dt and di/dt. Both

turn-on and steady-state current limits can be individually

programmed, providing protection against short circuits.

Power on RESET and logic controls allow complete

microprocessor interfacing. The RESET function of the

Si9750 is industry-standard with full programmability.

The Si9750 is available in a 16-pin SOIC package and is rated

over the commercial temperature range (0 to 70_C).

The Si9750 is available in both standard and lead (Pb)-free

packages.

FUNCTIONAL BLOCK DIAGRAM

BOOST

COIL

BIAS

Bias

Boost

BOOST

Ref

POR

BOOST

HI/LO

ENABLE

STATUS

Low R

N-Channel FET

GATE

Gate

Drive

Control

GATE

BIAS

SENSE

Overcurrent

RETRY

Retry

Delay

SENSE

LIMSET

(mW)

LIMSET

LOAD

−

LOAD

POR

RST

Reset

Load

Reset

Delay

−

Ref

GND

RESET

Bandgap

Ref

Document Number: 70028

S-40754—Rev. D, 19-Apr-04

www.vishay.com

Si9750

Vishay Siliconix

ABSOLUTE MAXIMUM RATINGS

Voltages Referenced to Ground

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 125_C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V

Boost Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 V

Power Dissipation (package)

Inputs/Outputs

16-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW

(except Gate, Boost and V

) . . . . . . . . . . . . . . . . . . . . . −0.3 to V + 0.3 V

RST

Thermal Impedance (Q ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W

RST

Input Current (0 < V

< 15 V) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

RST

Inputs/Outputs Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

RESET Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 mA

STATUS Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 mA

Notes

a. Device mounted with all leads soldered or welded to PC board.

b. Derate 7.2 mW/_C above 25_C.

* . Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Stresses above Absolute Maximum rating may cause permanent

damage. Functional operation at conditions other than the operating conditions specified is not implied. Only one Absolute Maximum rating should be applied at any

one time

SPECIFICATIONS

Test Conditions Unless Specified

Limits

0 to 70_C

Typ^b

2.9 V v V v 13.2 V

HI/LO = GND, R

= 12.5 kW

BIAS

Parameter

Symbol

Min^a

Max^a

Unit

= 100 mH, C

= 100 nF

BOOST

Supply

Quiescent Current

ENABLE =Logic Low

Logic

Enable Turn-On Voltage

Enable Turn-Off Voltage

Enable Source Current

Turn-On Time

0.3 x V

EN(on)

EN(off)

ENSRC

0.7 x V

= 0V

120

ENABLE

See Figure 3

Turn-Off Time

OFF

Turn-On Boost

See Figure 4

600

ON(BST)

Initial Short Circuit

Short Circuit

= 33 nF, See Figure 6

= 33 nF, See Figure 7

OFF

OFF(ISC)

GATE

OFF(SC)

GATE

Status Output Voltage

Status Output Delay Time

Status Threshold

= 200 mA

0.4

STAT

SINK

See Figure 8

STDLY

0.85 x V

0.7 x V

0.95 x V

STATTHR

HI/LO Turn-On Voltage

HI/LO Turn-Off Voltage

HILO(on)

0.3 x V

HILO(off)

Gate Drive

Enhancement Voltage (V

Source Current

− V

)

8.5

1.06

1.6

10.5

1.30

2.6

1.54

3.7

GATE

SENSE

SOURCE

= 9 V

CBOOST

Sink Current

SINK

Current Sense Circuit

Current Sense Amplifier Common Mode

Range

CMR

+ 0.3

Current Sense Amplifier Voltage Offset

Current Sense Amplifier Bias Current

−3

Normal Operation

−0.2

19.5

SOS

Reference Current

LIMSET

RLIMSET

Current Sense Amplifier Hysteresis

Current Sense Amplifier Series Offset

HYST

SOS

HI/LO = V , V

> 0.5 V

DD CMR

Power On Reset

RESET Output Voltage

= 1 mA, V > 2 V

0.4

OP(rst)

OUT DD

RESET Output Hysteresis

HYST

See Note c

RESET Comparator Input Threshold

1.223

1.250

1.277

RST

Document Number: 70028

S-40754—Rev. D, 19-Apr-04

www.vishay.com

Si9750

Vishay Siliconix

SPECIFICATIONS

Test Conditions Unless Specified

Limits

0 to 70_C

Typ^b

2.9 V v V v 13.2 V

HI/LO = GND, R

= 12.5 kW

BIAS

Parameter

Symbol

Min^a

Max^a

Unit

= 100 mH, C

= 100 nF

BOOST

Power On Reset

RESET Comparator Offset Voltage

RESET Comparator Input Bias Current

RESET Timer Delay

0.5

−0.2

150

130

RBIAS

BIAS

RST

= 15 nF, See Figure 8

110

190

200

RSTD

RETRY

= 100 nF

RETRY

Notes

a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.

b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production test.

c. In a practical situation, V

is multiplied by ratio of a resistor divider chain. For V = 13.2 V, V

= 20 mV.

HYST

d. The RESET comparator input threshold specification (V

) includes theRESET comparator offset voltage.

RST

PIN CONFIGURATION AND ORDERING INFORMATION

SOIC-16

BOOST

COIL

GND

ORDERING INFORMATION

GATE

LOAD

RST

Part Number

Temperature Range

Package

RETRY

Si9750CY

SENSE

LIMSET

HI/LO

RESET

Si9750CY-T1

Si9750CY-T1—E3

0 to 70_C

SOIC-16

STATUS

RST

ENABLE

BIAS

Top View

PIN DESCRIPTION

Pin Number

Function

Description

BOOST

Output of on-chip Boost converter. A 100-nF capacitor should be connected between BOOST and GND

Positive supply pin.

GATE

LOAD

Connection to external power MOSFET gate.

Connection to positive supply side of LOAD.

Connects external sense resistor of a sensefet sense pin to SENSE input of overcurrent trip comparator. A standard

MOSFET may also be used in conjunction with a low ohmic value shunt resistor.

SENSE

LIMSET

HI/LO

Connects overcurrent limit set resistor R

to the reference input of overcurrent trip comparator.

LIMSET

CMOS logic input to control the overcurrent trip comparator sensitivity at power-on. HI/LO should be connected to GND

for low Capacitive loads and to V for high capacitive loads.

ENABLE

CMOS logic input to turn IC on or off. GATE voltage remains low when ENABLE is high.

A resistor connected from this pin to GND programs the reference bias current for the overcurrent trip comparator

BIAS

resistor R

and the GATE

charge current. See Functional Description for equations.

LIMSET

(on)

Input to voltage monitor comparator.

RST

Open drain NMOS output. This pin is driven low when the current limiter is enabled and the LOAD voltage is greater than

STATUS

RESET

90% of V

Open drain NMOS output. This pin is driven low during power on reset or when V

reference.

is lower than the internal 1.25-V

RST

A capacitor connected from this pin to GND programs the retry timer.

A capacitor connected from this pin to GND programs the reset timer.

Negative supply pin.

RETRY

RST

GND

COIL

Connection to Boost converter inductor.

Document Number: 70028

S-40754—Rev. D, 19-Apr-04

www.vishay.com

Si9750

Vishay Siliconix

FUNCTIONAL DESCRIPTION

The Si9750 together with an n-channel MOSFET provides the

following functions:

If the HI/LO pin is tied low the current limit is 20% higher during

turn-on than the steady state current limit point.

D limits di/dt current for hot insertion applications

D provides complete short circuit protection

x R

> 1.2 x I

x R

LOAD

SENSE

BIAS LIMSET

(2)

(with pin HI/LO=Low)

D high-side drive allows n-channel MOSFET to be

used, for lower power dissipation

If a higher current limit is needed at start-up, the HI/LO pin can

be tied high. The equation becomes:

D industry-standard microprocessor reset function

D logic control input and outputs

x R

>1.2 x I

x R

(3)

LOAD

SENSE

BIAS

LIMSET

+ I

BIAS

(1 kW + R )

Setting the Current Limit

(HI/LO = High)

(SENSE, HI/LO pins, R_LIMSET, R_SENSE

)

The current limit point is determined by the voltage across

R_SENSE, the value of R_LIMSET, and the bias current. The

current limit circuit is shown in Figure 1

Notice that any current limit can be set at turn-on using an

optional resistor, R_HI.

Relaxation Mode Current Limit

(C_RETRYpin)

The steady state current is set by the equation:

In an overload condition, the Si9750 will go into a relaxation

mode current limit operation that not only protects the source

and load, but also reduces the power dissipated in the

MOSFET. When an overload is detected, the circuit quickly

turns off, then goes into a retry mode whereby the current is

ramped up slowly. If the fault still exists, the current will ramp

down again. This sequence will repeat indefinitely at a period

defined by 10⁶x C_RETRYuntil the fault is removed. Typically,

x R

> I

x R

LIMSET

(1)

LOAD

SENSE

BIAS

Due to the highly capacitive nature of some loads, the Si9750

has an option to increase the current limit point to a much

higher level at turn-on. In this case, turn-on is defined as V_GATE

< V_DD+ 7.8 V. This function is implemented with the HI/LO pin.

capacitors in the range of 1 nF to 1 mF can be used on C_RETRY

but the period should be >50 ms.

Si9750

BIAS

Overcurrent

HI/LO

−

1 kW, "20%

SENSE

GATE

LIMSET

HI/LO

LIMSET

(Optional)

LOAD

SENSE

LOAD

330 W

33 nF

FIGURE 1.

Document Number: 70028

S-40754—Rev. D, 19-Apr-04

www.vishay.com

Si9750

Vishay Siliconix

FUNCTIONAL DESCRIPTION (CONT’D)

di/dt Limiting On Hot and Cold Insertion (GATE pin)

boost inductor should typically be 100 mH, <3.5 W, >180 mA

dc, and the boost capacitor should be 100 nF.

The GATE pin provides a constant current source that is used

to control the rate of rise of the gate of the MOSFET, and hence

to control the di/dt of the load and source current. The equation

that governs the gate current is:

Logic Control

(STATUS, ENABLE, RESET, V_RSTand C_RSTpins)

R_BIAS

STATUS. The status monitor detects when the load voltage is

I_SOURCE+ 1.25 V x

+ 1.2 mA

(4)

90% of input voltage, V_LOAD> 0.9 x V_DD. This pin is an

open-drain NMOS output, capable of sinking 200 mA at V_OL

(for R

= 12.5 kW)

BIAS

0.4 V. If this pin is used in conjunction with the ENABLE of

another unit, power supply sequencing (or daisy-chaining) is

easily implemented.

Typically, a 33-nF capacitor should be connected from the

GATE pin to ground. If a large I_SOURCEis needed for high di/dt,

a 330-W resistor in series with C_GATEmay be necessary to

prevent oscillation. In the case that V_DD> 6 V, a resistor of

approximately 330 W is also recommended in series with the

gate. (Figure 1)

ENABLE. This CMOS logic compatible input serves as the

on/off control pin. This pin has 40-mA minimum pull-up to V_DD

RESET (V_RST, C_RST, RESET pins). This is a standard

implementation of the microprocessor reset function.

comparator looks at the voltage on V_RSTpin and compares it

with 1.25 V. This function is programmable by using an

external voltage divider. When V_RSTis higher than 1.25 V, the

reset signal is delayed by the C_RSTpin, defined by Equation (6)

and then goes high. (Figure 2)

Reference Bias Current

(R_BIASpin)

This pin sets the internal current used by R_LIMSETto determine

all the current limit points. Typically R_BIAS= 12.5 kW which sets

a 20-mA bias current. The equation which relates R_BIASto I_BIAS

is:

Reset delay t

[ 10 x C

(6)

RSTD

RST

1.25 V

5 x R_BIAS

I_BIAS

+ 20 mA

(5)

(for R

= 12.5 kW)

BIAS

HI/LO Pin

Power on Reset (POR)

(V_DDpin)

LIMSET

RETRY

Current

This function monitors the voltage on the V_DDpin and signals

the system if all input voltage requirements have been met. At

turn-on when V_DD> 2.7 V " 200 mV, a POR signal is

generated for a duration of 100 ms. After this point the system

is released into operation. If V_DDfalls below 2.7 V " 200 mV,

a second POR signal will be generated. If two POR signals are

detected, this indicates that the source for V_DDis not capable

of supplying the load current. The IC then turns off the

MOSFET and initiates its retry period, hence fully protecting

the MOSFET from an over-power condition.

Short Circuit

Applied to Output

Turn-On

GATE

> V + 7.8 V

Current Limit Point

LOAD

Boost Converter

(COIL, BOOST pins)

FIGURE 2. Typical Operation Under Start-up Condition With

An Overcurrent Fault Applied to the Output

The boost converter generates the gate drive for the external

n-channel MOSFET. This is limited to typically V_DD+ 11 V. The

Document Number: 70028

S-40754—Rev. D, 19-Apr-04

www.vishay.com

Si9750

Vishay Siliconix

TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED)

Gate-Source Drive Current vs. R

Gate-Sink vs. V

BIAS

3.0

2.8

2.6

2.4

2.2

2.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

2.80

4.88

6.96

9.04

(V)

11.12

13.20

(kW)

BIAS

Current vs. R

RESET Timer Delay vs. C

RESET

LIMSET

BIAS

400

300

200

100

(kW)

(nF)

RST

BIAS

RETRY Delay vs. C

RETRY

600

500

400

300

200

100

100 150 200 250 300 350 400

(nF)

RETRY

Document Number: 70028

S-40754—Rev. D, 19-Apr-04

www.vishay.com

Si9750

Vishay Siliconix

SWITCHING TIME TEST CIRCUITS

ENABLE

0.7 V

OFF

0.3 V

SOURCE

50 %

SINK

FIGURE 3. Normal-Mode Operation

ENABLE

BOOST

90 %

−V

BOOST DD

ON(bst)

50 %

SOURCE

FIGURE 4. Timing Definition with ENABLE Already On

FIGURE 5. Start of Boost Converter

RETRY

LOAD

Threshold

SENSE

OFF(isc)

OFF(sc)

SOURCE

1 V

50%

SINK

FIGURE 6. First Short Circuit

FIGURE 7. Relaxation-Mode Current Limit

Status Threshold

LOAD

STDLY

STATUS

0.3 x V

RSTD

RESET(2)

(2) With reset input divider correctly set, monitoring V

LOAD

FIGURE 8. STATUS and RESET

Document Number: 70028

S-40754—Rev. D, 19-Apr-04

www.vishay.com

Legal Disclaimer Notice

Vishay

Notice

Specifications of the products displayed herein are subject to change without notice. Vishay Intertechnology, Inc.,

or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies.

Information contained herein is intended to provide a product description only. No license, express or implied, by

estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Vishay's

terms and conditions of sale for such products, Vishay assumes no liability whatsoever, and disclaims any express

or implied warranty, relating to sale and/or use of Vishay products including liability or warranties relating to fitness

for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.

The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications.

Customers using or selling these products for use in such applications do so at their own risk and agree to fully

indemnify Vishay for any damages resulting from such improper use or sale.

Document Number: 91000

Revision: 08-Apr-05

www.vishay.com

SI9750CY-T1-E3 [VISHAY]

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