T15V2M08A-70P [TMT]
256K X 8 LOW POWER CMOS STATIC RAM; 256K ×8低功耗CMOS静态RAM
| 型号： | T15V2M08A-70P |
| 厂家： | 
TAIWAN MEMORY TECHNOLOGY |
| 描述： | 256K X 8 LOW POWER CMOS STATIC RAM |
| 文件： | 总12页 (文件大小：85K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TE
CH
Preliminary T15V2M08A
256K X 8 LOW POWER
CMOS STATIC RAM
SRAM
FEATURES
Low-power consumption
GENERAL DESCRIPTION
·
The T15V2M08A is a very Low Power
CMOS Static RAMorganizedas 262,144 words by
8 bits . This device is fabricated by high
performance CMOS technology. It can be
operated under wide power supply voltage range
from +2.7V to +3.6V.
- Active: 40mA at 55ns
- Stand-by: 5uA (CMOS input/output)
55/70/100 ns access time
·
·
·
·
·
·
·
Equal access and cycle time
Single +2.7V to 3.6V Power Supply
TTL compatible , Tri-state output
Common I/O capability
The T15V2M08A inputs and three-state
outputs are TTL compatible and allow for direct
interfacing with common system bus structures.
Data retention is guaranteed at a power supply
voltage as low as 2V.
Automatic power-down when deselected
Available in 32-pin TSOP-I (8x20mm) ,
TSOP-I(8x13.4mm) , 48-pin CSP packages
PART NUMBER EXAMPLES
Vcc
Vss
PART NO.
PACKAGE CODE
H = TSOP-I(8x20)
P= TSOP-I(8x13.4)
T15V2M08A-55H
T15V2M08A-70P
CORE
A0
DECODER
ARRAY
.
.
.
T15V2M08A-100C C = CSP
A17
WE
OE
I/O1
CONTROL
CIRCUIT
.
DATA I/O
.
CE1
CE2
I/O8
BLOCK DIAGRAM
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
PIN CONFIGURATIONS
A 1 1
A 9
1
2
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
O E
A 1 0
C E 1
I / O 8
I / O 7
I / O 6
I / O 5
I / O 4
V S S
I / O 3
I / O 2
I / O 1
A 0
A 8
3
A 1 3
4
W
E
5
C E 2
A 1 5
V D D
A 1 7
A 1 6
A 1 4
A 1 2
A 7
6
T S O P - I
( 8 x 2 0 m m )
&
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
( 8 x 1 3 . 4 m m )
A 6
A 1
A 5
A 2
A 4
A 3
1
2
3
4
5
6
A 0
A 1
C E 2
A 3
A 6
A 8
A
B
C
D
E
I / O 5
I / O 6
V S S
V D D
I / O 7
I / O 8
A 9
A 2
W E
N C
A 4
A 5
A 7
I / O 1
I / O 2
V D D
V S S
I / O 3
I / O 4
A 1 4
4 8 - C S P
T O P V I E W
N C
C E 1
A 1 1
A 1 7
A 1 6
A 1 2
F
O E
A 1 5
A 1 3
G
H
A 1 0
PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A17 Address inputs
SYMBOL DESCRIPTIONS
Output enable input
Power supply
Ground
OE
I/O0~I/O8 Data inputs/outputs
V
DD
Chip enable
V
SS
CE2
,
CE1
WE
Write enable input
NC
No connection
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 2
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on Any Pin Relative to Gnd
Power Dissipation
SYM
MIN.
-0.5
-
MAX.
+4.6 V
0.7
UNIT
V
R
V
PD
W
TSTG
IBIAS
Storage Temperature
-55
-40
+150
+85
°C
°
C
Temperature Under Bias
*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and function operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
WE
OE
CE2
DATA
MODE
Standby
Standby
CE
H
X
L
1
X
L
X
X
H
H
L
X
X
L
High-Z
High-Z
H
H
H
Data Out
High-Z
Active, Read
Active, Output Disable
Acitve, Write
L
H
X
L
Data In
*Note: X = Don’t Care, L = Low, H = High
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
OPERATING CHARACTERISTICS
(Vcc = 2.7 to 3.6V, Gnd = 0V, Ta = -40 C to 85 C)
°
°
-55
-70
-100
PARAMETER SYM.
TEST CONDITIONS
UNIT
Min Max Min Max Min Max
Input Leakage
Vcc = Max,
VIN = Gnd to Vcc
½ILI½
-
1
-
1
-
1
uA
Current
CE1 = VIH or CE2= VIL
OE
WE
or
or
= VIH
Output Leakage
½ILO½
-
1
-
1
-
1
uA
Current
= VIL
VOUT = Gnd to Vcc
CE1
WE
= VIL,CE2= VIH,
OE
=VIH,
= VIH ,
Operating Power
ICC
-
-
2
-
-
2
-
-
2
mA
Supply Current
= V or VIL,
IN
V
IH
IOUT=0mA
Cycle time=1us,
100% duty, IOUT =0mA,
CE1 £
ICC1
0.2V,
3
3
3
mA
³
CE2 VCC-0.2V,
Average Operating
Current
VIN £ 0.2V
Cycle time=min,
100% duty, IOUT =0mA,
CE1 = VIL,CE2= VIH ,
VIN = VIH or VIL
ICC2
-
-
40
-
-
35
-
-
25
mA
mA
CE1
V
IH
Standby Power
Supply Current
(TTL Level)
=
ISB
CE2= VIL
0.5
0.5
0.5
CE1
³
Vcc-0.2V,
³
CE2 VCC-0.2V
Standby Power
Supply Current
(CMOS Level)
ISB1
or CE2 £ 0.2V
-
5
-
5
-
5
uA
£
VIN 0.2V or
³
VIN Vcc-0.2V
VOL
VOH
I
I
OL= 2.0mA
OH = -1.0 mA
-
0.4
-
-
0.4
-
-
0.4
-
V
V
Output Low Voltage
Output High Voltage
2.2
2.2
2.2
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
RECOMMENDED OPERATING CONDITIONS
(Ta = -40 C to 85 C**)
°
°
PARAMETER
Supply Voltage
SYM
Vcc
Gnd
VIH
MIN
2.7
TYP
3.0
0.0
-
MAX
3.6
UNIT
V
V
V
V
0.0
0.0
2.1
-0.3
Vcc+0.3
0.6
Input Voltage
V
-
IL
CAPACITANCE
(f = 1 MHz, Ta = 25°C,)
PARAMETER
Input Capacitance
SYMBOL
CONDITION
MAX.
UNIT
pF
CIN
CI/O
VIN
= 0V
6
8
VIN
V
= OUT= 0V
Input/ Output Capacitance
pF
Note:
This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER
Input Pulse Levels
CONDITIONS
0.6V to 2.1V
3.0 ns
Input Rise and Fall Times
Input and Output Timing Reference Level
1.4V
C
C
L =30pF+1TTL Load(55ns/70ns)
Output Load
L =100pF+1TTL Load(Load for 100ns)
AC TEST LOADS AND WAVEFORM
T T L
D Q
R L
C L
3 0 p F
5 0 o h m
C L
*
Z 0 = 5 0 o h m
V t = 1 . 4 V
F i g . A * I n c l u d i n g S c o p e a n d J i g C a p a c i t a n c e
F i g . B O u t p u t L o a d E q u i v a l e n t
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 5
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
(
=2.7 to 3.6V, Gnd = 0V, Ta = -40 C to 85 C)
° °
AC CHARACTERISTICS V
cc
(1) READ CYCLE
-55
-70
-100
PARAMETER
SYM.
UNIT
Min
55
-
Max
-
Min
70
-
Max
-
Min
Max
tRC
tAA
tACE
tOE
tOH
tLZ
Read Cycle Time
100
-
-
100
100
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Enable Access Time
55
55
30
-
70
70
35
-
-
-
-
Output Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
-
-
-
10
10
-
10
10
-
10
10
-
-
-
-
tHZ
tOLZ
20
-
20
25
-
25
30
-
30
5
-
5
-
5
-
Output Disable to Output in High-Z tOHZ
(2)WRITE CYCLE
-55
-70
-100
PARAMETER
SYM.
UNIT
Min
55
50
50
0
Max
Min
70
60
60
0
Max
Min
100
80
80
0
Max
tWC
tCW
tAW
tAS
Write Cycle Time
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to Write End
Address Valid to Write End
Address Setup Time
-
-
-
-
-
-
-
-
-
Write Pulse Width
tWP
tWR
tDW
tDH
tWHZ
tOW
45
0
50
0
70
0
Write Recovery Time
-
-
-
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
25
0
-
-
30
0
-
-
40
0
-
-
-
25
-
-
25
-
-
30
-
5
5
5
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 6
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled)
t
RC
A d d r e s s
t
AA
t
OH
D
O UT
Previous DataValid
DataValid
READ CYCLE 2
(Chip Enable Controlled)
C E 1
C E 2
tACE
tOLZ
tOHZ
D OUT
DON'T CARE
UNDEFINED
Notes (READ CYCLE) :
WE
1.
are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to
VOH or VOL levels.
4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device
and from device to device interconnection.
±
5. Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not
100% tested.
6. Device is continuously selected with CE1 =VIL .
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 7
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
WE
WRITE CYCLE 1 (
Controlled)
t
WC
A d d r e s
s
t
t
AW
t
WR
CW
C E 1
C E 2
t
t
WP
AS
W
E
t
WHZ
t
OW
D
O
U T
High-Z
t
t
DW
DH
D
I N
H i g h - Z
CE
WRITE CYCLE 2 (
Controlled)
t
WC
A d d r e s s
t
t
AW
WR
t
CW
C E 1
t
AS
C E 2
t
WP
W
E
D
H ig h -Z
H ig h -Z
O
U T
t
t
DW
DH
D
H i g h - Z
I N
D O N' T C A RE
U N DE FIN E D
NOTES ( WRITE CYCLE ) :
1. A write occurs during the overlap of a low
CE1
WE
. A write begins at
, a high CE2 and a low
CE1
WE
the lateat transition among
goes low, CE2 going high and
going low. A write end at the
going high. tWP is measured
CE1
WE
earliest transition among
going high, CE2 going low and
from the beginning of write to the end of write.
CE1
2. tCW is measured from the later of
going low or CE2 going high to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 8
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
DATA RETENTION CHARACTERISTICS
PARAMETER
SYM.
TEST
MIN.
MAX.
UNIT
CONDITION
CE1
VDD -0.2V
VCC for Data Retention
VDR
ICCDR
tCDR
tR
³
£
2.0
-
-
V
uA
ns
Data Retention Current
CE2 0.2V
5
-
³
Chip Deselect to Data Retention Time
Operation Recovery Time
VIN Vcc -0.2V or
0
£
RC
VIN 0.2V
t
-
ns
DATA RETENTION WAVEFORM
(Ta = -20 C to 85 C)
°
°
Data Retention Mode
Vcc_typ
R
Vcc_typ
t
V
> 2.0V
t
V c c
C E 1
DR
CDR
CE1 >Vcc- 0.2V
V
V
IH
IH
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 9
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
PACKAGE DIMENSIONS
32-LEAD TSOP-I (8x20mm)
SYMBOL
Dimension in inches
0.044(MAX)
0.004±0.002
0.041(MAX)
0.008±0.004
0.006±0.001
0.724±0.008
0.315±0.004
0.787±0.008
0.020(TYP.)
Dimension in mm
1.10(MAX)
0.05±0.05
1.02(MAX)
0.20±0.10
0.15±0.02
18.4±0.2
A
A1
A2
b
C
D
E
HD
e
L
L1
y
8.0±0.1
20.0±0.2
0.5(TYP.)
0.5±0.1
0.8±0.2
0.020±0.004
0.031±0.008
0.002(MAX)
0.05(MAX)
°
°
°
°
è
0 ~5
0 ~5
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 10
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
PACKAGE DIMENSIONS
32-LEAD TSOP-I (8x13.4mm)
SYMBOL
Dimension in inches
0.044(MAX)
0.004±0.002
0.041(MAX)
0.008±0.004
0.006±0.001
0.465±0.008
0.315±0.004
0.528±0.008
0.020(TYP.)
Dimension in mm
1.10(MAX)
0.05±0.05
1.02(MAX)
0.20±0.10
0.15±0.02
11.8±0.2
A
A1
A2
b
C
D
E
HD
e
L
L1
y
8.0±0.1
13.4±0.2
0.5(TYP.)
0.5±0.1
0.8±0.2
0.020±0.004
0.031±0.008
0.002(MAX)
0.05(MAX)
°
°
° °
0 ~5
è
0 ~5
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 11
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V2M08A
Units : millimeters
PACKAGE DIMENSIONS
48-pin CSP (8 row x 6 column)
48 BALL FINE PITCH BGA (0.75mm ball pitch)
Bottom View
Top V iew
A1 INDEX MARK
B
0. 50
B 1
#A1
B /2
A
Y
E 2
D
0.30
E
E1
Symbol
A
min
typ
0.75
6.00
3.75
8.00
5.25
0.30
1.10
0.95
0.25
-
max
-
-
5.95
6.05
-
Notes :
B
1. Bump counts : 48 (8 row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75) typ.
3. All tolerance are ±0.050 unless otherwise specified.
4. ‘Y’ is coplanarity : 0.08(max)
5. Units : mm
-
B1
C
7.95
8.05
-
-
C1
D
0.25
0.35
1.20
-
-
E
-
0.20
-
E1
E2
Y
0.30
0.08
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 12
Publication Date: MAR. 2001
Revision:0.A
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