T15V2M16B-55SI [TMT]
128K X 16 LOW POWER CMOS STATIC RAM; 128K ×16低功耗CMOS静态RAM
| 型号： | T15V2M16B-55SI |
| 厂家： | 
TAIWAN MEMORY TECHNOLOGY |
| 描述： | 128K X 16 LOW POWER CMOS STATIC RAM |
| 文件： | 总12页 (文件大小：95K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TE
tmCH
T15V2M16B
128K X 16 LOW POWER
CMOS STATIC RAM
SRAM
FEATURES
• Access time : 45/55/70/100 ns
• Low-power consumption
GENERAL DESCRIPTION
The T15V2M16B is a very Low Power CMOS
Static RAM organized as 131,072 words by 16
Active: 5mA (ICC1
Stand-by: (CMOS input/output)
Max.. 15 uA for 55/70/100ns
Max.. 40 uA for 45ns
)
-
-
bits
.
This device is fabricated by high
performance CMOS technology. It can be operated
under wide power supply voltage range from
+2.7V to +3.6V.
• Equal access and cycle time
• Single +2.7V to 3.6V Power Supply
• TTL compatible , Tri-state output
• Common I/O capability
The T15V2M16B inputs and three-state
outputs are TTL compatible and allow for direct
interfacing with common system bus structures.
Data retention is guaranteed at a power supply
voltage as low as 2V.
• Automatic power-down when deselected
• Available in 44-PIN TSOP-II and 48-pin CSP
packages
• Operating temperature :
-
-
-10 ~ +70 °C
-40 ~ +85 °C
BLOCK DIAGRAM
PART NUMBER EXAMPLES
PART NUMBER
T15V2M16B-55S
T15V2M16B-70C
T15V2M16B-55SI
T15V2M16B-70CI
PACKAGE Temperature
Vcc
Vss
-10 ~ +70 °C
-10 ~ +70 °C
-40 ~ +85 °C
-40 ~ +85 °C
TSOP-II
CSP
CORE
ARRAY
DECODER
A0
.
.
.
TSOP-II
CSP
A16
CE
WE
OE
LB
CONTROL
CIRCUIT
I/O1
.
.
.
DATA I/O
UB
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
PIN CONFIGURATIONS
A5
A6
A7
OE
UB
LB
A4
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
A3
2
A2
3
A1
4
A0
5
CE
6
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A8
A9
A10
A11
NC
I/O1
7
I/O2
8
I/O3
9
I/O4
10
VCC
11
TSOP-II
VSS
I/O5
I/O6
I/O7
I/O8
WE
A16
A15
A14
A13
A12
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
LB
OE
A0
A1
A2
NC
A
B
C
D
E
F
I/O9
I/O10
VSS
VCC
I/O15
I/O16
NC
UB
I/O11
I/O12
I/O13
I/O14
NC
A3
A5
A4
A6
A7
CE
I/O1
I/O3
VCC
VSS
I/O7
I/O8
NC
I/O2
NC
NC
A14
A12
A9
I/O4
I/O5
I/O6
WE
A16
A15
A13
A10
G
H
A8
A11
48-Ball CSP TOP VIEW (Ball Down)
PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A16 Address inputs
I/O1~I/O16 Data inputs/outputs
SYMBOL DESCRIPTIONS
Lower byte (I/O 1~8)
Upper byte (I/O 9~16)
Power supply
LB
UB
Chip enable
VCC
VSS
NC
CE
WE
OE
Write enable input
Output enable input
Ground
No connection
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 2
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on Any Pin Relative to VSS
Power Dissipation
SYM
VR
PD
MIN.
-0.2
MAX.
+4.6 V
1.0
UNIT
V
-
W
TSTG
IBIAS
Storage Temperature
-55
+150
°C
Temperature Under Bias
-10 / -40
+70 / +85
°C
*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and function operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
I/O 1~8
I/O 9~16
MODE
Power
Standby
Standby
Active
Active
Active
Active
Active
Active
Active
Active
OE
X*
X*
H
WE
X*
X*
H
LB
X*
H
UB
X*
H
CE
H
X*
L
High-Z
High-Z
High-Z
High-Z
Data Out
High-Z
Data Out
Data In
High-Z
Data In
High-Z
High-Z
High-Z
High-Z
High-Z
Data Out
Data Out
High-Z
Data In
Data In
Deselected
Deselected
L
X*
L
Output Disabled
Output Disabled
Lower Byte Read
Upper Byte Read
Word Read
L
H
H
X*
L
L
L
H
H
L
L
H
H
L
L
L
H
L
L
L
X*
X*
X*
L
L
H
Lower Byte Write
Upper Byte Write
Word Write
L
L
H
L
L
L
L
L
*Note: X = Don’t Care (Must be low or high state), L = Low, H = High
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
RECOMMENDED OPERATING CONDITIONS
-
(Ta = -10 ~ +70 °C / -40°C ~ 85°C)
PARAMETER
SYM
Vcc
VSS
MIN
2.7
TYP
3.0
0.0
-
MAX
3.6
UNIT
V
V
V
V
Supply Voltage
Input Voltage
0.0
0.0
V
0.7Vcc
-0.2
Vcc+0.3
0.6
IH
V
-
IL
OPERATING CHARACTERISTICS
-
(Vcc = 2.7 to 3.6V, VSS = 0V, Ta = -10 ~ +70 °C / -40°C ~ 85°C)
-45
-55
-70
-100
PARAMETER SYM.
TESTCONDITIONS
UNIT
Min Max Min Max Min Max Min Max
Input Leakage
ILI
Vcc = Max,
-
1
-
1
-
1
-
1
uA
uA
V
= VSS to Vcc
Current
IN
CE= VIH or OE= VIH
Output Leakage
ILO
-
1
-
1
-
1
-
1
or WE = VIL
Current
VIO = VSS to Vcc
CE = VIL,
Operating Power
ICC
WE =VIH, OE= VIH ,
= VIH or VIL,
VIN
-
-
3
5
-
-
3
5
-
-
3
5
-
-
3
5
mA
mA
Supply Current
IOUT=0mA
Cycle time=1us,
100% duty, IIO=0mA,
ICC1
CE ≤ 0.2V,
VIN ≥ VCC-0.2V
or VIN ≤ 0.2V
Average Operating
Current
Cycle time=min,
100% duty, IIO=0mA,
ICC2
-
-
-
45
0.3
40
-
-
-
40
0.3
15
-
-
-
35
0.3
15
-
-
-
25 mA
0.3 mA
CE = VIL,
VIN = VIH or VIL
V
or
CE =
Standby Power
IH
ISB
Supply Current
(TTL Level)
LB = UB =V
IH
other input= VIL or V
IH
CE ≥ Vcc-0.2V or
LB = UB ≥Vcc-0.2V,
Standby Power
Supply Current
(CMOS Level)
ISB1
15
uA
V
V
≤ 0.2V or
IN
IN
≥ Vcc-0.2V
VOL
VOH
I
I
OL = 2.1mA
-
0.4
-
-
0.4
-
-
0.4
-
-
0.4
-
V
V
Output Low Voltage
Output High Voltage
OH = -1.0 mA
2.2
2.2
2.2
2.2
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
CAPACITANCE
(f = 1 MHz, Ta = 25°C,)
PARAMETER
Input Capacitance
SYMBOL
CIN
CONDITION
= 0V
MAX.
UNIT
pF
V
8
IN
CI/O
V
=VOUT= 0V
Input/ Output Capacitance
10
pF
IN
Note: This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER
CONDITIONS
Input Pulse Levels
0.6V to 0.7Vcc
3.0 ns
Input Rise and Fall Times
Input and Output Timing Reference Level
1.4V
CL =30pF+1TTL Load(45/55/70ns)
CL =100pF+1TTL Load(Load for 100ns)
Output Load
AC TEST LOADS AND WAVEFORM
TTL
DQ
RL
CL
30 pF
50 ohm
CL*
Z0 = 50 ohm
Vt =1.4V
Fig.A * Including Scope and Jig Capacitance
Fig.B Output Load Equivalent
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 5
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
AC CHARACTERISTICS(V =2.7 to 3.6V, V
= 0V, Ta = -10 ~ +70 °C / -40°C ~ 85°C)
cc
SS
(1) READ CYCLE
-45
-55
-70
-100
PARAMETER
SYM.
UNIT
Min Max Min Max Min Max Min Max
tRC
Read Cycle Time
45
-
-
45
45
25
-
55
-
-
55
55
30
-
70
-
-
70
70
35
-
100
-
-
100
100
50
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACE
tOE
Address Access Time
Chip Enable Access Time
-
-
-
-
Output Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
LB , UB Access Time
-
-
-
-
tOH
tLZ
10
10
-
10
10
-
10
10
-
10
10
-
-
-
-
-
tHZ
15
-
20
-
25
-
30
-
tOLZ
tOHZ
tBA
tBLZ
5
5
5
5
-
15
45
-
-
20
55
-
-
25
70
-
-
30
100
-
-
-
-
-
LB , UB Enable to Output in Low-Z
LB , UB Disable to Output in
High-Z
10
10
10
10
tBHZ
-
15
-
20
-
25
-
30
ns
(2)WRITE CYCLE
-45
-55
-70
-100
PARAMETER
SYM.
tWC
UNIT
Min Max Min Max Min Max Min Max
Write Cycle Time
45
35
35
0
-
-
55
50
50
0
-
-
70
60
60
0
-
-
100
80
80
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCW
tAW
tAS
Chip Enable to Write End
Address Valid to Write End
Address Setup Time
-
-
-
-
-
-
-
-
tWP
tWR
tDW
tDH
Write Pulse Width
30
0
-
45
0
-
50
0
-
70
0
-
Write Recovery Time
-
-
-
-
Data Valid to Write End
Data Hold Time
20
0
-
25
0
-
30
0
-
40
0
-
-
-
-
-
tWHZ
tOW
Write Enable to Output in High-Z
Output Active from Write End
-
15
-
-
20
-
-
25
-
-
30
-
5
5
5
5
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 6
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled, CE = OE = VIL , WE =V , LB or/and UB = VIL )
IH
t
RC
A d d r e s s
t
AA
t
OH
D
O U T
Previous Data Valid
Data Valid
READ CYCLE 2 (WE =V )
IH
tRC
A d d r e s s
tAA
tOH
tACE
C E
tHZ
tBA
UB
/
L B
tBHZ
tOE
O E
tOLZ
tOHZ
tBLZ
tLZ
D
OUT
High-Z
DON'T CARE
UNDEFINED
Notes (READ CYCLE) :
1. WE are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to
V
OH or VOL levels.
4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device
and from device to device interconnection.
5. Transition is measured ±200mV from steady state voltage with load. This parameter is sampled and not
100% tested.
6. Device is continuously selected with CE =VIL .
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 7
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
WRITE CYCLE 1 (WE Controlled)
t
WC
Ad d r e s s
t
t
WR
AW
t
CW
C E
L B
U B
/
t
t
WP
AS
W E
t
WHZ
t
OW
D
O U T
High-Z
t
t
DW
DH
D
High-Z
I N
WRITE CYCLE 2 (CE Controlled)
t
WC
A d d r e s s
t
t
WR
AW
t
CW
C E
t
AS
U B
/
L B
t
WP
W E
D
Hig h -Z
Hig h -Z
O U T
t
t
DH
DW
D
Hig h -Z
I N
DON'T CARE
UNDEFINED
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 8
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
WRITE CYCLE 3 (UB,LB Controlled)
t
WC
A d d r e s s
t
t
WR
AW
t
CW
U B
/ L B
t
AS
C E
t
WP
W E
D
Hig h -Z
Hig h -Z
O U T
t
t
DH
DW
D
Hig h -Z
I N
DON'T CARE
UNDEFINED
NOTES ( WRITE CYCLE ) :
1. A write occurs during the overlap of a low CE , a low WE . A write begins at the lateat
transition among CE goes low, WE going low. A write end at the earliest transition among
CE going high, WE going high. tWP is measured from the beginning of write to the end of
write.
2. tCW is measured from the later of CE going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 9
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Deselect to Data Retention
Time
SYM.
VDR
TEST CONDITION
CE ≥VCC -0.2V
VIN ≥ Vcc -0.2V or
VIN ≤ 0.2V
MIN.
MAX.
UNIT
V
2.0
-
-
15/40*
-
ICCDR
tCDR
uA
ns
0
Operation Recovery Time
tR
tRC
-
ns
*note : the data retention current ‘max=40uA’ only for –45ns .
DATA RETENTION WAVEFORM
(Ta = -10 ~ +70 °C / -40°C ~ 85°C)
Data Retention Mode
Vcc_typ
Vcc_typ
t
V
> 2.0V
V c c
C E
DR
t
CDR
R
CE >Vcc- 0.2V
V
V
IH
IH
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 10
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
PACKAGE DIMENSIONS
44-LEAD TSOP-II
D
44
23
E2
E
E1
L1
b1
22
INDEX MARK
Mirror finish
c
e
b
A
£c
A3
A2
A1
SEATING PLANE
c1
L
Dimension in mm
Dimension in inch
Symbol
Min
Nom
-
Max
1.20
Min
Nom
-
Max
0.047
A
A1
A2
A3
b
b1
c
c1
D
-
-
0.05
-
0.1
0.002
-
0.004
0.95
1.00
1.05
0.037
0.039
0.010
0.014(typ)
0.006
0.032
0.004
0.725
0.031(typ)
0.463
0.400
0.458
0.020
0.032(typ)
-
0.041
-
-
0.25
-
-
-
-
-
-
0.35(typ)
0. 15
0.805
0.10
0.10
0.25
0.004
0.010
-
-
-
-
-
-
-
-
18.31
18.41
0.80(typ)
11.76
10.16
10.76
0.5
18.51
0.721
0.729
e
E
-
-
-
-
11.56
10.03
11.96
10.29
0.455
0.394
0.471
0.405
E1
E2
L
L1
θ
-
0.4
-
-
0.6
-
-
-
0.016
0.024
0.8(typ)
-
-
0
-
8
0
8
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 11
Publication Date: NOV. 2002
Revision:A
TE
tmCH
T15V2M16B
PACKAGE DIMENSIONS
Units : millimeters
48-pin CSP (8 row x 6 column)
48 BALL FINE PITCH BGA (0.75mm ball pitch)
Bottom View
Top View
A1 INDEX MARK
0.50
B
B1
#A1
B/2
A
Y
E2
D
0.36
E
E1
Symbol
A
min
typ
0.75
6.00
3.75
8.00
5.25
0.30
1.10
0.95
0.25
-
max
-
-
5.95
6.05
-
B
Notes :
-
B1
C
1. Bump counts : 48 (8 row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75) typ.
3. All tolerance are ±0.050 unless otherwise specified.
4. ‘Y’ is coplanarity : 0.08(max)
5. Units : mm
7.95
8.05
-
-
C1
D
0.25
0.35
1.20
-
-
E
-
0.20
-
E1
E2
Y
0.30
0.08
TM Technology Inc. reserves the right
to change products or specifications without notice.
P. 12
Publication Date: NOV. 2002
Revision:A
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