T15V4M16A [TMT]

256K X 16 LOW POWER CMOS STATIC RAM; 256K ×16低功耗CMOS静态RAM
T15V4M16A
型号: T15V4M16A
厂家: TAIWAN MEMORY TECHNOLOGY    TAIWAN MEMORY TECHNOLOGY
描述:

256K X 16 LOW POWER CMOS STATIC RAM
256K ×16低功耗CMOS静态RAM

文件: 总12页 (文件大小:92K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
TE  
tm
CH  
Preliminary T15V4M16A  
256K X 16 LOW POWER  
CMOS STATIC RAM  
SRAM  
FEATURES  
Low-power consumption  
GENERAL DESCRIPTION  
·
The T15V4M16A is a very Low Power  
CMOS Static RAMorganized as 262,144 words by  
16 bits. That operates on a wide voltage range  
from 2.7V to 3.6V power supply, Fabricated using  
high performance CMOS technology, Inputs and  
three-state outputs are TTL compatible and allow  
for direct interfacing with common system bus  
structures. Data retention is guaranteed at a power  
supply voltage as low as 1.5V.  
Active: 5mA (ICC1  
)
-
-
Stand-by: 10uA (CMOS input/output)  
55/70/100 ns access time  
·
·
·
·
·
·
·
Equal access and cycle time  
Single +2.7V to 3.6V Power Supply  
TTL compatible , Tri-state output  
Common I/O capability  
Automatic power-down when deselected  
Available in 44-PIN TSOP-II and 48-pin CSP  
packages  
BLOCK DIAGRAM  
PART NUMBER EXAMPLES  
Vcc  
Vss  
PART NO.  
PACKAGE CODE  
S = TSOP-II  
C = CSP  
CORE  
ARRAY  
T15V4M16A-55S  
T15V4M16A-70C  
T15V4M16A-100C  
A0  
DECODER  
.
.
.
A17  
CE  
WE  
OE  
LB  
CONTROL  
CIRCUIT  
I/O1  
.
.
.
DATA I/O  
I/O16  
UB  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 1  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
PIN CONFIGURATIONS  
A5  
A6  
A7  
OE  
UB  
LB  
I/O16  
I/O15  
I/O14  
I/O13  
VSS  
VCC  
I/O12  
I/O11  
I/O10  
I/O9  
NC  
A4  
A3  
A2  
A1  
A0  
CE  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
I/O1  
I/O2  
I/O3  
I/O4  
VCC  
VSS  
I/O5  
I/O6  
I/O7  
I/O8  
WE  
A16  
A15  
A14  
A13  
A12  
TSOP-II  
A8  
A9  
A10  
A11  
A17  
1
2
3
4
5
6
LB  
OE  
A0  
A1  
A2  
NC  
A
B
C
D
E
F
I/O9  
I/O10  
VSS  
UB  
A3  
A5  
A4  
A6  
A7  
CE  
I/O1  
I/O3  
I/O11  
I/O12  
I/O13  
I/O14  
NC  
I/O2  
A17  
NC  
A14  
A12  
A9  
VCC  
VSS  
I/O7  
I/O8  
NC  
I/O4  
I/O5  
I/O6  
WE  
VCC  
I/O15  
I/O16  
NC  
A16  
A15  
A13  
A10  
G
H
A8  
A11  
48-Ball CSP TOP VIEW (Ball Down)  
PIN DESCRIPTIONS  
SYMBOL DESCRIPTIONS  
A0 ~ A17 Address inputs  
I/O1~I/O16 Data inputs/outputs  
SYMBOL DESCRIPTIONS  
Lower byte (I/O 1~8)  
Upper byte (I/O 9~16)  
Power supply  
LB  
UB  
Chip enable  
VCC  
CE  
Write enable input  
Output enable input  
V
Ground  
WE  
OE  
SS  
NC  
No connection  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 2  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
ABSOLUTE MAXIMUM RATINGS*  
PARAMETER  
Voltage on Any Pin Relative to VSS  
Power Dissipation  
SYM  
MIN.  
-0.2  
-
MAX.  
+3.6 V  
1.0  
UNIT  
V
R
V
PD  
W
TSTG  
IBIAS  
Storage Temperature  
-55  
-40  
+150  
+85  
°C  
°
C
Temperature Under Bias  
*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to  
the device. This is a stress rating only and function operation of the device at these or any other  
conditions outside those indicated in the operational sections of this specification is not implied.  
Exposure to absolute maximum rating conditions for extended periods may affect reliability.  
TRUTH TABLE  
OE WE LB  
UB  
I/O 1~8  
I/O 9~16  
MODE  
Power  
Standby  
Standby  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
Active  
CE  
H
X*  
L
X*  
X*  
H
X*  
X*  
H
H
H
H
H
L
X*  
H
L
X*  
H
X*  
L
High-Z  
High-Z  
High-Z  
High-Z  
Data Out  
High-Z  
Data Out  
Data In  
High-Z  
Data In  
High-Z  
High-Z  
High-Z  
High-Z  
High-Z  
Data Out  
Data Out  
High-Z  
Data In  
Data In  
Deselected  
Deselected  
Output Disabled  
Output Disabled  
Lower Byte Read  
Upper Byte Read  
Word Read  
L
H
X*  
L
H
L
L
L
L
L
H
L
L
L
L
L
L
X*  
X*  
X*  
L
H
L
Lower Byte Write  
Upper Byte Write  
Word Write  
L
H
L
L
L
L
*Note: X = Dont Care (Must be low or high state), L = Low, H = High  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 3  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
RECOMMENDED OPERATING CONDITIONS  
(Ta = -40°C to 85°C**)  
PARAMETER  
Supply Voltage  
SYM  
Vcc  
VSS  
MIN  
2.7  
TYP  
3.0  
0.0  
-
MAX  
3.6  
UNIT  
V
V
V
V
0.0  
0.0  
VIH  
Input Voltage  
2.1  
-0.2  
Vcc+0.3  
0.6  
V
-
IL  
OPERATING CHARACTERISTICS  
(Vcc = 2.7 to 3.6V,  
= 0V, Ta = -40°C to 85°C)  
VSS  
-55  
-70  
-100  
PARAMETER SYM.  
TEST CONDITIONS  
UNIT  
Min Max Min Max Min Max  
Input Leakage  
Vcc = Max,  
VIN = VSS to Vcc  
÷ ÷  
ILI  
-
1
-
1
-
1
uA  
Current  
CE  
OE  
= VIH  
= VIH or  
WE  
Output Leakage  
Current  
÷
÷
ILO  
-
1
-
1
-
1
uA  
or  
= VIL  
VIO = VSS to Vcc  
CE  
= VIL,  
WE  
OE  
= VIH ,  
Operating Power  
Supply Current  
=VIH,  
ICC  
-
-
3
-
-
3
-
-
3
mA  
IN = V or VIL,  
V
IH  
IOUT=0mA  
Cycle time=1us,  
100% duty, I =0mA,  
IO  
ICC1  
£
CE 0.2V,  
5
5
5
mA  
³
VIN VCC-0.2V  
Average Operating  
Current  
£
or VIN 0.2V  
Cycle time=min,  
100% duty, I =0mA,  
IO  
ICC2  
-
-
-
45  
0.3  
10  
-
-
-
40  
0.3  
10  
-
-
-
30  
0.3  
10  
mA  
mA  
uA  
CE  
= VIL,  
VIN = VIH or VIL  
V
UB V  
CE =  
LB =  
or  
Standby Power  
Supply Current  
(TTL Level)  
IH  
ISB  
=
IH  
VIH  
other input= VIL or  
CE ³ Vcc-0.2V or  
UB  
Standby Power  
Supply Current  
(CMOS Level)  
³
LB =  
Vcc-0.2V,  
ISB1  
£
VIN 0.2V or  
³
VIN Vcc-0.2V  
VOL  
VOH  
I
I
OL= 2.1mA  
-
0.4  
-
-
0.4  
-
-
0.4  
-
V
V
Output Low Voltage  
Output High Voltage  
OH = -1.0 mA  
2.2  
2.2  
2.2  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 4  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
CAPACITANCE  
(f = 1 MHz, Ta = 25°C,)  
PARAMETER  
Input Capacitance  
SYMBOL  
CONDITION  
MAX.  
UNIT  
pF  
CIN  
VIN  
= 0V  
8
CI/O  
VIN  
V
= OUT= 0V  
Input/ Output Capacitance  
10  
pF  
Note: This parameter is guaranteed by device characterization and is not production tested.  
AC TEST CONDITIONS  
PARAMETER  
CONDITIONS  
Input Pulse Levels  
0.6V to 2.1V  
3.0 ns  
Input Rise and Fall Times  
Input and Output Timing Reference Level  
1.4V  
C
C
L =30pF+1TTL Load(55ns/70ns)  
Output Load  
L =100pF+1TTL Load(Load for 100ns)  
AC TEST LOADS AND WAVEFORM  
TTL  
DQ  
RL  
CL  
30 pF  
50 ohm  
CL*  
Z0 = 50 ohm  
Vt =1.4V  
Fig.A * Including Scope and Jig Capacitance  
Fig.B Output Load Equivalent  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 5  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
AC CHARACTERISTICS(V =2.7 to 3.6V, V = 0V,Ta = -40°C to 85°C)  
cc  
SS  
(1) READ CYCLE  
-55  
-70  
-100  
PARAMETER  
SYM.  
UNIT  
Min  
55  
-
Max  
-
Min  
70  
-
Max  
-
Min  
Max  
-
tRC  
Read Cycle Time  
Address Access Time  
100  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
tACE  
tOE  
55  
55  
30  
-
70  
70  
35  
-
100  
100  
50  
-
Chip Enable Access Time  
-
-
-
Output Enable Access Time  
Output Hold from Address Change  
Chip Enable to Output in Low-Z  
Chip Disable to Output in High-Z  
Output Enable to Output in Low-Z  
Output Disable to Output in High-Z  
-
-
-
tOH  
tLZ  
10  
10  
-
10  
10  
-
10  
10  
-
-
-
-
tHZ  
20  
-
20  
55  
-
25  
-
25  
70  
-
30  
-
tOLZ  
tOHZ  
tBA  
tBLZ  
5
-
5
-
5
-
30  
100  
-
UB  
UB  
UB  
LB ,  
LB ,  
LB ,  
Access Time  
-
-
-
Enable to Output in Low-Z  
Disable to Output in High-Z  
10  
-
10  
-
10  
-
t
20  
25  
30  
BHZ  
(2)WRITE CYCLE  
-55  
-70  
-100  
PARAMETER  
SYM.  
UNIT  
Min  
55  
50  
50  
0
Max  
Min  
70  
60  
60  
0
Max  
Min  
100  
80  
80  
0
Max  
tWC  
tCW  
tAW  
tAS  
Write Cycle Time  
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Chip Enable to Write End  
Address Valid to Write End  
Address Setup Time  
-
-
-
-
-
-
-
-
-
tWP  
Write Pulse Width  
45  
0
50  
0
70  
0
tWR  
tDW  
tDH  
tWHZ  
tOW  
Write Recovery Time  
Data Valid to Write End  
Data Hold Time  
-
-
-
25  
0
-
-
30  
0
-
-
40  
0
-
-
Write Enable to Output in High-Z  
Output Active from Write End  
-
20  
-
-
25  
-
-
30  
-
5
5
5
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 6  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
TIMING WAVEFORMS  
READ CYCLE 1  
(Address Controlled, CE  
OE  
WE V  
UB  
, LB or/and = V )  
=
= V ,  
=
IL  
IH  
IL  
t
RC  
Ad dress  
t
AA  
t
OH  
D
OUT  
Previous Data Valid  
Data Valid  
V
WE =  
READ CYCLE 2 (  
)
IH  
tRC  
A d d r e s s  
tA A  
tOH  
tA CE  
C E  
tHZ  
tB A  
U B  
/
L B  
tB HZ  
tOE  
O E  
tOLZ  
tOHZ  
tB LZ  
tLZ  
D OUT  
High-Z  
DON'T CARE  
UNDEFINED  
(Chip Enable Controlled)  
Notes (READ CYCLE) :  
WE  
1.  
are high for read cycle.  
2. All read cycle timing is referenced from the last valid address to the first transition address.  
3. tHZand tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to  
VOH or VOL levels.  
4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device  
and from device to device interconnection.  
±
5. Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not  
100% tested.  
CE  
6. Device is continuously selected with  
=V .  
IL  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 7  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
WE  
WRITE CYCLE 1 (  
Controlled)  
t
WC  
Add r ess  
t
t
AW  
WR  
t
CW  
CE  
U B  
/
LB  
t
t
WP  
AS  
W E  
t
WHZ  
t
OW  
D
O U T  
High-Z  
t
t
DH  
DW  
D
I N  
High-Z  
CE  
WRITE CYCLE 2 (  
Controlled)  
t
WC  
A d d r e s s  
t
t
WR  
AW  
t
CW  
C E  
t
AS  
U B  
/
L B  
t
WP  
W E  
D
Hig h - Z  
Hig h - Z  
O U T  
t
t
DH  
DW  
D
I N  
H ig h -Z  
DO N'T CARE  
UNDEFINE D  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 8  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
UB  
WRITE CYCLE 3 (  
, LB Controlled)  
t
WC  
A d d r e s s  
t
t
AW  
WR  
t
CW  
U B  
/ L B  
t
AS  
C E  
t
WP  
W E  
D
Hig h - Z  
Hig h - Z  
O U T  
t
t
DW  
DH  
D
Hig h - Z  
I N  
DO N'T CARE  
UNDEFINE D  
NOTES ( WRITE CYCLE ) :  
1. A write occurs during the overlap of a low  
CE  
WE  
. A write begins at the lateat transition  
, a low  
CE  
WE  
CE  
going  
among  
goes low,  
going low. A write end at the earliest transition among  
WE  
WP  
high,  
going high. t is measured from the beginning of write to the end of write.  
CW  
t
CE  
going low to the end of write.  
2.  
is measured from the later of  
AS  
3. t is measured from the address valid to the beginning of write.  
WR  
4. t is measured from the end of write to the address change.  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 9  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
DATA RETENTION CHARACTERISTICS  
PARAMETER  
SYM.  
TEST  
MIN.  
MAX.  
UNIT  
CONDITION  
CE  
VCC -0.2V  
VCC for Data Retention  
VDR  
ICCDR  
tCDR  
tR  
³
1.5  
-
-
10  
-
V
uA  
ns  
³
VIN Vcc -0.2V or  
VIN 0.2V  
Data Retention Current  
£
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
RC  
t
-
ns  
DATA RETENTION WAVEFORM  
(Ta = -40 C to 85 C)  
°
°
D ata R etenti on M ode  
V cc _ty p  
V c c_ty p  
t
V
> 1.5V  
V c c  
C E  
D R  
t
C D R  
R
C E >V c c- 0.2V  
V
V
IH  
IH  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 10  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
PACKAGE DIMENSIONS  
44-LEAD TSOP-II  
D
44  
23  
E2  
E E1  
L1  
b1  
22  
INDEX MARK  
Mirror finish  
c
e
b
A
£c  
A3  
A2 A1  
SEATING PLANE  
c1  
L
Dimension in mm  
Dimension in inch  
Symbol  
Min  
Nom  
-
-
1.00  
0.25  
0.35(typ)  
0. 15  
0.805  
0.10  
Max  
1.20  
0.1  
1.05  
-
Min  
Nom  
-
Max  
0.047  
A
A1  
A2  
A3  
b
b1  
c
c1  
D
-
-
0.05  
0.95  
-
-
0.10  
-
-
0.002  
-
0.004  
0.037  
0.039  
0.010  
0.014(typ)  
0.006  
0.032  
0.004  
0.725  
0.031(typ)  
0.463  
0.400  
0.458  
0.020  
0.032(typ)  
-
0.041  
-
-
-
-
-
0.25  
-
-
0.004  
0.010  
-
-
-
-
18.31  
18.41  
0.80(typ)  
11.76  
10.16  
10.76  
0.5  
18.51  
0.721  
0.729  
e
E
-
-
-
0.455  
0.394  
-
0.016  
-
-
0.471  
0.405  
-
0.024  
-
11.56  
10.03  
11.96  
10.29  
E1  
E2  
L
L1  
q
-
0.4  
-
-
0.6  
-
0.8(typ)  
-
0
8
0
8
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 11  
Publication Date: SEP. 2000  
Revision:0.B  
TE  
tm
CH  
Preliminary T15V4M16A  
Units : millimeters  
PACKAGE DIMENSIONS  
48-pin CSP (8 row x 6 column)  
48 BALL FINE PITCH BGA (0.75mm ball pitch)  
Bottom View  
Top V iew  
A1 INDEX MARK  
B
0. 50  
B 1  
#A1  
B /2  
A
Y
E 2  
D
0.30  
E
E1  
Symbol  
A
min  
typ  
0.75  
6.00  
3.75  
8.00  
5.25  
0.30  
1.10  
0.95  
0.25  
-
max  
-
-
5.95  
6.05  
-
Notes :  
B
1. Bump counts : 48 (8 row x 6column)  
2. Bump pitch : (x,y)=(0.75 x 0.75) typ.  
3. All tolerance are ±0.050 unless otherwise specified.  
4. ‘Y’ is coplanarity : 0.08(max)  
5. Units : mm  
-
B1  
C
7.95  
8.05  
-
-
C1  
D
0.25  
0.35  
1.20  
-
-
E
-
0.20  
-
E1  
E2  
Y
0.30  
0.08  
Taiwan Memory Technology, Inc. reserves the right  
to change products or specifications without notice.  
P. 12  
Publication Date: SEP. 2000  
Revision:0.B  

相关型号:

T15V4M16A-100C

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