T15V4M08A [TMT]
512K X 8 LOW POWER CMOS STATIC RAM; 512K ×8低功耗CMOS静态RAM![T15V4M08A](http://pdffile.icpdf.com/pdf1/p00064/img/icpdf/T15V4M08A_337888_icpdf.jpg)
型号: | T15V4M08A |
厂家: | ![]() |
描述: | 512K X 8 LOW POWER CMOS STATIC RAM |
文件: | 总11页 (文件大小:76K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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TE
CH
Preliminary T15V4M08A
512K X 8 LOW POWER
CMOS STATIC RAM
SRAM
FEATURES
Low-power consumption
GENERAL DESCRIPTION
·
The T15V4M08A is a very Low Power
CMOS Static RAMorganizedas 524,288 words by
8 bits . This device is fabricated by high
performance CMOS technology. It can be
operated under wide power supply voltage range
from +2.7V to +3.6V.
- Active: 40mA at 55ns
- Stand-by: 10uA (CMOS input/output)
55/70/100 ns access time
·
·
·
·
·
·
·
Equal access and cycle time
Single +2.7V to 3.6V Power Supply
TTL compatible , Tri-state output
Common I/O capability
The T15V4M08A inputs and three-state
outputs are TTL compatible and allow for direct
interfacing with common system bus structures.
Data retention is guaranteed at a power supply
voltage as low as 1.5V.
Automatic power-down when deselected
Available in 32-pin TSOP-I(8x13.4mm) and
48-pin CSP packages
PART NUMBER EXAMPLES
Vcc
Vss
PART NO.
PACKAGE CODE
P= TSOP-I(8x13.4)
C = CSP
T15V4M08A-55C
T15V4M08A-70P
CORE
A0
DECODER
.
.
.
ARRAY
A18
WE
OE
CE
I/O1
.
.
.
CONTROL
CIRCUIT
DATA I/O
I/O8
BLOCK DIAGRAM
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 1
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
PIN CONFIGURATIONS
A 1 1
A9
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A 1 0
C E
A8
3
A 1 3
W E
A 1 8
A 1 5
V C C
A 1 7
A 1 6
A 1 4
A 1 2
A7
4
I / O 8
I / O 7
I / O 6
I / O 5
I / O 4
V S S
I / O 3
I / O 2
I / O 1
A0
5
6
7
TSOP-I
8
9
(8x13.4mm)
10
11
12
13
14
15
16
A6
A1
A5
A2
A4
A3
1
2
3
4
5
6
A 0
A 1
N C
A 3
A 6
A 8
A
B
C
D
E
I / O 5
I / O 6
V S S
V C C
I / O 7
I / O 8
A 9
A 2
W
E
A 4
A 5
A 7
I / O 1
I / O 2
V C C
V S S
N C
4 8 - C S P
T O P V I E W
A 1 8
C E
A 1 7
I / O 3
I / O 4
A 1 4
F
O E
A 1 6
A 1 2
A 1 5
A 1 3
G
H
A 1 0
A 1 1
PIN DESCRIPTIONS
SYMBOL DESCRIPTIONS
A0 ~ A18 Address inputs
I/O1~I/O8 Data inputs/outputs
SYMBOL DESCRIPTIONS
Output enable input
Power supply
Ground
OE
VCC
Chip enable
V
SS
CE
Write enable input
NC
No connection
WE
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 2
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
Voltage on Any Pin Relative to V
Power Dissipation
SYM
MIN.
-0.2
-
MAX.
+3.6 V
0.7
UNIT
V
SS
R
V
PD
W
TSTG
IBIAS
Storage Temperature
-55
-40
+150
+85
°C
°
C
Temperature Under Bias
*Note: Stresses greater than those listed above Absolute Maximum Ratings may cause permanent damage to
the device. This is a stress rating only and function operation of the device at these or any other
conditions outside those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
TRUTH TABLE
WE
OE
DATA
MODE
Standby
CE
H
L
X
H
H
L
X
L
High-Z
Data Out
High-Z
Active, Read
L
H
X
Active, Output Disable
Acitve, Write
L
Data In
*Note: X = Don’t Care (Must be low or high state), L = Low, H = High
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 3
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
OPERATING CHARACTERISTICS
(Vcc = 2.7 to 3.6V, Vss = 0V, Ta = -40 C to 85 C)
°
°
-55
-70
-100
PARAMETER SYM.
TEST CONDITIONS
UNIT
Min Max Min Max Min Max
Input Leakage
Vcc = Max,
VIN = Vss to Vcc
½ILI½
-
1
-
1
-
1
uA
Current
CE = VIH
OE
WE
or
or
= VIH
Output Leakage
½ILO½
-
1
-
1
-
1
uA
Current
= VIL
VOUT = Vss to Vcc
CE
= VIL,
=VIH,
WE
OE
= VIH ,
Operating Power
Supply Current
ICC
ICC1
ICC2
-
-
-
2
-
-
-
2
-
-
-
2
mA
mA
mA
= VIH or VIL,
IN
V
IOUT=0mA
Cycle time=1us,
100% duty, IOUT =0mA,
3
3
3
CE £
£
0.2V,VIN 0.2V
³
or VIN Vcc-0.2V
Average Operating
Current
Cycle time=min,
100% duty, IOUT =0mA,
40
35
25
CE
= VIL,
VIN = VIH or VIL
CE V
Standby Power
Supply Current
(TTL Level)
=
IH
ISB
VIN = VIH or VIL
-
-
0.3
10
-
-
0.3
10
-
-
0.3
10
mA
uA
CE ³
Vcc-0.2V,
VIN 0.2V or
Standby Power
Supply Current
(CMOS Level)
£
ISB1
³
VIN Vcc-0.2V
VOL
VOH
I
I
OL= 2.1mA
-
2.2
0.4
-
-
2.2
0.4
-
-
2.2
0.4
-
V
V
Output Low Voltage
Output High Voltage
OH = -1.0 mA
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 4
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
RECOMMENDED OPERATING CONDITIONS
(Ta = -40 C to 85 C)
°
°
PARAMETER
Supply Voltage
SYM
Vcc
Vss
VIH
MIN
2.7
TYP
3.0
0.0
-
MAX
3.6
UNIT
V
V
V
V
0.0
0.0
0.7Vcc
-0.2
Vcc+0.3
0.6
Input Voltage
V
-
IL
CAPACITANCE
(f = 1 MHz, Ta = 25 C,)
°
PARAMETER
Input Capacitance
SYMBOL
CONDITION
MAX.
UNIT
pF
CIN
VIN
= 0V
8
CI/O
VIN
V
= OUT= 0V
Input/ Output Capacitance
10
pF
Note: This parameter is guaranteed by device characterization and is not production tested.
AC TEST CONDITIONS
PARAMETER
CONDITIONS
Input Pulse Levels
0.6V to 0.7Vcc
3.0 ns
Input Rise and Fall Times
Input and Output Timing Reference Level
1.4V
C
C
L =30pF+1TTL Load(55ns/70ns)
Output Load
L =100pF+1TTL Load(Load for 100ns)
AC TEST LOADS AND WAVEFORM
T T L
D Q
R L
C L
5 0 o h m
3 0 p F
C L
*
Z 0 = 5 0 o h m
V t = 1 . 4 V
F i g . A * I n c l u d i n g S c o p e a n d J i g C a p a c i t a n c e
F i g . B O u t p u t L o a d E q u i v a l e n t
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 5
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
(
=2.7 to 3.6V, Vss = 0V, Ta = -40 C to 85 C)
° °
AC CHARACTERISTICS V
cc
(1) READ CYCLE
-55
-70
-100
PARAMETER
SYM.
UNIT
Min
55
-
Max
-
Min
70
-
Max
-
Min
Max
-
tRC
Read Cycle Time
100
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACE
tOE
Address Access Time
Chip Enable Access Time
55
55
30
-
70
70
35
-
100
100
50
-
-
-
-
Output Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
-
-
-
tOH
tLZ
tHZ
10
10
-
10
10
-
10
10
-
-
-
-
20
-
20
25
-
25
30
-
30
tOLZ
tOHZ
5
-
5
-
5
-
(2)WRITE CYCLE
-55
-70
-100
PARAMETER
SYM.
UNIT
Min
55
50
50
0
Max
Min
70
60
60
0
Max
Min
Max
tWC
tCW
tAW
tAS
Write Cycle Time
-
-
-
-
100
80
80
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to Write End
Address Valid to Write End
Address Setup Time
-
-
-
-
-
-
-
-
-
tWP
tWR
tDW
tDH
tWHZ
tOW
Write Pulse Width
45
0
50
0
70
0
Write Recovery Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
-
-
-
25
0
-
-
30
0
-
-
40
0
-
-
-
20
-
-
25
-
-
30
-
5
5
5
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 6
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
TIMING WAVEFORMS
READ CYCLE 1
(Address Controlled,
)
CE
OE
WE V
= V , =
IH
=
IL
t
RC
A d d r e s s
t
AA
t
OH
D
O UT
Previous DataValid
DataValid
V
WE =
READ CYCLE 2 (
)
IH
t R C
A d d r e s s
t O H
t A A
t
A C E
C E
t H Z
t O E
O E
t O L Z
t L Z
t O H Z
D
O U T
H i g h - Z
D O N ' T C A R E
U N D E F I N E D
Notes : (READ CYCLE) :
WE
1.
are high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition referenced to
VOH or VOL levels.
4. At any given temperature and voltage condition. tHZ (max.) is less than tLZ (min.) both for a given device
and from device to device interconnection.
±
5. Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not
100% tested.
CE
6. Device is continuously selected with
=V .
IL
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 7
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
WE
WRITE CYCLE 1 (
Controlled)
t
W C
A
d
d
r
e
s s
t
t
A W
WR
t
C W
C
E
t
t
A S
W P
W
E
t
WHZ
t
OW
D
O
U
T
H igh-Z
t
t
DW
DH
D
I N
H i g h - Z
CE
WRITE CYCLE 2 (
Controlled)
t
W
C
A
d
d
r
e
s
s
t
t
A W
W
R
t
C W
C
E
t
A
S
t
W
P
W
E
D
H
H
i
i
g h - Z
O
U T
t
t
D H
D W
D
g h - Z
H i g h - Z
I N
D
U
O
N ' T C A R E
N D F I N
E
E D
NOTES ( WRITE CYCLE ) :
1. A write occurs during the overlap of a low
CE WE
CE
WE
. A write begins at the lateat transition
, a low
going low. A write end at the earliest transition among
going high. tWP is measured from the beginning of write to the end of write.
CE
CE
among
WE
goes low,
going
high,
2. tCW is measured from the later of
going low to the end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change.
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 8
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
DATA RETENTION CHARACTERISTICS
PARAMETER
SYM.
TEST
MIN.
MAX.
UNIT
CONDITION
CE
VCC for Data Retention
VDR
ICCDR
tCDR
tR
³
1.5
-
-
10
-
V
uA
ns
Vcc -0.2V
Data Retention Current
³
Chip Deselect to Data Retention Time
Operation Recovery Time
VIN Vcc -0.2V or
0
£
RC
VIN 0.2V
t
-
ns
DATA RETENTION WAVEFORM
(Ta = -40 C to 85 C)
°
°
Data Retention Mode
V D R > 1.5V
V cc_typ
t
V c c _ T Y P
V C C
t
R
C D R
CE>VCC-0. 2V
C E
V IH
V IH
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 9
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
PACKAGE DIMENSIONS
32-LEAD TSOP-I (8x13.4mm)
SYMBOL
Dimension in inches
0.044(MAX)
0.004±0.002
0.041(MAX)
0.008±0.004
0.006±0.001
0.465±0.008
0.315±0.004
0.528±0.008
0.020(TYP.)
Dimension in mm
1.10(MAX)
0.05±0.05
1.02(MAX)
0.20±0.10
0.15±0.02
11.8±0.2
A
A1
A2
b
C
D
E
HD
e
L
L1
y
8.0±0.1
13.4±0.2
0.5(TYP.)
0.5±0.1
0.8±0.2
0.020±0.004
0.031±0.008
0.002(MAX)
0.05(MAX)
°
°
° °
0 ~5
è
0 ~5
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 10
Publication Date: MAR. 2001
Revision:0.A
TE
CH
Preliminary T15V4M08A
Units : millimeters
PACKAGE DIMENSIONS
48-pin CSP (8 row x 6 column)
48 BALL FINE PITCH BGA (0.75mm ball pitch)
Bottom View
Top V iew
A1 INDEX MARK
B
0. 50
B 1
#A1
B /2
A
Y
E 2
D
0.30
E
E1
Symbol
A
min
typ
0.75
6.00
3.75
8.00
5.25
0.30
1.10
0.95
0.25
-
max
-
-
5.95
6.05
-
Notes :
B
1. Bump counts : 48 (8 row x 6column)
2. Bump pitch : (x,y)=(0.75 x 0.75) typ.
3. All tolerance are ±0.050 unless otherwise specified.
4. ‘Y’ is coplanarity : 0.08(max)
5. Units : mm
-
B1
C
7.95
8.05
-
-
C1
D
0.25
0.35
1.20
-
-
E
-
0.20
-
E1
E2
Y
0.30
0.08
Taiwan Memory Technology, Inc. reserves the right
to change products or specifications without notice.
P. 11
Publication Date: MAR. 2001
Revision:0.A
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