VSP1221PFB [TI]
适用于 CCD 传感器的 12 位 21MSPS 单通道 AFE | PFB | 48 | 0 to 70;
| 型号： | VSP1221PFB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 CCD 传感器的 12 位 21MSPS 单通道 AFE | PFB | 48 | 0 to 70 CD 商用集成电路 传感器 转换器 |
| 文件： | 总26页 (文件大小：310K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
12-BIT, 21-MSPS, ULTRALOW-POWER
CCD SIGNAL PROCESSOR
FEATURES
PIN ASSIGNMENTS
•
•
•
12-Bit, 21-MSPS, Analog-to-Digital
Converter
PACKAGE
(TOP VIEW)
Low Power: 70 mW Minimum
Power-Down Mode: 4 mW
Low Input-Referred Noise: 75-dB
SNR Typical at 0-dB Gain
48 47 46 45 44 43 42 41 40 39 38 37
•
•
•
•
Novel Optical-Black (OB) Calibration
Low-Aperture Delay
36
35
34
33
32
31
30
29
28
27
26
25
DACO2
AVSS
DACO1
AVDD
TP2
D0/SDO
D1
1
2
3
4
5
6
7
8
9
Single 3-V Supply Operation
D2
D3
D4
D5
DNL: <±0.5 LSB and
INL: <±1.5 LSB Typical at 0-dB Gain
PIN
DIN
•
•
Programmable-Gain Range: 0 dB to 36 dB,
Gain Resolution of 0.05 dB/Step
D6
TP1
D7
D8
48-Pin TQFP Package
CLREF
AVDD
AVSS
VSS
D9 10
APPLICATIONS
D10
D11
11
12
•
Digital Still Camera
•
Digital Video Camera
13 14 15 16 17 18 19 20 21 22 23 24
DESCRIPTION
The VSP1221 is a highly-integrated mixed-signal IC
used for signal conditioning and analog-to-digital
conversion at the output of a CCD array. The IC has
a correlated double sampler (CDS) and an analog
programmable-gain amplifier (PGA) stage followed by
an analog-to-digital converter (ADC) and a digital
PGA stage. The CDS is used to sample the CCD
signal and is followed by the analog PGA stage. The
ADC is a12-bit, 21-MSPS pipelined ADC. The digital
PGA provides further amplification.
Additionally, there is an offset calibration loop for
optical-black correction. The optical-black reference
level is user-programmable. The chip also has two
8-bit digital-to-analog converters (DAC) for external
analog settings.
The chip has a serial port for configuring internal
control registers.
The VSP1221 is available in a 48-pin TQFP package
and operates from a single 3-V power supply.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
Terminal Functions
TERMINAL
TYPE(1)
DESCRIPTION
NAME
PIN
D0
/SDO
D1
D0 = Bit 0 ADC output, least-significant bit (LSB)
SDO = Serial data output (used for register read back)
1
DO
2
3
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
DO
P
Bit 1 ADC output
D2
Bit 2 ADC output
D3
4
Bit 3 ADC output
D4
5
Bit 4 ADC output
D5
6
Bit 5 ADC output
D6
7
Bit 6 ADC output
D7
8
Bit 7 ADC output
D8
9
Bit 8 ADC output
D9
10
11
12
13
14
15
16
Bit 9 ADC output
D10
D11
DIVDD
DIVSS
DVSS
Bit 10 ADC output
Bit 11 ADC output, most-significant bit (MSB)
Power supply for digital I/O
Digital ground for digital I/O
Digital ground
P
P
ADCCL
K
DI
ADC clock
DVDD
CFG1
BLKG
17
18
19
P
Digital power supply
DI
DI
Configuration pin 1. Must be connected to GND
Blanking pulse:
High = Normal operation
Low = Digital output as programmed in the blanking register (see the blanking register section)
Optical-black clamping pulse (default = active low)
CDS reference sampling pulse (default = active low)
CDS data sampling pulse (default = active low)
Dummy clamping pulse (default = active low)
Configuration pin 2. Must be connected to GND
Substrate ground
CLPOB
SHP
20
DI
DI
21
SHD
22
DI
CLPDM
CFG2
VSS
23
DI
24
DI
25
P
AVSS
AVDD
CLREF
TP1
26, 35, 41
P
Analog ground
27, 33, 40
P
Analog power supply
28
29
30
31
32
34
36
37
38
39
42
AO
AIO
AI
External decoupling for clamp voltage
Test point. Do not connect
DIN
CCD signal input
PIN
AI
Input ground
TP2
AIO
AO
A0
AO
AO
AO
DI
Test point. Do not connect
DAC01
DAC02
ISET
General-purpose 8-bit DAC output voltage
General-purpose 8-bit DAC output voltage
Internal bias-current setting
REFP
REFM
OE
External decoupling for internal positive reference
External decoupling for internal negative reference
Output data enable:
Low = Normal operation
High = Digital output high impedance state
RESET
STBY
43
44
DI
DI
Hardware reset (active low)
Hardware power down (active low)
(1) P: Power Supply, AI: Analog input, AO: Analog output, AIO: Analog input/output, DI: Digital input, DO: Digital output
2
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
Terminal Functions (continued)
TERMINAL
TYPE(1)
DESCRIPTION
NAME
PIN
SCKP
45
DI
SCKP - Serial clock polarity:
High = Sample serial data on rising edge of serial clock (pin 48)
Low = Sample serial data on falling edge of serial clock (pin 48)
SLOAD
SDIN
46
47
48
DI
DI
DI
Serial data latch
Serial data input
Serial clock input
SCLK
FUNCTIONAL BLOCK DIAGRAM
CLPDM CLREF TP1
TP2
AVDD
REFP ISET REFM
DVDD
DIVDD
OE
INT. REF.
CLAMP
D0/SDO
12
DIN
PIN
12-Bit
ADC
3-State
Latch
Analog
PGA
Digital
PGA
CDS
D11
RESET
ADCCLK
SHD
+
−
Vb
Register
Offset
Correction
Logic
Control
SHP
8-Bit
DAC
DAC
Register
DACO1
DACO2
BLKG
CLPOB
STBY
PGA
Register
8
8-Bit
DAC
DAC
Register
10
OB
SCKP
OB DAC
Calibration
Circuit
CFG1
CFG2
2x8
SLOAD
SCLK
SDIN
Serial
Port
VSS
AVSS
DVSS
DIVSS
Figure 1. Internal Block Diagram fo the VSP1221
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
Supply voltage, AVDD, DVDD, DIVDD
Analog input voltage
-0.3 V to 6.5 V
-0.3 V to AVDD + 0.3 V
-0.3 V to DVDD + 0.3 V
0°C to 150°C
Digital input voltage
Junction temperature, TJ
Storage temperature, Tstg
Lead temperature, (10 sec)
-65°C to 150°C
260°C
(1) Stresses beyond those listed under,, absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under ,,recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
ELECTRICAL CHARACTERISTICS
GENERAL SPECIFICATIONS
All typical specifications are at TA = 25°C, all power supply voltages = 3 V, and conversion rate = 21 MHz, unless otherwise
stated. All maximum specifications are assured across operating temperature and voltage ranges.
PARAMETERS
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
AVDD
DVDD
DIVDD
AVDD
DVDD
DIVDD
Analog supply voltage
Digital supply voltage
Digital I/O supply voltage
2.7
2.7
1.8
20
2
3
3
3.3
3.3
3.3
29
6
V
24
4
Operating current
mA
0.5
80
1
1
4
Normal mode
90
2
100
4
Power dissipation
mW
Power-down mode
REFERENCE
Positive reference voltage
1 µF to ground (pin 38)
1 µF to ground (pin 39)
100 kΩ to ground (pin 37)
1.95
0.7
2.05
0.75
1
2.2
0.9
V
Negative reference voltage
V
V
External bandgap voltage reference
Bandgap temperature coefficient
100
PPM/°C
TEMPERATURE RANGE
TA Operating temperature
DIGITAL INPUT
-20
75
°C
VIH
VIL
IIH
IIL
Logic-high input voltage
0.8DIVDD
V
Logic-low input voltage
Logic-high input current
Logic-low input current
Input capacitance
0.2DIVDD
DIVDD = 3 V
DIVDD = 3 V
-10
-10
10
10
µA
pF
CI
5
5
DIGITAL OUTPUT
VOH
VOL
IOZ
Logic-high output voltage
IOH = 50 µA, DIVDD = 3 V
IOL = 50 µA, DIVDD = 3 V
0.8DIVDD
-10
V
Logic-low output voltage
0.2DIVDD
High-impedance-state output current
Output capacitance
10
15
µA
pF
CO
CO
4
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
ELECTRICAL CHARACTERISTICS (CONTINUED)
DEVICE SPECIFICATIONS
All typical specifications are at TA = 25°C, all power supply voltages = 3 V, and conversion rate = 21 MHz, unless otherwise
stated. All maximum specifications are assured across operating temperature and voltage ranges.
PARAMETERS
FULL CHANNEL
TEST CONDITIONS
MIN
TYP
MAX UNIT
Input signal level for full-scale output
Input capacitance
Input referred noise
Integral nonlinearity
Differential nonlinearity
Data latency
Single ended, gain = 0 dB
1000
8
mV
pF
Gain = 0 dB
Gain = 0 dB
Gain = 0 dB
130
±2
360
µV
LSB
±1.5
±5
±0.5 ±0.75 +1.5/-1
LSB
10
Clocks
MHz
Conversion rate
21
PGA
Gain control code
Maximum gain
10
36
Bits
dB
dB
dB
dB
dB
Gain code = 1011010000 (720 Decimal)
Gain code = 0000000000
Minimum gain
0
Gain resolution
0.05
Integral nonlinearity
Differential nonlinearity
±0.02 ±0.05
±0.02 ±0.05
±0.4
±0.3
ANALOG-TO-DIGITAL CONVERTER (ADC)
Resolution
12
Bits
Conversion rate
21
MHz
No missing codes
Integral nonlinearity
±1
LSB
LSB
Differential nonlinearity
±0.5
3.5
(fixed)
Data latency
Clocks
GENERAL-PURPOSE DIGITAL-TO-ANALOG CONVERTER (DAC)
Resolution
8
Bits
LSB
LSB
V
Integral nonlinearity
Differential nonlinearity
Output voltage range
±0.1
±1
±1
±0.1
0
AVDD
Output settling time
10-pF external load. Settle to 1 mV
4
µs
SERIAL INTERFACE
Clock frequency (SCLK)
OPTICAL-BLACK CALIBRATION
Maximum correctable CCD black level
Convergence time
DIVDD = 3 V
40
MHz
100
mV
Black level = 100 mV, gain = 12 dB, OB reference level = 0
440
±1
550 Clocks
Gain = 0-20dB
Gain = 20-26 dB
Gain = 26-32 dB
Gain = 32-36 dB
±2
±1
±4
Calibration error
LSB
±4
±2
±4
±8
5
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
TIMING REQUIREMENTS
SAMPLE AND CONVERSION TIMING
N
N+1
DIN
(CCD IN)
t
t
CCD_SHP
WSHP
SHP
SHD
t
t
t
CCD_SHD
WSHD
DSHP
t
DSHD
t
t
ADC_SHD
WADC
t
t
ADCCLK
WADC
ADCCLK
D0–D11
t
t
OD
HOLD
N−10
N−9
N−8
N−7
Figure 2. Sample and Conversion Timing
SAMPLE AND CONVERSION TIMING
PARAMETERS
MIN
TYP
MAX UNIT
tADCCLK
tWADC
tWSHP
tWSHD
ADC clock period
ADC high or low width
SHP pulse width
46
23
5
ns
ns
ns
ns
SHD pulse width
5
tCCD_SHP CCD reset start to SHP rising edge
tCCD_SHD CCD data start to SHD rising edge
tADC_SHD ADC falling edge to SHD rising edge
See Note(1) See Note(1)
See Note(2) See Note(2)
15
See Note(1)
See Note(2)
35
3
ns
ns
ns
ns
ns
tDSHP
tDSHD
tHOLD
tOD
Sampling delay, reset
Sampling delay, data
Output hold time
Output delay
1
4
4
4
1.75
5
7
15
(1) Best performance if tCCD_SHP > 15 ns
Good performance if 10 ns < tCCD_SHP < 15 ns
Poor performance if tCCD_SHP < 10 ns
(2) Best performance if tCCD_SHD > 19 ns
Good performance if 10 ns < tCCD_SHD < 19 ns
Poor performance if tCCD_SHD < 15 ns
6
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
SERIAL INTERFACE TIMING
Standard Functionality, SCKP (Pin 45) = High (Sample Data on Rising Edge of SCLK),
Operation = Write
t
t
SLOADH
SLOADS
SLOAD
t
WSCLK
t
t
SCLK
WSCLK
SCLK
SDIN
t
DH
t
DS
MSB
LSB
16 Bits
Figure 3. Serial Interface Timing for Write, SCKP = High
Standard Functionality, SCKP (Pin 45) = Low (Sample Data on Falling Edge of SCLK),
Operation = Write
t
t
SLOADH
SLOADS
SLOAD
t
WSCLK
t
t
SCLK
WSCLK
SCLK
SDIN
t
DH
t
DS
MSB
LSB
16 Bits
Figure 4. Serial Interface Timing for Write, SCKP = Low
SERIAL INTERFACE TIMING FOR WRITE, SCKP = LOW
PARAMETERS
MIN
25
12.5
5
TYP
MAX UNIT
tSCLK
tWSCLK
tSLOADS
tSLOADH
tDS
SCLK period
ns
ns
ns
ns
ns
ns
SCLK high or low width
SLOAD to SCLK setup time
SCLK to SLOAD hold time
Data setup time
2
5
tDH
Data hold time
2
7
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
Standard Functionality, SCKP (Pin 45) = High, Operation = Read
t
t
SLOADS
SLOADH
SLOAD
SCLK
CLK CLK
CLK CLK
CLK CLK CLK CLK
16 17 18 19
CLK CLK
23 24
CLK
32
1
2
6
7
A4 A3 A2 A1 A0
(Address)
MSB
MSB
SDIN
SDO
D9–D0 LSB
DATA_REQUEST
(16 Bits)
D9–D0
(Data)
D15–D10
LSB
DATA_SEND
(16 Bits)
Figure 5. Serial Interface Timing for Read, SCKP = High
Device register values can be read back serially from the SDO pin (pin 1). For serial data read, user first sends a
16 bit DATA_REQUEST on the SDIN pin (pin 47). The format is as follows:
DATA_REQUEST on SDIN
SD15
SD14-SD10
SD9-SD0
1
Required register address
Don't Care
Although the length of DATA_REQUEST is 16 bits, the ten LSBs are don't cares. Also, note that SD15 (RD/WR)
should be 1 for register read (see the serial data format section). The register address portion of
DATA_REQUEST is decoded and the register data value (DATA_SEND) is available on the SDO pin at the rising
edge of CLK18 (see Figure 5) if SLOAD is low at that time. If SLOAD is high at that time, then DATA_SEND is
available when SLOAD goes low again. The format of DATA_SEND is as follows:
DATA_SEND on SDO
SD15-SD10
SD9-SD0
Don't Care
Required register data
Although the length of DATA_SEND is 16 bits, the six MSBs are don't cares.
8
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
SDO Timing
SCLK
t
SHOLD
t
SOD
MSB
LSB
SDO
16 Bits
Figure 6. Serial Interface Timing Between SCLK and SDO
SERIAL INTERFACE TIMING BETWEEN SCLK AND SDO(1)
PARAMETERS
MIN TYP
MAX UNIT
tSHOLD
tSOD
Data output hold time
Data output delay
5
ns
13
ns
(1) Data output transition occurs at the falling edge of SCLK; so data should be sampled at the rising edge of SCLK. Since the SDO pin is
multiplexed with the D0 pin, OE (pin 42) should be low.
Standard Functionality, SCKP (Pin 45) = Low, Operation = Read
t
t
SLOADS
SLOADH
SLOAD
SCLK
CLK CLK
CLK CLK
CLK CLK CLK CLK
16 17 18 19
CLK CLK
23 24
CLK
32
1
2
6
7
A4 A3 A2 A1 A0
(Address)
MSB
MSB
SDIN
SDO
D9–D0 LSB
DATA_REQUEST
(16 Bits)
D9–D0
(Data)
D15–D10
LSB
DATA_SEND
(16 Bits)
Figure 7. Serial Interface Timing for Read, SCKP = Low
The SDO timing is the same as before, except that data should be sampled at the falling edge of SCLK.
9
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
SERIAL DATA FORMAT
Standard Functionality
The serial data is always grouped in 16-bit blocks with the following format. Multiple 16-bit blocks can be send
through the SDIN pin (pin 47) keeping SLOAD (pin 46) low.
SD15
MSB
SD14
SD13
SD12
SD11
SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
LSB
RD/WR(1)
A4
A3
A2
A1
A0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Register Address
Register Data
(1) RD/WR = 0, Write into registers, RD/WR = 1, Read from registers
(2)
REGISTER DESCRIPTION
REGISTER ADDRESS
REGISTER NAME
REGISTER FUNCTION
A4
0
A3
0
A2
0
A1
0
A0
0
Control register
PGA register
Mode control
Gain control
0
0
0
0
1
0
0
0
1
0
User DAC1 register
User DAC2 register
Reserved
User DAC1 control
User DAC2 control
Reserved
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
Reserved
Reserved
0
0
1
1
0
OB register
OB level control
Blanking output control
Clock signal polarity control
ADCCLK
0
0
1
1
1
Blanking register
Signal polarity register
Timing register 1
Timing register 2
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
SHP
(2) The register values are updated as soon as the register is written. It may take 0 to 9 ADCCLK cycles for it to have effect on the device.
10
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
Control Register
SD15
MSB
SD1
3
SD1
1
SD0
LSB
SD14
SD12
SD10
SD9
SD8
SD7
SD6
SD5 SD4 SD3
SD2
SD1
RD/W
R
Re-
served
Re-
served
0
0
0
0
0
STBYZ CLAMPPIN OB
Reserved
Data
Reserved
RTSY
Address
BIT
NAME
DEFAULT VALUE
DESCRIPTION
SD0
RTSY
0
RTSY = 0, no change
RTSY = 1, reset all register bits to their default settings
SD1
RESERVED
RESERVED
RESERVED
RESERVED
OB
0
0
Reserved
Reserved
Reserved
Reserved
SD2
SD3-SD5
SD6
All 0
X
SD7
1
OB = 0, optical-black calibration disable(1)
OB = 1, optical-black calibration enable
SD8
SD9
CLAMPPIN(2)
STBYZ
1
1
CLAMPPIN = 1, disable clamping on PIN (pin 31), connect PIN directly to ground.
CLAMPPIN = 0, enable clamping on PIN (pin 31), connect PIN to ground via capacitor.
STBYZ = 0, device in power-down mode (software power down) STBYZ = 1, no change
(1) Under this condition, the previous value of black level remains unchanged.
(2) See the CCD input section.
Programmable-Gain Amplifier (PGA) Register
SD15
MSB
SD0
LSB
SD14
SD13
SD12
SD11 SD10 SD9 SD8 SD7 SD6
MSB
SD5 SD4 SD3 SD2 SD1
RD/WR
0
0
0
0
1
GAIN
Data
LSB
Address
BIT
NAME
DEFAULT VALUE
DESCRIPTION
SD0-DS9 GAIN
All 0
Programmable-gain control
Gain step = 0.05 dB
Minimum gain = 0 dB
Maximum gain = 36 dB
Code
Gain
0000000000
0 dB
0000000001
0.05 dB
.
.
.
1011001111
1011010000
Higher codes
35.95 dB
36 dB
36 dB
11
VSP1221
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SLES012A–SEPTEMBER 2001–REVISED JULY 2004
User DAC1 Register
SD15
MSB
SD0
LSB
SD14 SD13 SD12
SD11
SD10
SD9
SD8
SD7 SD6 SD5
SD4 SD3 SD2 SD1
MSB
LSB
RD/WR
0
0
0
1
0
Reserved
PDZ1
DACIN1
Address
Data
BIT
SD0-DS7
SD8
NAME
DEFAULT VALUE
DESCRIPTION
DACIN1
All 0
0
Eight-bit digital input to DAC1
PDZ1
PDZ1 = 0, DAC1 in power-down mode
PDZ1 = 1, DAC1 in functional mode
SD9
Reserved
0
Reserved
User DAC2 Register
SD15
MSB
SD0
LSB
SD14 SD13 SD12 SD11 SD10
SD9
SD8
SD7 SD6 SD5 SD4 SD3 SD2 SD1
RD/WR
0
0
0
1
1
Reserved
PDZ2
MSB
DACIN2
LSB
Address
Data
BIT
SD0-DS7
SD8
NAME
DEFAULT VALUE
DESCRIPTION
DACIN2
PDZ2
All 0
0
Eight-bit digital input to DAC2
PDZ1 = 0, DAC2 in power-down mode
PDZ1 = 1, DAC2 in functional mode
SD9
Reserved
0
Reserved
OB Register
SD15
MSB
SD0
LSB
SD14 SD13 SD12 SD11 SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
RD/WR
0
0
1
1
0
Reserved
MSB
OBLEVEL
LSB
Address
Data
BIT
NAME
DEFAULT VALUE
DESCRIPTION
SD0-DS9
OBLEVEL
01000000J
(64 LSBs)
OB reference level
Code
OB Level
00000000 0
00000001 1
.
LSB
LSB
.
11111110 254
11111111 255
Reserved
LSBs
LSBs
SD8-SD9
Reserved
All 0
12
VSP1221
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SLES012A–SEPTEMBER 2001–REVISED JULY 2004
Blanking Register
SD15
MSB
SD0
LSB
SD14 SD13 SD12 SD11 SD10
SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
RD/WR
0
0
1
1
1
MSB
BLKGVAL
LSB
Address
Data
BIT
NAME
DEFAULT
VALUE
DESCRIPTION
SD0-
DS9
BLKGVAL
All 0
Output data when BLKG (pin 19) is low
Code
Output data (blanking level)
0000000000
0000000001
.
0
1
LSB
LSB
.
1111111110
1111111111
Reserved
1022
1023
LSBs
LSBs
SD8-
SD9
Reserved
All 0
Signal Polarity Register(1)
SD15
MSB
SD0
LSB
SD14 SD13 SD12 SD11 SD10 SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
RD/WR
0
1
0
0
0
Reserved
SPDZ ADCZ
Data
OBZ
BLZ
CLZ
Address
(1) For this register to take effect, bit SD4 of timing register 1 must be 0.
BIT
NAME
DEFAULT VALUE
DESCRIPTION
CLZ = 0, CLPDM (pin 23) = active low
SD0
SD1
SD2
SD3
SD4
CLZ
0
CLZ = 1, CLPDM (pin 23) = active high
BLZ
0
0
BLZ = 0, BLKG (pin 19) = active low
BLZ = 1, BLKG (pin 19) = active high
OBZ
OBZ = 0, CLPOB (pin 20) = active low
OBZ = 1, CLPOB (pin 20) = active high
ADCZ
SPDZ
Reserved
0
ADCZ = 0, ADCCLK (pin 16) = active low
ADCZ = 1, ADCCLK (pin 16) = active high
0
SPDZ = 0, SHP (pin 21) = active low, SHD (pin 22) = active low
SPDZ = 1, SHP (pin 21) = active high, SHD (pin 22) = active high
SD5-SD9
All 0
Reserved
13
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
Timing Register 1
SD15
MSB
SD0
LSB
SD14 SD13 SD12 SD11 SD10 SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
RD/WR
0
1
0
0
1
Reserved
BYPZ
MSB
ADCDELAY
LSB
Address
Data
BIT
NAME
DEFAULT VALUE
DESCRIPTION
SD0-SD3 ADCDELAY
All 0
Delay ADC clock by programmed value
Delay step = 0.8 ns
Code
0000
0001
.
Delay
0
0.8 ns
.
1110
1111
11.2 ns
12 ns
SD4
BYPZ
1
BYPZ = 0, signal polarity and programmable delay enable(1)
BYPZ = 1, signal polarity and programmable delay disable
SD5-SD9 Reserved
All 0
Reserved
(1) When BYPZ = 0, the internal delays of SHP and SHD increases approximately by 3 ns.
(2)
Timing Register 2
SD15
MSB
SD0
LSB
SD14 SD13 SD12 SD11 SD10 SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
RD/WR
0
1
0
1
0
Reserved
MSB
SHDDELAY
Data
LSB
MSB
SHPDELAY
LSB
Address
(2) For this register to take effect, bit SD4 of timing register 1 must be 0 (see the timing register 1 section.
BIT
NAME
DEFAULT
VALUE
DESCRIPTION
SD0-SD3 SHPDELAY
SD4-SD7 SHDDELAY
SD8-SD9 Reserved
All 0
All 0
All 0
Delay SHP clock by programmed value
Delay step = 0.8 ns
Code
0000
0001
.
Delay
0
0.8 ns
1110
1111
11.2 ns
12 ns
Delay SHD clock by programmed value
Delay step = 0.8 ns
Code
0000
0001
.
Delay
0
0.8 ns
1110
1111
Reserved
11.2 ns
12 ns
14
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
PRINCIPLES OF OPERATION
INTRODUCTION
The principle functions of the VSP1221 are described below. The sections discussed are:
•
•
•
•
•
•
CDS
ADC
PGA
Voltage and current reference
Serial interface
Timing
– SHP, SHD, AND ADCCLK
– CLPDM
– BLKG
– CLPOB
– OE
– RESET
•
•
•
Optical-black calibration
Standby mode
General-purpose DAC
Before describing the individual blocks, a simplified block diagram of the VSP1221 is shown in Figure 8.
CLPOB
OB Reference
OB
Calibration
Circuit
OB DAC
Analog
Digital
PGA
CCD Input
CLPDM
12-Bit
Output
12-Bit
ADC
PGA
CDS
Latch
C
IN
Gain Code
Gain Code
SHP SHD BLKG
ADCCLK
OE
Input
Clamp
Figure 8. Simplified Block Diagram of the VSP1221
CDS
The output signal from the CCD is fed to the correlated double sampler (CDS) through off-chip coupling capacitor
Cin (a 0.22-µF capacitor is recommended for Cin). The CCD signal is sampled twice during one pixel period: at
the reference level (SHP) and at the data level (SHD). Subtracting these two samples extracts the pixel value
and reduces the reset noise and other low-frequency noises that are present at the output of the CCD signal.
ADC
The output analog signal from the analog PGA stage is passed to the 12-bit analog-to-digital converter (ADC).
The ADC employs a three-stage pipelined architecture to achieve high-throughput and low-power consumption.
Fully-differential implementation and digital-error correction ensures 12-bit resolution.
15
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
PRINCIPLES OF OPERATION (continued)
PGA
VSP1221 has a programmable gain amplifier (PGA) which is composed of analog and digital stages. The total
gain range is 0 dB-36 dB in 0.05-dB steps. The gain can be adjusted by programming the PGA register through
the serial port, see the programmable gain amplifier (PGA) register section.
VOLTAGE REFERENCE
All the reference voltages and the bias currents used by the device are created by an internal bandgap circuit.
Connecting an external 100-kΩ resistor from ISET (pin 37) to ground provides the bias current. The voltage at
the ISET pin is 1 V and the reference current is 10 µA (1 V/100 kΩ). The reference voltages for the ADC are
REFP (2.05 V) and REFM (0.75 V). They are available on pins 38 and 39, respectively. The full-scale range of
the ADC is twice the difference between REFP and REFM. Pins REFP and REFM should be heavily decoupled
with appropriate capacitors (1 µF recommended).
SERIAL INTERFACE
Standard Functionality
A simple three-wire (SCLK, SDIN, and SLOAD) serial interface is provided to allow writing/reading the internal
registers of the VSP1221. The serial data SDIN (pin 47) is 16 bits long. The MSB (most significant bit) is set to 0
for writing to and to 1 for reading from the internal registers. Following this, there are five address bits for
accessing and ten data bits for writing to the particular registers. During a read operation, data from the particular
register is available on SDO (pin 1). To enable serial read/write, SLOAD (pin 46) should be pulled low. Sending
blocks of 16-bit data to SDIN can program multiple registers. The polarity of the serial clock (SCLK, pin 48) can
be controlled by SCKP (pin 45). For serial interface timing see the serial data format section; for serial data
format and description of the internal registers see the register description section.
TIMING
A description of the different timing signals of the VSP1221 follows. The timing diagram in the sample and
conversion timing section has additional information. Note that the polarity of SHP/SHD, ADCCLK, CLPDM,
BLKG, and CLPOB can be programmed to be active low or active high (see the signal polarity register section).
The timing diagram in the timing specifications section is based on active-low polarity.
SHP, SHD, and ADCCLK
SHP/SHD are used for correlated double sampling of the CCD signal. Sample reference (SHP) is used to sample
the reference level of the CCD signal, and sample data (SHD) is used to sample the data level. The ADC clock
(ADCCLK) is used to latch the output of the ADC to the external pins. SHP, SHD, and ADCCLK are used to
generate internal timing signals using the on-chip timing generator for proper synchronization of different blocks.
SHP, SHD, and ADCCLK can be internally delayed by programming the timing registers through the serial port
(see the timing register 1 and timing register 2 sections.
The following is recommended to get the best performance:
SHP and SHD must first be aligned based on the CCD signal and timing shown in Figure 2 (tDSHP and tDSHD). It is
observed that if output data switches at the instant of sampling (tDSHP), the device noise performance degrades.
The data switches a few ns after the rising edge of ADCCLK (tOD). To improve performance, ADCCLK can be
varied within the tADC_SHDrange.
CLPDM
The CCD signal is capacitively coupled to the VSP1221 because the dc level of the CCD signal is usually too
high and might damage the chip. The purpose of the CLPDM signal is to clamp the ac-coupling capacitor Cin to
establish the proper dc bias for the CDS. The dc bias for the CDS is set to the clamp voltage, which is around
800 mV below the supply voltage. The clamp voltage can be decoupled with an external capacitor at CLREF (pin
28). This helps in charging the ac-coupling capacitor Cin faster, since the charge will be provided by the
decoupling capacitor. The recommended value for the decoupling capacitor is 1 µF. The dummy pixel clamp
(CLPDM) signal is usually available during the dummy pixels of the CCD and is applied at the line rate of the
CCD sensor.
16
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
PRINCIPLES OF OPERATION (continued)
BLKG
Some CCDs have large transient output signals during blanking intervals. Such signals might drive the VSP1221
into saturation and can cause long recovery times. To prevent this, the VSP1221 has an input-blanking function
which disconnects the CCD input from the CDS when it receives the blanking (BLKG) signal. Additionally, the
output from the VSP1221 during blanking will be equal to the value programmed in the blanking register. The
blanking level can be adjusted by programming the blanking register through the serial port (see the blanking
register section).
CLPOB
The optical-black clamp (CLPOB) pulse is used for optical-black calibration (explained in the optical-black
calibration section). The CLPOB pulse is given to the device during optical-black pixels of the CCD.
OE
Output enable (OE) is used to latch the output data to the output pins. When OE is low, data is latched to the
output pins (D0-D11); when it is high, the output is 3-state.
RESET
When the reset (RESET) signal is pulled low (hardware reset), all the internal registers are reset to their default
values. In addition, the device also has a software-reset option that allows setting the RTSY bit in the control
register through the serial port (see the control register section). See the control register section for the default
values of the internal registers. In addition to resetting the registers, hardware reset also resets the output of the
OB DAC to zero. However, to exactly reset the OB DAC to zero, RESET must be kept low for approximately
600 ns.
OPTICAL-BLACK CALIBRATION
Optical-black calibration (OB) is used to clamp the CCD black level to the user-defined OB reference level. In
CCDs, thermally generated electrons produce a significant amount of charge even at room temperature. So,
even in the absence of light (black level), thermal electrons generate a considerable amount of current in CCDs.
Thus, the CCD black level carries a residual signal, also known as the CCD offset, which is typically in the order
of 50 mV. This residual signal reduces the effective dynamic range of the CCD input, resulting in a degradation
of image quality. An offset voltage must be subtracted from the CCD black level so that the difference between
the CCD black level and the offset voltage is equal to the reference OB level programmed by the user. The
reference OB level is much lower than the CCD black level, so that the effective dynamic range of the CCD input
increases and the image quality improves. The offset voltage has to be determined based on the CCD black
level. There are certain CCD pixels which are not exposed to light (optical-black pixels) and the CCD signal
corresponding to these pixels represent the CCD black level. Thus, the offset voltage is determined during the
optical-black pixels, and the offset voltage is kept constant and is subtracted from the CCD input to cancel the
CCD offset during normal image pixels.
OB calibration in the VSP1221 is done in a closed feedback loop. The difference between the CCD black level
and the offset voltage is compared with the user-defined OB reference level at the output of the digital PGA
stage. The error is fed to an OB calibration circuit which generates a step proportional to the error and a sign
based on the sign of the error. The step and the sign are then given to the OB DAC, which generates an analog
voltage that updates the offset voltage at the input of the CDS. If the error is positive, the offset voltage is
increased; if the error is negative, the offset voltage is decreased. This continues in a closed feedback loop until
the difference between the CCD black level and the offset voltage converges to the OB reference level. The OB
calibration circuit has been designed so that a 100-mV CCD black level converges to zeroreference OB level
within 500-750 pixel clocks. Convergence time increases with an increase in gain. Convergence is faster if the
CCD black level is smaller than 100 mV. A plot of the convergence time as a function of the PGA gain is shown
in the performance plots section. Since the feedback loop includes the CDS, the PGA, and the ADC, it also
cancels any offset introduced by these blocks. The OB reference level can be adjusted by programming the OB
register through the serial port (see the OB register section).
17
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
PRINCIPLES OF OPERATION (continued)
STANDBY (POWER-DOWN MODE)
To save power, the VSP1221 can be put into standby mode (power-down mode) both through hardware and
software. Pulling the STBY signal low puts the device into standby mode (hardware power-down). In this mode,
the reference is pulled down, all the functional blocks are disabled, the output is all zero, and the power
dissipation is zero. The power-up time is of the order of 10 ms. Software power down can be exercised by
resetting the STBYZ bit in the control register through the serial port (see the control register section). This is
similar to hardware power down, except that the reference is not pulled down. Hence, the power dissipation is
around 4 mW and the power-up time is of the order of 10 µs. The user can still program all the internal registers
during both hardware and software power down.
GENERAL PURPOSE DAC
The VSP1221 has two 8-bit general-purpose digital-to-analog converters (DACs) that can be used for external
analog settings. The output voltage of each DAC can be independently set and has a range of 0 V to the supply
voltage with eight-bit resolution. The digital input to the DACs can be set by programming the User DAC1 and
User DAC2 registers through the serial port (see the User DAC1 register and User DAC2 register sections).
When not used in the system, the DACs can be put in standby mode by programming the above-mentioned
registers. The DACs are, by default, in standby mode. The average power consumed by each DAC is
approximately 1 mW.
18
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
APPLICATION INFORMATION
3 V
0.1 µF
48 47 46 45 44 43 42 41 40 39 38 37
0.1 µF
D0/SDO
D1
DACO2
36
1
AVSS
35
2
D2
D3
D4
D5
DACO1
34
3
AVDD
TP2
PIN
DIN
33
4
32
Buffer
0.22 µF
5
31
6
VSP1221
CCDOUT
ICX205
D6
30
7
D7
D8
D9
D10
D11
TP1
0.22 µF
29
28
27
26
25
8
CLREF
AVDD
AVSS
VSS
(CCD)
9
10
11
12
1 µF
13 14 15 16 17 18 19 20 21 22 23 24
0.1 µF
CLAMP
0.1 µF
SR
SV
CXD2460
(Timing Generator)
OBCLP
BLKG
ADCCLK
0.1 µF
Data
PIXEL CLOCK
LINE CLOCK
FRAME CLOCK
Serial
Interface
Signal Processor
Block
Figure 9. Application Diagram of the VSP1221
NOTE:
The application circuits shown are typical examples of the operation of the devices.
Texas Instruments cannot assume responsibility for any problems arising out of the
use of these circuits or for any infringement of third-pary patents and other rights due
to the same.
CCD INPUT
The CCD output may need an off-chip external buffer in order to drive the input capacitive load of the VSP1221.
The buffer output is applied to DIN (pin 30) through an ac-coupling capacitor. It is advisable to connect PIN (pin
31) to the buffer ground through a similar ac-coupling capacitor for the following reason: since the input stage of
the VSP1221 is differential, the input to the CDS is the voltage difference between DIN and PIN. Hence, if the
noise path for DIN and PIN are similar, the noise can be effectively cancelled. This is not the case if the noise
paths are different. However, PIN can also be connected directly to ground.In this case, bit SD8 (CLAMPPIN) of
the control register should be 1 (see the control register section). If PIN is connected to an ac-coupling capacitor,
it is recommended to set bit SD8 (CLAMPPIN) of the control register to 0 so that the ac-coupling capacitor is
charged to a fixed clamp voltage. The recommended value for the ac coupling capacitor is 0.22 µF.
19
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
APPLICATION INFORMATION (continued)
REFERENCE DECOUPLING
Pins REFP (pin 38) and REFM (pin 39) should be connected to ground by means of decoupling capacitors. A
1-µF ceramic capacitor is recommended for reference decoupling. For better high-frequency decoupling, 0.1 µF
ceramic capacitors may be used in parallel. The decoupling capacitors should be placed as close as possible to
the reference pins.
CLAMP DECOUPLING
To decouple the clamp voltage, a 1-µF ceramic capacitor may be connected to CLREF (pin 28). See the
CLPDMsection for further details.
INTERNAL BIAS CURRENT SETTING
To set the internal bias current, ISET (pin 37) should be connected to ground through a 100-kΩ resistor.
However, no capacitor should be connected to the ISET pin.
POWER SUPPLY, GROUNDING, AND DEVICE DECOUPLING
The VSP1221 has several power-supply pins. Each major internal analog block has a dedicated AVDD supply
pin (pins 27, 33, and 40). The DVDD supply pin (pin 17) powers all internal digital circuitry. Both AVDD and
DVDD work with 3-V power supplies. DIVDD and DIGND (pins 13 and 14) supply power to the output digital
driver (D0-D11). DIVDD is independent of DVDD and can be operated from 1.8 V to 3.3 V. This allows the
outputs to interface with digital ASICs requiring different supply voltages
General design practices should apply to the PCB to limit high-frequency transients and noise that are fed back
into the supply lines. This requires adequate bypassing of the supply pins. In the case of power supply
decoupling, 0.1-µF ceramic capacitors are sufficient to keep the impedance low over a wide frequency range.
Since their effectiveness depends largely on the proximity to the individual supply pin, all decoupling capacitors
should be placed as close as possible to the supply pins.
To reduce high-frequency and noise coupling, it is highly recommended to short the digital and analog grounds
immediately outside the package. This can be accomplished by running a low-impedance line under the package
between pins DVSS and AVSS.
DATA OUTPUT
It is recommended to keep the capacitive loading on the output data lines as low as possible (typically less than
15 pF). Larger capacitive loads demand higher charging-current surges, which can feed back into the analog
portion of the VSP1221 and affect its performance. If the data lines are long, it is advisable to use external
buffers or latches, which also provides the added benefit of isolating the VSP1221 from any digital noise that
may couple back. In addition, resistors in series with each data line helps in minimizing the surge current. Typical
resistor values are 40-50 Ω .
20
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
APPLICATION INFORMATION (continued)
Optical Black
Pixels
Dummy
Pixels
Active Image
Pixels
N
N+1
DIN
(CCD IN)
SHP
SHD
CLPOB
BLKG
CLPDM
ADCCLK
N−9 N−8 N−7
D0–D11
12 Clocks
12 Clocks
OB Calibration Cycle
A. OB Calibration latency is 12 clocks. So, OB update starts 12 clocks after CLPOB is pulled low and stops 12 clocks
after CLPOB is pulled high.
B. If active image pixels are located immediately after CLPOB goes high, the OB update will affect the adjacent 12
pixels.
C. The device clocks are stopped during BLKG and CLPDM. Therefore, if these signals appear immediately after
CLPOB goes high, the OB calibration update for the subsequent 12 clocks will stop. So, its recommended to delay
BLKG and CLPDM by at least 12 pixels after CLPOB goes high.
Figure 10. System Timing Diagram Example
21
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
APPLICATION INFORMATION (continued)
PERFORMANCE PLOTS
INPUT-REFERRED NOISE
RMS OUTPUT-REFERRED NOISE
vs
vs
GAIN
GAIN
180
160
140
120
100
80
20
16
12
8
4
60
0
0
4
8
12 16
Gain − dB
Figure 11.
20 24
28 32 36
0
4
8
12 16
20 24
28 32 36
Gain − dB
Figure 12.
PGA ACT GAIN
vs
REGISTER VALUE
36
32
28
24
20
16
12
8
4
0
1
101
201
301
401
501
601
701
PGA Gain Register Value
Figure 13.
22
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
APPLICATION INFORMATION (continued)
INL GRAPH
2
1.5
1
0.5
0
−0.5
−1
−1.5
0
1000
2000
3000
4000
Figure 14.
DNL GRAPH
0.8
0.6
0.4
0.2
0
−0.2
−0.4
−0.6
−0.8
0
1000
2000
3000
4000
Figure 15.
23
VSP1221
www.ti.com
SLES012A–SEPTEMBER 2001–REVISED JULY 2004
APPLICATION INFORMATION (continued)
POWER CONSUMPTION
OPTICAL-BLACK-VALUE CONVERGENCE
vs
vs
FREQUENCY
NUMBER OF ADCCLKs
85
80
75
70
65
60
55
50
45
40
900
800
700
600
500
400
300
200
100
0
1
201
401
601
801
1001 1201
5
12.5
20
f − Frequency − MHz
Number of ADC Clocks
Figure 16.
Figure 17.
24
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
M
0,08
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
Gage Plane
6,80
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4073176/B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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