VSP2100 [BB]
CCD SIGNAL PROCESSOR For Digital Cameras; CCD信号处理器为数码相机
| 型号： | VSP2100 |
| 厂家： | 
BURR-BROWN CORPORATION |
| 描述： | CCD SIGNAL PROCESSOR For Digital Cameras |
| 文件： | 总13页 (文件大小：219K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
VSP2100
VSP2100
TM
CCD SIGNAL PROCESSOR
For Digital Cameras
DESCRIPTION
FEATURES
The VSP2100Y is a complete digital camera IC, pro-
viding signal conditioning and 10-bit analog-to-digital
conversion for the output of a CCD array.
● CCD SIGNAL PROCESSING:
Correlated Double Sampling
Black Level Clamping
0 to +34dB Gain Ranging
High SNR: 53dB
The primary CCD channel provides correlated double
sampling to extract the video information from the
pixels, 0dB to +34dB gain ranging with digital control
for varying illumination conditions, and black level
clamping for an accurate black reference.
● 10-BIT A/D CONVERSION:
Up to 27MHz Conversion Rate
No Missing Codes
● PORTABLE OPERATION:
Low Voltage: 2.7V to 3.6V
Low Power: 190mW at 3.0V
Input signal clamping and offset correction of the CDS
is also performed. The stable gain control is linear in
dB. Additionally, the black level is quickly recovered
after gain change. An on-chip general purpose 10-bit
digital-to-analog converter allows you to obtain ana-
log control voltage for iris control.
● LOW POWER: 160mW at 2.7V
● POWER-DOWN MODE: 18mW
The VSP2100Y is available in a 48-lead LQFP pack-
age and operates from a single +3V supply.
APPLICATIONS
● VIDEO CAMERAS
● DIGITAL STILL CAMERAS
● PC CAMERAS
● SECURITY CAMERAS
OB
REFCK DATCK WRT SD SCLK
DAC OUT
ADCK DRVDD
C
10-Bit
D/A Converter
(DAC1)
Serial Port
Register
A/D
Timing Control
10-Bit
Black Level
Auto-Zero
D/A Converter
(DAC0)
CCD D
Correlated
Double
Sampling
10-Bit
A/D
Converter
10-Bit
Digital
Output
Output
Latch
Log VCA
+6dB
+28dB
CCD Out
CCD R
Clamp
Dummy
Pixel
Auto- Zero
A/D
Reference
DUMC
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
FAXLine: (800) 548-6133 (US/Canada Only)
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
•
Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1998 Burr-Brown Corporation
PDS-1469A
Printed in U.S.A. September, 1998
SPECIFICATIONS
At TA = +25°C, all power supply voltages = +3.0V, and conversion rate = 18MHz, unless otherwise specified.
VSP2100Y
TYP
PARAMETER
RESOLUTION
CONDITIONS
MIN
MAX
UNITS
10
Bits
DIGITAL INPUT
Logic Family
Logic Levels
CMOS
Logic HI
Logic LO
Logic HI, VIN = +3V
Logic LO, VIN = 0V
2.5
0
V
V
µA
µA
%
+0.4
10
10
Logic Currents
A/D Clock Duty Cycle
50
DIGITAL OUTPUT
Logic Family
CMOS
Logic Levels
Logic HI, CL = 10pF
Logic LO, CL = 10pF
2.5
0
3
+0.4
V
V
ANALOG OUTPUT
General Purpose D/A Converter Output
DAC Settling TIme
0.3
2.4
V
µs
1.0
TRANSFER CHARACTERISTICS
Differential Non-Linearity
Integral Non-Linearity
±0.4
±2.0
LSB
LSB
No Missing Codes
Guaranteed
Signal Settling Time
Black to Full-Scale Change
to 1/4 LSB into A/D
110
27
ns
Conversion Rate
Data Latency
Signal-to-Noise Ratio(1)
500kHz
MHz
Clocks
dB
5.5
53
Grounded Input Cap,
VCA Gain max
Black Clamp Level
32
11
LSB
ns
CDS
Data Settling Time to ±0.1% for FS Change
with RS = 40
From Leading Edge
of DATCK
Input Capacitance
Input Time Constant
Data Full-Scale Input
DATCK LOW
20
300
pF
ps
mV
After AC-Coupling Cap
600
INPUT CLAMP
Clamp-On Resistance
Clamp Level
3.3
1
kΩ
V
VCA CHARACTERISTICS
Gain Control Voltage Range
Gain at Control Voltage, max
Gain at Control Voltage, min
Gain Control Linearity
0.3
32
2.4
V
dB
dB
dB
µs
34
–2
±1.0
10
Gain Control Settling Time
Transfer Function
17
dB/V
POWER SUPPLY
Rated Voltage
Quiescent Current
Power Dissipation
Power-Down Mode
+2.7
–25
+3.0
63
190
18
+3.6
+85
V
mA
mW
mW
TEMPERATURE RANGE
Specified Range
Ambient
°C
Thermal Resistance, θJA
48-Lead LQFP
100
°C/W
NOTE: (1) SNR = 20log (full-scale voltage/rms noise).
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
2
VSP2100
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
Power Supply (+VS) ............................................................................. +6V
Analog Input .............................................................. –0.3V to (+VS +0.3V)
Logic Input ............................................................... –0.3V to (+VS +0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ...................................................... –40°C to +150°C
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
VSP2100Y
"
48-Lead LQFP
"
340
"
–25°C to +85°C
VSP2100Y
"
VSP2100Y
VSP2100Y/2K
50-Piece Tray
Tape and Reel
"
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP2100Y/2K” will get a single 2000-
piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book.
®
3
VSP2100
PIN CONFIGURATION
48 47 46 45 44 43 42 41 40 39 38 37
DVSS1
1
2
3
4
5
6
7
8
9
36 WRT
35 SCLK
34 SD
B10 (LSB)
B9
B8
B7
B6
B5
B4
B3
33 AVDD2
32 LCM
31 AVSS4
30 TP2
VSP2100Y
29 TP1
28 AVSS2
27 CCD R
26 CCD D
25 AVSS1
B2 10
B1 (MSB) 11
DRVDD 12
13 14 15 16 17 18 19 20 21 22 23 24
PIN DESCRIPTIONS
PIN DESIGNATOR
DESCRIPTION
PIN
DESIGNATOR
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
DVSS1
B10 (LSB)
B9
Digital Ground
Bit 10, ADC Output, Least Significant Bit
Bit 9, ADC Output
Bit 8, ADC Output
Bit 7, ADC Output
Bit 6, ADC Output
Bit 5, ADC Output
Bit 4, ADC Output
Bit 3, ADC Output
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
C
AVSS1
CCD D
CCD R
AVSS2
TP1
TP2
AVSS4
LCM
AVDD2
SD
SCLK
WRT
2.4V
CM
AVDD3
AVDD4
RESET
DACOUT
AVDD5
AVDD6
AVSS5
AVSS6
REFN
REFP
Capacitor for Optical Feedback Loop
Analog Ground
CCD Signal Input
Capacitor for Dummy Feedback Loop
Analog Ground
Test Pin 1, Open
Test Pin 2, Open
Analog Ground
Attenuator Common-Mode Bypass
Analog Power Supply
Serial Data Input for D/A Converters
Clock for Serial Data Input
Write Pulse for Serial Data Input, Rising Edge Trigger
Attenuator Ladder Bypass
ADC Common-Mode Voltage
Analog Power Supply
B8
B7
B6
B5
B4
B3
B2
Bit 2, ADC Output
B1 (MSB)
DRVDD
DRVSS
DVSS2
DVSS3
ADCK
DVDD
PD
Bit 1, ADC Output, Most Significant Bit
Digital Power Supply for Digital Outputs (B1-B10)
Digital Ground for Digital Outputs (B1-B10)
Digital Ground
Digital Ground
Clock for Digital Data Output Latch
Digital Power Supply
Power Down: LOW = Normal Operation
HIGH = Reduced Power (digital
output= 0000000000)
Preblanking: LOW = ADC Output: –FS +32LSB
HIGH = ADC Output: Normal
Optical Black Clamp Pulse, Active LOW
CDS Reference Sampling Pulse, Active LOW
CDS Data Sampling Pulse, Active LOW
Dummy Clamp, Active LOW
Analog Power Supply
Resets DAC Registers, Active LOW
D/A Converter (DAC1) Output
Analog Power Supply
Analog Power Supply
Analog Ground
Analog Ground
ADC Negative Reference, Bypass to Ground
ADC Positive Reference, Bypass to Ground
19
PB
20
21
22
23
OB
REFCK
DATCK
DUMC
®
4
VSP2100
SERIAL CONTROL DATA FORMAT FOR DAC0/DAC1
TIMING SPECIFICATIONS FOR SERIAL REGISTERS
Timing Specifications = tMIN to tMAX with +3V power supply.
BIT
NO. DESIGNATOR DESCRIPTION
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
1
2
A1
A0
Start Bit. Either HIGH or LOW will be acceptable.
Address Bit. Selects internal DACs.
LOW = DAC0, VGA control DAC
HIGH = DAC1, general purpose DAC
tCKP
tCKL
tCKH
tSD
Serial Clock Period
Serial Clock Pulse Width LOW
Serial Clock Pulse Width HIGH
Data Setup Time
100
50
50
50
25
100
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
4
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Digital Input Data for DAC, Bit 10 (MSB)
Digital Input Data for DAC, Bit 9
Digital Input Data for DAC, Bit 8
Digital Input Data for DAC, Bit 7
Digital Input Data for DAC, Bit 6
Digital Input Data for DAC, Bit 5
Digital Input Data for DAC, Bit 4
Digital Input Data for DAC, Bit 3
Digital Input Data for DAC, Bit 2
Digital Input Data for DAC, Bit 1 (LSB)
tHD
Data Hold Time
5
tSW
tW
tWD
tRS
Write Pulse Setup Time
Write Pulse Width
6
7
8
Data Valid Delay Time
Register Reset Pulse Width
Register Reset Delay Time
9
10
11
12
tRSD
TIMING FOR SERIAL PORT WRITING
tCKH
tCKL
SCLK
tCKP
Must be LOW before WRT goes HIGH
tSD
A0
tHD
D8
A1
D9
D7
D6
D5
D4
D3
D2
D1
D0
SD
WRT
tW
tSW
tWD
DATA
Valid
TIMING FOR REGISTER RESET
tRS
RESET
tRSD
REGISTER
DATA
All Zeros
TIMING FOR PREBLANKING
PB Mode
ADCK
5.5 Clocks
t7
t7
5.5 Clocks
DIGITAL OUTPUT
PB Mode
®
5
VSP2100
TIMING DIAGRAMS
9.5MHz
0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns
106
RESET
HI
56
CCD OUT
132
132
151
REFCK
DATCK
26
26
45
80
79
96
ADCK
OB
19
159
DUMC
24
127
167
81
88
OUTPUT DATA
DATA VALID
DATA VALID
14MHz
0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns
RESET
HI
39
CCD OUT
REFCK
DATCK
21
21
37
54
69
56
91
161
ADCK
OB
28
69
168
208
DUMC
–7
33
DATA VALID
136
176
DATA VALID
58
65
OUTPUT DATA
®
6
VSP2100
TIMING DIAGRAMS (CONT)
18MHz
0ns 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns 90ns 100ns 110ns 120ns 130ns 140ns 150ns 160ns 170ns 180ns 190ns 200ns
RESET
HI
27.7
55.5
CCD OUT
REFCK
DATCK
18
18
32
46
46
60
74
130
ADCK
OB
24
64
DUMC
48
55
OUTPUT DATA
DATA VALID
DATA VALID
DATA VALID
CDS/ADC TIMING DIAGRAM
18MHz
Feedthrough Data Output Interval
CDS Input
(CCD Output)
N
N + 1
N + 2
t1
REFCK
(Pin 21)
t0
t3
DATCK
(Pin 22)
t2
t6
ADCK
(Pin 16)
t4
t5
t7
DIGITAL OUTPUT
(Pins 2-11)
N - 7
N - 6
N - 5
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
t0
t1
REFCK Pulse Width
REFCK Samling Delay
DATCK Pulse Width
DATCK Sampling Delay
ADCK Pulse Width
ADCK Delay
11
1.5
11
14
2
ns
ns
ns
ns
ns
ns
ns
t2
14
2
t3
1.5
18.5
0
t4, t5
t6
27
13
8.3
26
t7
Output Data Delay(1)
7.1
9.5
NOTE: (1) CLOAD = 5pF.
®
7
VSP2100
TYPICAL HORIZONTAL INTERVAL TIMING
Dummy
Pixel
Video
Video
Blanking
Interval
CCD
Optical Black
OB
DUMC
PB
Black Level
OUTPUT
Video
Video
®
8
VSP2100
TYPICAL PERFORMANCE CURVES
At TA = +25°C, all power supply voltages = +3.0V, and conversion rate = 18MHz, unless otherwise specified.
VCA CHARACTERISTICS
QUIESCENT CURRENT vs POWER SUPPLY
40
35
30
25
20
15
10
5
100
80
60
40
20
0
2.7V
3.0V
3.6V
3.3V
0
–5
2.7
3.0
3.3
Power Supply Voltage (V)
DAC0 Code (LSB)
®
9
VSP2100
CORRELATED DOUBLE SAMPLER (CDS)
THEORY OF OPERATION
The CDS removes low frequency noise from the output of
the image sensor. Refer to Figure 2 which shows a block
diagram of the CDS. The output from the CCD array is
sampled during the reference interval as well as during the
data interval. Noise that is present at the input and is of a
period greater than the pixel interval will be eliminated by
subtraction.
The VSP2100 is an integrated circuit that contains many of
the key features associated with the processing of analog
signals in a video camera or a digital-still camera. Figure 1
shows a simplified block diagram of the VSP2100.
The output from the CCD array is first sent to a Correlated
Double Sampler (CDS), then a voltage-controlled attenuator
with a logarithmic control characteristic, and an output
amplifier prior to being applied to the input of a 10-bit A/D
converter.
The VSP2100 employs a three track/hold correlated double
sampler architecture. Track/Hold 2 is sampled during the
reference interval by the REFCK signal. Track/Hold 3 is
resampled at the same time that the data Track/Hold 1 is
sampled by the DATCK signal. This is done to remove large
transients from Track/Hold 2 that results from a portion of
the reset transient being present during the acquisition time
of this track and hold. The output of Track/Hold 2 is buffered
by a voltage follower.
Two calibration cycles are employed to reduce the offset
variation of the VSP2100. During the dummy pixel time, an
input auto-zero circuit is activated that eliminates the offset
of the correlated double sampler. During the optical black
timing interval, another auto-zero circuit is employed to
eliminate the offset associated with the output amplifier and
the remaining offset from the CDS.
Dummy
Feedback
Loop
Black Level
Auto-Zero
Loop
ADCK
DUMC
OB
10-Bit
27MHz
A/D
CDS
VCA
Digital Output
CCD Input
Output
Amplifier
Clamp
REFCK DATCK
Gain Control
FIGURE 1. Simplified Block Diagram of VSP2100.
T/H1
Data Sampling Channel
CCD
Input
To VCA
Reference Sampling
Channel
T/H3
T/H2
1V
DUMC REFCK
DATCK
FIGURE 2. Block Diagram of Correlated Double Sampler.
®
10
VSP2100
DIFFERENCE AMPLIFIER
pixel auto-zero loop is in operation. The duty cycle (D) must
be considered as the loop operates in a sampled mode.
Operation of the dummy auto-zero loop is activated by the
DUMC signal that happens once during each horizontal line
interval.
The correlated double sampler function is completed when
the output of the data and reference channel are sent to the
difference amplifier where the signals are subtracted. In
addition to providing the difference function, the difference
amplifier amplifies the signal by a factor of 2 which helps
to improve the overall signal-to-noise ratio. The difference
amplifier also generates a differential signal to drive the
voltage-controlled attenuator.
TIMING
The REFCK and DATCK signals are used to operate the
CDS as previously explained. These same two signals are
also used by internal timing circuitry to create the necessary
timing signals for the A/D. The output from the A/D is read
out to external circuitry by the ADCK signal. DUMC is used
to activate the dummy pixel auto-zero loop and OB is used
to activate the black level auto-zero loop. The input digital
timing signals REFCK, DATCK, DUMC and OB are ca-
pable of being driven from either 3V or 5V logic levels.
INPUT CLAMP
The output from the CCD array is capacitively coupled to the
VSP2100. To prevent shifts in the DC level from taking place
due to varying input duty cycles, the input capacitor is
clamped during the dummy pixel interval by the REFCK
signal and the DUMC signal. A P-channel transistor is used
for this input clamp switch to allow a 2V negative change at
the input that would bring the signal below ground by 1.
Under typical conditions, the bias at the input to the VSP2100
is at 1V.
VOLTAGE-CONTROLLED ATTENUATOR
To maximize the dynamic range of the VSP2100, a voltage-
controlled attenuator is included with a control range from
0dB to –34dB. The gain control has a logarithmic relation-
ship between the control voltage and the attenuation. The
attenuator processes a differential signal from the difference
amplifier to improve linearity and to reject both power supply
and common-mode noise. The output from the attenuator is
amplified by 28dB prior to being applied to the A/D. A
typical gain control characteristic of the VSP2100 is shown
in the typical performance curve, “VCA Characteristics”.
DUMMY PIXEL AUTO-ZERO LOOP
The output from the data and reference channel is processed
by the previously mentioned difference amplifier. The dif-
ferential output from the difference amplifier is sent to both
the voltage-controlled logarithmic attenuator and to an error
amplifier. The error amplifier amplifies and feeds a signal to
the difference amplifier to drive the offset measured at the
output of the difference amplifier to zero. A block diagram
of this circuit is shown in Figure 3. This error amplifier
serves the purpose of reducing the offset of the CDS to avoid
a large offset from being amplified by the output amplifier.
BLACK LEVEL AUTO-ZERO LOOP
The black level auto-zero loop amplifies the difference
between the output of the output amplifier and a reference
signal during the optical black timing interval. This differ-
ence signal is amplified and fed back into the output ampli-
fier to correct the offset. In doing so, the output level of the
entire CCD channel can be controlled to be approximately –
FS + 32LSBs under zero input signal conditions. The black
level auto-zero loop is activated by the OB timing signal.
The effective time constant of this loop is given by:
RC
T =
AD
where R is 10kΩ, C is an external capacitor connected to pin
27 (CCD R), A is the gain of the error amplifier with a value
of 50, and D is the duty cycle of the time that the dummy
Figure 4 shows a block diagram of the black level auto-zero
loop. The loop time constant is given by:
C
T =
(GM) (D)
To VCA
CCD
Input
CDS
Output Amplifier
From
VCA
To ADS
32LSB
A
Error
Amplifier
GM
Error
Amplifier
R
CCD R
C
C
C
DUMCK
OB
FIGURE 4. Black Level Auto-Zero Loop.
VSP2100
FIGURE 3. Block Diagram of Dummy Pixel Loop.
®
11
where C is the external filter capacitance applied to pin 24
(C), GM is .001Ω and D is the duty cycle of the time that the
black level auto-zero loop is in operation. The duty cycle (D)
must be considered as the loop operates in a sampled mode.
Operation of the black level auto-zero loop is activated by
the OB signal that happens once during each horizontal line
interval.
DECOUPLING AND GROUNDING
CONSIDERATIONS
The VSP2100 has several supply pins, one of which is
dedicated to supply only the digital output driver (pin 12,
DRVDD). The remaining supply pins are not, as is often the
case, divided into analog and digital supply pins since they
are internally connected on the chip. For this reason, it is
recommended that the VSP2100 be treated as an analog
component and be powered from the analog supply only.
Digital supply lines often carry high levels of wide band
noise which can couple back into the VSP2100 and limit
performance.
A/D CONVERTER
The A/D converter utilizes a pipline architecture. The fully
differential topology and digital error correction guarantee
10-bit resolution. The A/D converter circuitry includes a
reference circuit that provides bias voltages for the entire
system.
Figure 5 shows the recommended decoupling scheme for the
VSP2100. In most cases, 0.1µF ceramic chip capacitors are
adequate to keep the impedance low over a wide frequency
range. Their effectiveness largely depends on the proximity
to the individual pin. Therefore, they should be located as
close as possible to the pins. In addition, one larger capacitor
(1µF to 22µF) should be placed on the PC board in proxim-
ity of the VSP2100.
SERIAL INTERFACE AND DACs
The VSP2100 incorporates two identical 10-bit DACs (DAC0
and DAC1). DAC0 is for controlling the amount of attenu-
ation of the log Voltage Controlled Attenuator (VCA) and
DAC1 is for user-defineable options such as iris control.
The input data for these DACs are set by the written data
through the serial interface. The serial port has an 12-bit
register which is controlled by four signals (SD, SCLK,
WRT, RESET). SD is the serial data input, SCLK is the
clock for the serial data, WRT pulse takes the serial register
data into another internal parallel register at the rising edge,
RESET resets all the registers’ data to zeros asynchronously
when RESET = LOW. The serial register uses master-slave
dual flip-flops and the master flip-flop receives the input
data at the rising edge of SCLK and transmits this data into
the slave at the falling edge of SCLK. Therefore, the clock
SCLK must be normally LOW.
OTHER RECOMMENDATIONS
DRVDD is a power supply used exclusively for the digital
output driver and should not be connected to AVDD and
DVDD, even if the power supply voltage is the same. The
voltage level difference between DRVDD, AVDD, and DVDD
should be kept less than 0.3V.
If your PC board has analog and digital ground, AVSS, DVSS,
and DRVSS should be connected to analog ground.
DEMONSTRATION BOARD
A demonstration board, DEM-VSP2100, is available to
assist in the inital evaluation of the circuit performance
using the VSP2100. The schematic of the DEM-VSP2100 is
shown in Figure 5.
When the DAC input data is all zeros, this corresponds to a
maximum output voltage of 2.4V. In a similar manner, all
ones correspond to a DAC output voltage of 0.3V. The VCA
attenuation is at a minimum—which is the same as the
channel gain being a maximum—when the DAC voltage is
at 0.3V.
The serial data format and the related signal timing are
shown page 5. When the input serial data is longer than 12
bits, the last 12 bits become effective and the former bits are
erased.
When the registers are reset, the user should be careful that
the channel gain setting becomes maximum and DAC1
output voltage goes to maximum.
®
12
VSP2100
5
4
3
2
1
S S
D R V
S S 2 D V
S S 3 D V
R E F P
R E F N
S S 6 A V
A D C K
S S 5 A V
D D D V
P D
D D 6
A V
D D 5
A V
P B
D A C O U T
R E S E T
O B
D D 4
R E F C K
A V
D D 3
D A T C K
D U M C
A V
C M
2 . 4 V
C
2
4
6
8
1
3
5
7
9
1 0
1 2 1 1
1 4 1 3
1 6 1 5
1 8 1 7
2 0 1 9
2 2 2 1
2 4 2 3
2 6 2 5
2 8 2 7
3 0 2 9
FIGURE 5. DEM-VSP2100Y Schematic.
®
13
VSP2100
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