VSP2080T/2K [TI]
SPECIALTY CONSUMER CIRCUIT, PDSO20, TSSOP-20;
| 型号： | VSP2080T/2K |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SPECIALTY CONSUMER CIRCUIT, PDSO20, TSSOP-20 光电二极管 商用集成电路 |
| 文件： | 总9页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
®
VSP2080
VSP2080
®
TM
CCD SIGNAL FRONT-END
PROCESSOR FOR DIGITAL CAMERAS
DESCRIPTION
FEATURES
The VSP2080 is a complete front-end processing IC
for digital cameras. The VSP2080 provides signal
conditioning for the output of a CCD array. The
VSP2080 provides correlated double sampling to ex-
tract the video information from the pixels, 0dB to
+34dB gain range with analog control for varying
illumination conditions, and black level clamping for
an accurate black reference. The stable gain control is
linear in dB. Additionally, the black level quickly
recovers after screen changes. The MODE pin allows
the selection of logic-input polarity. The VSP2080 is
available in a 20-lead TSSOP package.
● CCD SIGNAL PROCESSING
Correlated Double Sampling
Black Level Clamping
0 to +34dB Gain Range
55dB SNR Referred to Full Scale
● SELECTABLE LOGIC-INPUT POLARITY
Positive Active or Negative Active
● PORTABLE OPERATION
Low Voltage: 2.7V to 3.6V
Low Power: 144mW at 3.0V
Power-Down Mode: 10mW
APPLICATIONS
● VIDEO CAMERAS
● DIGITAL STILL CAMERAS
● PC CAMERAS
● SECURITY CAMERAS
MODE
REFCK
DATCK
AGC IN
OB
C
Logic Input
Polarity
Control
Optical
Black Level
Auto-Zero
Clamp
OUT
+28dB
Correlated
Double
Sampling
CCD D
CCD R
Log
VCA
CCD
OUT
+6dB
Dummy
Pixel
Internal
Bias
Auto-Zero
Generator
DUMC
REFT
REFB REF IN
International Airport Industrial Park
•
Mailing Address: PO Box 11400, Tucson, AZ 85734
•
Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706
• Tel: (520) 746-1111
Twx: 910-952-1111 Internet: http://www.burr-brown.com/
•
•
Cable: BBRCORP Telex: 066-6491
•
•
FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132
•
©1998 Burr-Brown Corporation
PDS-1498B
Printed in U.S.A. August, 1999
SBMS004
SPECIFICATIONS
At TA = +25°C, and VDDA = +3.0V, unless otherwise specified.
VSP2080T
TYP
PARAMETER
CONDITIONS
MIN
MAX
UNITS
DIGITAL INPUT
Logic Family
Logic Levels
CMOS
Logic HI
Logic LO
2.5
0
+VDDA
+0.4
10
V
V
Logic Currents
Logic HI, VIN = +VDDA
Logic LO, VIN = 0V
µA
µA
10
ANALOG OUTPUT
Output Voltage
1.0
1.010
0.90
2.0
1.045
1.1
V
x REF IN
V
Output Black Level
Reference Input (REF IN)
1.030
1.0
TRANSFER CHARACTERISTICS
Signal-to-Noise Ratio(1)
Grounded Input Cap,
Gain Min
55
31
dB
Black Clamp Level
mV
CDS
Data Settling Time to ±0.1% for FS Change
with RS = 40
From Leading Edge
of DATCK
11
ns
Input Capacitance
DATCK LOW
20
pF
ps
Input Time Constant
Full-Scale Input Voltage
300
After AC-Coupling Cap
600
0.7
mV
INPUT CLAMP
Clamp-On Resistance
Clamp Level
3.3
1
kΩ
V
GAIN CONTROL CHARACTERISTICS
Linear Gain Control Voltage Range
Gain at Max Control Voltage
Gain Control Linearity
2.3
V
dB
34
±1.0
10
dB
Gain Control Settling Time
Transfer Function
µs
Linear Range
20.6
dB/V
POWER SUPPLY
Rated Voltage
+2.7
–25
+3.0
48
+3.6
+85
V
Current, Quiescent
Power Dissipation
Power-Down Mode
mA
mW
mW
144
10
TEMPERATURE RANGE
Specified Range
Ambient
°C
Thermal Resistance, θJA
20-Lead TSSOP
130
°C/W
NOTE: (1) SNR = 20log (full-scale voltage/rms noise).
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN
assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject
to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not
authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.
®
2
VSP2080
PIN CONFIGURATION
PIN DESCRIPTIONS
PIN DESIGNATOR
TYPE
DESCRIPTION
Top View
TSSOP
1
2
LCM
2.4V
Bypass
Bypass
Attenuator Common-Mode Bypass,
Bypass to GND with 0.1µF capacitor
LCM
2.4V
1
2
3
4
5
6
7
8
9
20 REF IN
19 REFB
18 REFT
17 VDDA
Attenuator Ladder Bypass,
Bypass to GND with 0.1µF capacitor
3
4
OUT
C
Analog Output
Capacitor
Analog Output
OUT
Capacitor for Optical Black Auto-Zero
Loop
C
5
MODE
Logic Input
Mode Control for Logic Input:
LO = Positive Pulse Active
HI = Negative Pulse Active
MODE
OB
16 AGC IN
15 GNDA
14 CCD R
13 CCD D
12 GNDA
11 VDDA
VSP2080T
6
OB
Logic Input
Logic Input
Logic Input
Logic Input
Logic Input
Optical Black Clamp Pulse
Sampling Pulse for Reset
Sampling Pulse for Data
Dummy Pixel Clamp Pulse
REFCK
DATCK
DUMC
7
REFCK
DATCK
DUMC
PD
8
9
10
Power-Down Control:
LO = Normal Operation
HI = Reduced Power
PD 10
11
12
13
14
15
16
17
18
19
20
VDDA
GNDA
CCD D
CCD R
GNDA
AGC IN
VDDA
Power Supply
Ground
Positive Power Supply
Analog Ground
Analog Input
Capacitor
CCD Signal Input
Capacitor for Dummy Feedback Loop
Analog Ground
ABSOLUTE MAXIMUM RATINGS
Ground
+VS ....................................................................................................... +6V
Analog Input .......................................................... –0.3V to (+VDDA +0.3V)
Logic Input ............................................................ –0.3V to (+VDDA +0.3V)
Case Temperature ......................................................................... +100°C
Junction Temperature .................................................................... +150°C
Storage Temperature ..................................................................... +150°C
Analog Input
Power Supply
Bypass
Sets Gain of Gain Control Amp.
Positive Power Supply
REFT
Bypass for Internal Top Reference
Bypass for Internal Bottom Reference
External Reference Input (1.0V)
REFB
REF IN
Bypass
Analog Input
PACKAGE/ORDERING INFORMATION
PACKAGE
DRAWING
NUMBER(1)
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
MARKING
ORDERING
NUMBER(2)
TRANSPORT
MEDIA
PRODUCT
PACKAGE
VSP2080T
"
20-Lead TSSOP
"
353
"
–25°C to +85°C
VSP2080T
"
VSP2080T
VSP2080T/2K
250-Piece Tray
Tape and Reel
"
NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are
available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP2080T/2K” will get a single 2000-
piece Tape and Reel.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
®
3
VSP2080
TIMING DIAGRAM
27MHz
Feedthrough Data Output Interval
CDS Input
(CCD Output)
N
N + 1
N + 2
t1
REFCK
(Pin 7)
t0
t3
DATCK
(Pin 8)
t2
t4
2.0V
ANALOG OUTPUT
(Pin 3)
1.03V
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
t0
t1
t2
t3
t4
REFCK Pulse Width
REFCK Sampling Delay
DATCK Pulse Width
11
1.5
11
14
2
ns
ns
ns
ns
ns
14
2
DATCK Sampling Delay
Analog Output Settling Time(1)
1.5
110
NOTE: (1) CLOAD = 5pF.
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VDD = +3.0V, and conversion rate = 18MHz, unless otherwise specified.
GAIN CONTROL CHARACTERISTICS
40
QUIESCENT CURRENT vs POWER SUPPLY
60
50
40
30
20
10
0
35
30
25
20
15
10
5
0
–5
–10
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.7
3.0
3.3
AGCIN Input (V)
Power Supply Voltage (V)
®
4
VSP2080
CORRELATED DOUBLE SAMPLER (CDS)
THEORY OF OPERATION
The CDS removes low frequency noise from the output of
the image sensor. Refer to Figure 2 which shows a block
diagram of the CDS. The output from the CCD array is
sampled during the reference interval as well as during the
data interval. Noise that is present at the input and is of a
period greater than the pixel interval will be eliminated by
subtraction.
The VSP2080 contains all of the key features associated with
the processing of analog signals in a CCD video camera or
digital still camera. Figure 1 shows a simplified block
diagram of the VSP2080. The output from the CCD array is
first clamped to an internal reference of +1V. This sets the
proper signal range for the input of the Correlated Double
Sampler (CDS). The CDS operates at at gain of 2 and
provides a differential output. Its output drives a voltage-
controlled attenuator with a logarithmic control characteris-
tic. An output amplifier drives this signal to external cir-
cuitry and sets the proper black level for the ADS900 A/D
converter.
The VSP2080 employs a three track-and-hold correlated
double sampler architecture. Track/Hold 2 samples the CCD
noise during the reference interval as driven by the REFCK
signal. Track/Hold 3 resamples this level at the same time
that Track/Hold 1 samples the video information as driven
by the DATCK signal. This is done to remove large tran-
sients from Track/Hold 2 that result from a portion of the
reset transient being present during the acquisition time of
this track-and-hold. The output of Track/Hold 2 is buffered
by a voltage follower.
Dummy
Feedback
Black Level
Auto-Zero
Loop
Loop
DUMC
OB
CCD D
Analog
Output
CCD
OUT
CDS
VCA
CEXT
Output
Amplifier
Clamp
REFCK DATCK
Gain Control
FIGURE 1. Simplified Block Diagram of VSP2080.
T/H1
CCD D
Data Sampling Channel
CCD
OUT
To VCA
CEXT
Reference Sampling
Channel
T/H3
T/H2
1V
DUMC REFCK
DATCK
FIGURE 2. Simplified Block Diagram of Correlated Double Sampler.
®
5
VSP2080
DIFFERENCE AMPLIFIER
be considered as the loop operates in a sampled mode. Opera-
tion of the dummy auto-zero loop is activated by the DUMC
signal that happens once during each horizontal line interval.
The correlated double sampler function is completed when
the output of the data and reference channel are sent to the
difference amplifier where the signals are subtracted. In
addition to providing the difference function, the difference
amplifier amplifies the signal by a factor of 2 which helps
to improve the overall signal-to-noise ratio. The difference
amplifier also generates a differential signal to drive the
voltage-controlled attenuator.
TIMING
The REFCK and DATCK signals are used to operate the
CDS as previously explained. The input digital timing sig-
nals REFCK, DATCK, DUMC and OB are capable of being
driven from either 3V or 5V logic levels.
INPUT CLAMP
VOLTAGE-CONTROLLED ATTENUATOR
The output from the CCD array is capacitively coupled to the
VSP2080. To prevent shifts in the DC level from taking place
due to varying input duty cycles, the input capacitor is
clamped during the dummy pixel interval by the REFCK
signal. A P-channel transistor is used for this input clamp
switch to be able to allow a 2V negative change at the input
that would bring the signal below ground by 1V. Under
typical conditions, the black level at the input to the VSP2080
is at 1V.
To maximize the dynamic range of the VSP2080, a voltage-
controlled attenuator is included with a control range from
0dB to –34dB. The gain control has a logarithmic relation-
ship between the control voltage and the attenuation. The
attenuator processes a differential signal from the difference
amplifier to improve linearity and to reject both power supply
and common-mode noise. The output from the attenuator is
amplified by 28dB prior to being applied to theA/D.Atypical
gain control characteristic of the VSP2080 is shown in the
typical performance curve, “Gain Control Characteristics”.
DUMMY PIXEL AUTO-ZERO LOOP
The output from the data and reference channel is processed
by the previously mentioned difference amplifier. The dif-
ferential output from the difference amplifier is sent to both
the voltage-controlled logarithmic attenuator and to an error
amplifier. The error amplifier amplifies and feeds a signal to
the difference amplifier to drive the offset measured at the
output of the difference amplifier to zero. A block diagram
of this circuit is shown in Figure 3. This error amplifier
serves the purpose of reducing the offset of the CDS to avoid
a large offset from being amplified by the output amplifier.
The effective time constant of this loop is given by:
BLACK LEVEL AUTO-ZERO LOOP
The black level auto-zero loop amplifies the difference
between the output of the output amplifier and a reference
signal during the dummy pixel interval. This difference
signal is amplified and fed back into the output amplifier to
correct the offset. In doing so, the output level of the entire
CCD channel can be controlled to be approximately –FS +
31mV under zero signal conditions. The black level auto-
zero loop is activated by the OB timing signal. Figure 4
shows a block diagram of the black level auto-zero loop. The
loop time constant is given by:
R • C
T =
C
T =
A • D
GM • D
where R is 10kΩ, C is an external capacitor connected to
CCD R (pin 14), A is the gain of the error amplifier with a
value of 50, and D is the duty cycle of the time that the dummy
pixel auto-zero loop is in operation. The duty cycle (D) must
where C is the external filter capacitance applied to C (pin 4),
GM is .001 Siemens (inverse ohm) and D is the duty cycle
of the time that the black level auto-zero loop is in operation.
The duty cycle (D) must be considered as the loop operates
in a sampled mode. Operation of the black level auto-zero
loop is activated by the OB signal that happens once during
each horizontal line interval.
To VCA
CCD D
CDS
Output Amplifier
From
VCA
OUT
1.03 • REF IN
A
Error
Amplifier
GM
Error
R
CCD R
Amplifier
C
CEXT
CEXT
DUMC
OB
FIGURE 3. Simplified Block Diagram of Dummy Pixel
FIGURE 4. Simplified Block Diagram of Optical Black
Level Auto-Zero Loop.
Loop.
®
6
VSP2080
DECOUPLING AND GROUNDING
CONSIDERATIONS
proximity to the individual pin. Therefore, they should be
located as close as possible to the pins. In addition, one
larger capacitor (1µF to 22µF) should be connected from
VDDA to ground and placed on the PC board in proximity of
the VSP2080.
Figure 5 shows the recommended decoupling scheme for
the VSP2080. In most cases, 0.1µF ceramic chip capacitors
are adequate to keep the impedance low over a wide fre-
quency range. Their effectiveness largely depends on the
0.047µF
CCD Output
VSP2080
0.1µF
0.1µF
0.1µF
1
2
3
4
5
6
7
8
9
LCM
REF IN 20
0.1µF
2.4V
REFB 19
VDDA
0.1µF
OUT
REFT 18
VDDA 17
0.1µF
C
0.1µF
MODE
OB
AGC IN 16
GNDA 15
CCD R 14
CCD D 13
GNDA 12
VDDA 11
0.1µF
REFCK
DATCK
DUMC
DSP
0.1µF
10 PD
0.1µF
Analog
Input
ADS900
Reference Out (1.0V)
A/D Converter
FIGURE 5. VSP2080 Typical Application and Bypassing Requirements.
®
7
VSP2080
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
VSP2080T
OBSOLETE ZZ (BB)
OBSOLETE ZZ (BB)
ZZ353
20
20
TBD
TBD
Call TI
Call TI
Call TI
Call TI
VSP2080T/2K
ZZ353
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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