TVP5158IPNPR [TI]
With Independent Scalers, Noise Reduction, Auto Contrast, and Flexible Output Formatter for Security and Other Multi-Channel Video Applications; 具有独立定标器，降噪，自动对比度，以及安全等多通道视频应用灵活的输出格式
| 型号： | TVP5158IPNPR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | With Independent Scalers, Noise Reduction, Auto Contrast, and Flexible Output Formatter for Security and Other Multi-Channel Video Applications |
| 文件： | 总111页 (文件大小：1553K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVP5158, TVP5157, TVP5156
Four-Channel NTSC/PAL Video Decoders
With Independent Scalers, Noise Reduction, Auto
Contrast, and Flexible Output Formatter for Security and
Other Multi-Channel Video Applications
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES243F
July 2009–Revised July 2011
TVP5158, TVP5157, TVP5156
SLES243F–JULY 2009–REVISED JULY 2011
www.ti.com
Contents
1
Introduction ........................................................................................................................ 9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
Features ...................................................................................................................... 9
Applications .................................................................................................................. 9
Description ................................................................................................................. 10
Related Products .......................................................................................................... 10
Trademarks ................................................................................................................. 10
Document Conventions ................................................................................................... 11
Ordering Information ...................................................................................................... 11
Functional Block Diagram ................................................................................................ 12
2
3
Terminal Assignments ....................................................................................................... 13
Pinout ....................................................................................................................... 13
Functional Description ....................................................................................................... 16
2.1
3.1
Analog Video Processing and A/D Converters ........................................................................ 16
3.1.1
3.1.2
3.1.3
Analog Video Input ............................................................................................. 16
Analog Video Input Clamping ................................................................................. 17
A/D Converter ................................................................................................... 17
3.2
Digital Video Processing .................................................................................................. 17
3.2.1
2x Decimation Filter ............................................................................................ 17
3.2.2
3.2.3
Automatic Gain Control ........................................................................................ 17
Composite Processor .......................................................................................... 17
3.2.3.1 Color Low-Pass Filter .............................................................................. 18
3.2.3.2 Y/C Separation ..................................................................................... 19
Luminance Processing ......................................................................................... 20
3.2.4
3.3
3.4
3.5
3.6
AVID Cropping ............................................................................................................. 21
Embedded Syncs .......................................................................................................... 21
Scaler ....................................................................................................................... 22
Noise Reduction ........................................................................................................... 22
3.7
3.8
Auto Contrast .............................................................................................................. 22
Output Formatter .......................................................................................................... 23
3.8.1
Non-Interleaved Mode ......................................................................................... 23
Pixel-Interleaved Mode ......................................................................................... 23
3.8.2
3.8.2.1 2-Ch Pixel-Interleaved Mode ..................................................................... 24
3.8.2.2 4-Ch Pixel-Interleaved Mode ..................................................................... 24
3.8.2.3
Metadata Insertion for Non-Interleave Mode and Pixel-Interleaved Mode ................. 25
3.8.3
Line-Interleaved Mode Support (TVP5158 only) ........................................................... 26
3.8.3.1 2-Ch Line-Interleaved Mode ...................................................................... 26
3.8.3.2 4-Ch Line-Interleaved Mode ...................................................................... 27
3.8.3.3 8-Ch Line-Interleaved Mode ...................................................................... 27
3.8.3.4 Hybrid Modes ....................................................................................... 29
3.8.3.5 Metadata Insertion for Line-Interleaved Mode ................................................. 29
3.9
Audio Sub-System (TVP5157 and TVP5158 Only) ................................................................... 32
3.9.1
3.9.2
3.9.3
3.9.4
Features ......................................................................................................... 33
Audio Sub-System Functional Diagram ..................................................................... 34
Serial Audio Interface .......................................................................................... 34
Analog Audio Input Clamping ................................................................................. 35
2
Contents
Copyright © 2009–2011, Texas Instruments Incorporated
TVP5158, TVP5157, TVP5156
www.ti.com
SLES243F–JULY 2009–REVISED JULY 2011
3.9.5
Audio Cascade Connection ................................................................................... 36
3.10 I2C Host Interface .......................................................................................................... 38
3.10.1 I2C Write Operation ............................................................................................. 39
3.10.2 I2C Read Operation ............................................................................................ 39
3.10.3 VBUS Access ................................................................................................... 41
3.11 Clock Circuits .............................................................................................................. 42
3.12 Reset Mode ................................................................................................................ 43
4
5
Internal Control Registers ................................................................................................... 44
4.1
Overview .................................................................................................................... 44
Register Definitions ........................................................................................................ 47
4.2
Electrical Specifications ..................................................................................................... 92
5.1
5.2
5.3
5.4
5.5
5.6
Absolute Maximum Ratings .............................................................................................. 92
Recommended Operating Conditions .................................................................................. 93
Reference Clock Specifications .......................................................................................... 93
Electrical Characteristics ................................................................................................. 94
DC Electrical Characteristics ............................................................................................. 94
Video A/D Converters Electrical Characteristics ...................................................................... 95
5.7
5.8
Audio A/D Converters Electrical Characteristics ...................................................................... 95
Video Output Clock and Data Timing ................................................................................... 96
5.8.1
Video Input Clock and Data Timing .......................................................................... 96
I2C Host Port Timing ...................................................................................................... 97
I2S Port Timing .................................................................................................. 98
5.9
5.9.1
5.10 Miscellaneous Timings .................................................................................................... 98
5.11 Power Dissipation Ratings ............................................................................................... 98
Application Information ...................................................................................................... 99
6
6.1
6.2
6.3
6.4
6.5
4-Ch D1 Applications ..................................................................................................... 99
8-Ch CIF Applications ..................................................................................................... 99
16-Ch CIF Applications .................................................................................................. 100
Application Circuit Examples ........................................................................................... 101
Designing with PowerPAD™ Devices ................................................................................. 102
Revison History ........................................................................................................................ 103
Copyright © 2009–2011, Texas Instruments Incorporated
Contents
3
TVP5158, TVP5157, TVP5156
SLES243F–JULY 2009–REVISED JULY 2011
www.ti.com
List of Figures
1-1
Functional Block Diagram ....................................................................................................... 12
Video Analog Processing and ADC Block Diagram ......................................................................... 16
Anti-Aliasing Filter Frequency Response ..................................................................................... 17
Composite Processor Block Diagram.......................................................................................... 18
Color Low-Pass Filter Frequency Response ................................................................................. 19
Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling................................. 19
Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling .............................................. 20
Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling ................................................ 20
Luminance Edge-Enhancer Peaking Block Diagram ........................................................................ 21
Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling ............................................................ 21
2-Ch Pixel-Interleaved Mode Timing Diagram................................................................................ 24
4-Ch Pixel-Interleaved Mode Timing Diagram................................................................................ 25
Cascade Connection for 16-Ch CIF Recoding and Multi-Ch CIF Preview ............................................... 28
Cascade Connection for 16-Ch CIF Recoding and Multi-Ch Half-D1 Preview........................................... 29
Cascade Connection for 16-Ch CIF Recoding and 2-Ch D1/Multi-Ch CIF Preview..................................... 29
Start Code in 8-Bit BT.656 Interface........................................................................................... 30
Start Code in 16-Bit YCbCr 4:2:2 Interface ................................................................................... 31
Audio Sub-System Functional Diagram ....................................................................................... 34
Serial Audio Interface Timing Diagram ........................................................................................ 35
Audio Cascade Connection ..................................................................................................... 36
VBUS Access ..................................................................................................................... 41
Clock and Crystal Connectivity ................................................................................................. 42
Reset Timing...................................................................................................................... 43
Video Output Clock and Data Timing.......................................................................................... 96
I2C Host Port Timing ............................................................................................................. 97
4-Ch D1 Application (Single BT.656 Interface)............................................................................... 99
4-Ch D1 Application (16-Bit YCbCr 4:2:2 Interface) ......................................................................... 99
8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application ................................................... 100
8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application ................................................... 100
Video Input Connectivity ....................................................................................................... 102
Audio Input Connectivity ....................................................................................................... 102
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
5-1
5-2
6-1
6-2
6-3
6-4
6-5
6-6
4
List of Figures
Copyright © 2009–2011, Texas Instruments Incorporated
TVP5158, TVP5157, TVP5156
www.ti.com
SLES243F–JULY 2009–REVISED JULY 2011
List of Tables
1-1
Device Options ................................................................................................................... 10
Terminal Functions .............................................................................................................. 14
EAV and SAV Sequence........................................................................................................ 21
Standard Video Resolutions .................................................................................................... 22
Video Resolutions Converted by the Scaler .................................................................................. 22
Summary of Line Frequencies, Data Rates and Pixel Counts for Different Standards ................................. 23
Output Ports Configuration for Non-Interleaved Mode ...................................................................... 23
Output Ports Configuration for Pixel-Interleaved Mode ..................................................................... 24
VDET Statues Insertion in SAV/EAV Codes.................................................................................. 25
Channel ID Insertion in Horizontal Blanking Code........................................................................... 25
Channel ID Insertion in SAV/EAV Code Sequence.......................................................................... 25
Output Ports Configuration for Line-Interleaved Mode ...................................................................... 26
Default Super-Frame Format and Timing ..................................................................................... 30
Bit Assignment of 4-Byte Start Code for Active Video Line................................................................. 31
Bit Field Definition of 4-Byte Start Code for Active Video Line............................................................. 31
Bit Assignment of 4-Byte Start Code for the Dummy Line.................................................................. 32
Serial Audio Output Channel Assignment..................................................................................... 37
I2C Terminal Description ........................................................................................................ 38
I2C Host Interface Device Addresses.......................................................................................... 38
Reset Mode ....................................................................................................................... 43
Reset Sequence.................................................................................................................. 43
Registers Summary .............................................................................................................. 44
Status 1 ........................................................................................................................... 47
Status 2 ........................................................................................................................... 48
Color Subcarrier Phase Status ................................................................................................ 48
ROM Version ..................................................................................................................... 48
RAM Version MSB .............................................................................................................. 49
RAM Version LSB ............................................................................................................... 49
Chip ID MSB ..................................................................................................................... 49
Chip ID LSB ...................................................................................................................... 49
Video Standard Status .......................................................................................................... 50
Video Standard Select .......................................................................................................... 50
CVBS Autoswitch Mask ......................................................................................................... 51
Auto Contrast Mode ............................................................................................................. 51
Luminance Brightness .......................................................................................................... 51
Luminance Contrast ............................................................................................................. 52
Brightness and Contrast Range Extender .................................................................................... 52
Chrominance Saturation ........................................................................................................ 52
Chrominance Hue ............................................................................................................... 53
Color Killer ........................................................................................................................ 53
Luminance Processing Control 1 .............................................................................................. 54
Luminance Processing Control 2 .............................................................................................. 54
Power Control .................................................................................................................... 55
Chrominance Processing Control 1 ........................................................................................... 56
Chrominance Processing Control 2 ........................................................................................... 56
AGC Gain Status ................................................................................................................ 57
Back-End AGC Status .......................................................................................................... 57
2-1
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10
4-11
4-12
4-13
4-14
4-15
4-16
4-17
4-18
4-19
4-20
4-21
4-22
4-23
4-24
4-25
4-26
Copyright © 2009–2011, Texas Instruments Incorporated
List of Tables
5
TVP5158, TVP5157, TVP5156
SLES243F–JULY 2009–REVISED JULY 2011
www.ti.com
4-27
4-28
4-29
4-30
4-31
4-32
4-33
4-34
4-35
4-36
4-37
4-38
4-39
4-40
4-41
4-42
4-43
4-44
4-45
4-46
4-47
4-48
4-49
4-50
4-51
4-52
4-53
4-54
4-55
4-56
4-57
4-58
4-59
4-60
4-61
4-62
4-63
4-64
4-65
4-66
4-67
4-68
4-69
4-70
4-71
4-72
4-73
4-74
Status Request .................................................................................................................. 57
AFE Gain Control ................................................................................................................ 57
Luma ALC Freeze Upper Threshold .......................................................................................... 58
Chroma ALC Freeze Upper Threshold ....................................................................................... 58
AGC Increment Speed .......................................................................................................... 58
AGC Increment Delay ........................................................................................................... 58
AGC Decrement Speed ......................................................................................................... 59
AGC Decrement Delay ......................................................................................................... 59
AGC White Peak Processing .................................................................................................. 60
Back-End AGC Control ......................................................................................................... 61
AFE Fine Gain ................................................................................................................... 61
AVID Start Pixel .................................................................................................................. 62
AVID Pixel Width ................................................................................................................ 62
Noise Reduction Max Noise .................................................................................................... 62
Noise Reduction Control ........................................................................................................ 63
Noise Reduction Noise Filter Beta ............................................................................................ 63
Operation Mode Control ........................................................................................................ 64
Color PLL Speed Control ....................................................................................................... 64
Sync Height Low Threshold .................................................................................................... 65
Sync Height High Threshold ................................................................................................... 65
Clear Lost Lock Detect .......................................................................................................... 65
VSYNC Filter Shift ............................................................................................................... 65
656 Version/F-bit Control ....................................................................................................... 66
F-Bit and V-Bit Decode Control ................................................................................................ 67
F-Bit and V-Bit Control .......................................................................................................... 68
Output Timing Delay ............................................................................................................ 68
Auto Contrast User Table Index ............................................................................................... 69
Blue Screen Y Control .......................................................................................................... 69
Blue Screen Cb Control ........................................................................................................ 69
Blue Screen Cr Control ......................................................................................................... 70
Blue Screen LSB Control ....................................................................................................... 70
Noise Measurement ............................................................................................................. 70
Weak Signal High Threshold ................................................................................................... 70
Weak Signal Low Threshold ................................................................................................... 70
Noise Reduction Y/U/V T0 ..................................................................................................... 71
Vertical Line Count Status ...................................................................................................... 71
Output Formatter Control 1 ..................................................................................................... 71
Output Formatter Control 2 ..................................................................................................... 72
Interrupt Control ................................................................................................................. 72
Embedded Sync Offset Control 1 ............................................................................................. 72
Embedded Sync Offset Control 2 ............................................................................................. 73
AVD Output Control 1 ........................................................................................................... 74
AVD Output Control 2 ........................................................................................................... 75
OFM Mode Control .............................................................................................................. 76
OFM Channel Select 1 .......................................................................................................... 77
OFM Channel Select 2 .......................................................................................................... 78
OFM Channel Select 3 .......................................................................................................... 78
OFM Super-Frame Size ........................................................................................................ 79
6
List of Tables
Copyright © 2009–2011, Texas Instruments Incorporated
TVP5158, TVP5157, TVP5156
www.ti.com
SLES243F–JULY 2009–REVISED JULY 2011
4-75
4-76
4-77
4-78
4-79
4-80
4-81
4-82
4-83
4-84
4-85
4-86
4-87
4-88
4-89
4-90
4-91
4-92
4-93
4-94
4-95
OFM EAV2SAV Duration ....................................................................................................... 79
Misc OFM Control ............................................................................................................... 80
Audio Sample Rate Control .................................................................................................... 80
Analog Audio Gain Control 1 ................................................................................................... 81
Analog Audio Gain Control 2 ................................................................................................... 82
Audio Mode Control ............................................................................................................. 83
Audio Mixer Select .............................................................................................................. 84
Audio Mute Control .............................................................................................................. 85
Analog Mixing Ratio Control 1 ................................................................................................. 85
Analog Mixing Ratio Control 2 ................................................................................................. 86
Audio Cascade Mode Control .................................................................................................. 86
Super-Frame EAV2SAV Duration Status ..................................................................................... 86
Super-Frame SAV2EAV Duration Status ..................................................................................... 87
VBUS Data Access With No VBUS Address Increment ................................................................... 87
VBUS Data Access With VBUS Address Increment ........................................................................ 87
VBUS Address Access ......................................................................................................... 87
Interrupt Status .................................................................................................................. 88
Interrupt Mask .................................................................................................................... 89
Interrupt Clear .................................................................................................................... 90
Decoder Write Enable .......................................................................................................... 90
Decoder Read Enable .......................................................................................................... 91
Copyright © 2009–2011, Texas Instruments Incorporated
List of Tables
7
TVP5158, TVP5157, TVP5156
SLES243F–JULY 2009–REVISED JULY 2011
www.ti.com
8
List of Tables
Copyright © 2009–2011, Texas Instruments Incorporated
TVP5158, TVP5157, TVP5156
www.ti.com
SLES243F–JULY 2009–REVISED JULY 2011
Four-Channel NTSC/PAL Video Decoders
Check for Samples: TVP5158, TVP5157, TVP5156
1
Introduction
1.1 Features
1234
– Support crystal interface with on-chip
• Common Device Features
oscillator and single clock input mode
(TVP5156, TVP5157, TVP5158)
– Single 27-MHz clock input or crystal for all
– Four separate video decoder channels
having the following features for each
channel
standards and all channels
– Internal phase-locked loop (PLL) for
line-locked clock (separate for each channel)
and sampling
•
Accepts NTSC (J, M, 4.43) and PAL (B, D,
G, H, I, M, N, Nc, 60) video data
– Standard programmable video output format
•
Composite video inputs,
Pseudo-differential video inputs to
improved noise immunity
•
ITU-R BT.656, 8-bit 4:2:2 with embedded
syncs
•
•
High-speed 10-bit ADC
Fully differential CMOS analog
preprocessing channels with clamping
•
YCbCr 16-bit 4:2:2 with embedded syncs
– Macrovision™ copy protection detection
– 3.3-V compatible I/O
•
•
•
•
Integrated Anti-Aliasing filter
2D 5-line (5H) adaptive comb filter
Noise reduction and auto contrast
Robust automatic video standard
detection (NTSC/PAL) and switching
– 128-pin TQFP package
– Available in commercial (0°C to 70°C)
temperature range
• Additional TVP5158/TVP5157 Specific Features
– Integrated four-channel audio ADC with
•
Programmable hue, saturation,
sharpness, brightness and contrast
Luma-peaking processing
Patented architecture for locking to weak,
noisy, or unstable signals
audio sample rate of 8 kHz or 16 kHz
– Support Master and Slave mode I2S Output
– Support audio cascade connection
•
•
• Additional TVP5158 Specific Features
– Enhanced channel multiplexing capability –
Line-interleaved mode
– Four-channel D1 multiplexed output at 8 bit
– Four independent scalers support horizontal
and/or vertical 2:1 downscaling
– Channel multiplexing capabilities with
at 108 MHz
metadata insertion
•
– Video cascade connection for 8-Ch CIF, 8-Ch
Half-D1, and 8-Ch CIF + 1-Ch D1 outputs
– Also available in Industrial (-40°C to 85°C)
Pixel-interleaved mode supports up to
four-channel D1 multiplexed 8-bit output
at 108 MHz
Supports concurrent NTSC and PAL
inputs
temperature range
•
• Qualified for Automotive Applications
(AEC-Q100 Rev G – TVP5158IPNPQ1,
TVP5158IPNPRQ1)
1.2 Applications
•
•
•
•
Security/surveillance digital video recorders/servers and PCI products
Automotive infotainment video hub
Large format video wall displays
Game systems
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
DaVinci is a trademark of Texas Instruments.
Macrovision is a trademark of Macrovision Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2011, Texas Instruments Incorporated
TVP5158, TVP5157, TVP5156
SLES243F–JULY 2009–REVISED JULY 2011
www.ti.com
1.3 Description
The TVP5158, TVP5157, and TVP5156 devices are 4-channel high-quality NTSC/PAL video decoders
that digitize and decode all popular base-band analog video formats into digital video output. Each
channel of this decoder includes 10-bit 27-MSPS A/D converter (ADC). Preceding each ADC in the
device, the corresponding analog channel contains an analog circuit that clamps the input to a reference
voltage and applies the gain.
Composite input signal is sampled at 2x the ITU-R BT.601 clock frequency, line-locked alignment, and is
then decimated to the 1x pixel rate. CVBS decoding uses five-line adaptive comb filtering for both the
luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts. A chroma trap filter is
also available. On CVBS inputs, the user can control video characteristics such as contrast, brightness,
saturation, and hue via an I2C host port interface. Furthermore, luma peaking (sharpness) with
programmable gain is included.
All 4 channels are independently controllable. These decoders share a single clock input for all channels
and for all supported standards.
TVP5158 provides a glueless audio and video interface to TI DaVinci™ video processors. Video output
ports support 8-bit ITU-R BT.656 and 16-bit 4:2:2 YCbCr with embedded synchronization. TVP5158
supports multiplexed pixel-interleaved and line-interleaved mode video outputs with metadata insertion.
TVP5158 and TVP5157 integrate 4-Ch audio ADCs to reduce the BOM cost for surveillance market.
Multiple TVP5158 devices can be cascade connected to support up to 8-Ch Video or 16-Ch audio
processing.
Noise reduction and auto contrast functions improve the video quality under low light condition which is
very critical for surveillance products.
The TVP5158, TVP5157, and TVP5156 can be programmed by using a single I2C serial interface. I2C
commands can be sent to one or more decoder cores simultaneously, reducing the amount of I2C activity
necessary to configure each core. This is especially useful for fast downloading modified firmware to the
decoder cores.
TVP5158, TVP5157, and TVP5156 use 1.1-V, 1.8-V, and 3.3-V power supplies for the analog/digital core
and I/O. These devices are available in a 128-pin TQFP package.
Table 1-1. Device Options
Device Name
TVP5156
4-Ch Audio ADC
Line-Interleaved Modes
No
No
No
TVP5157
Yes
Yes
TVP5158
Yes
1.4 Related Products
•
•
•
•
TVP5154A
TVP5150AM1
TVP5146M2
TVP5147M1
1.5 Trademarks
DaVinci, PowerPAD are trademarks of Texas Instruments.
Macrovision is a trademark of Macrovision Corporation.
Other trademarks are the property of their respective owners.
10
Introduction
Copyright © 2009–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TVP5158 TVP5157 TVP5156
TVP5158, TVP5157, TVP5156
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SLES243F–JULY 2009–REVISED JULY 2011
1.6 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are
as follows:
•
•
•
•
•
To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit
binary field.
To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a
12-bit hexadecimal field.
All other numbers that appear in this document that do not have either a b or h following the number
are assumed to be decimal format.
If the signal or terminal name has a bar above the name (for example, RESETB), then this indicates
the logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
RSVD indicates that the referenced item is reserved.
1.7 Ordering Information
PACKAGED DEVICES(1) (2)
TA
PACKAGE OPTION
TQFP 128-Pin PowerPADTM Package
TVP5156PNP
TVP5156PNPR
TVP5157PNP
Tray
Tape and reel
Tray
0°C to 70°C
TVP5157PNPR
TVP5158PNP
Tape and reel
Tray
TVP5158PNPR
TVP5158IPNP
Tape and reel
Tray
TVP5158IPNPR
TVP5158IPNPQ1(3)
TVP5158IPNPRQ1(3)
Tape and reel
Tray
-40°C to 85°C
Tape and reel
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) AEC-Q100 Rev G certified
Copyright © 2009–2011, Texas Instruments Incorporated
Introduction
11
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TVP5158, TVP5157, TVP5156
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www.ti.com
1.8 Functional Block Diagram
VIN_1_P
10-Bit
ADC
Y/C
Separation
Noise Reduction/
Auto Contrast
DVO_A_[7:0]
Scaler
Scaler
Scaler
Scaler
VIN_1_N
VIN_2_P
VIN_2_N
Y/C
Separation
10-Bit
ADC
Noise Reduction/
Auto Contrast
DVO_B_[7:0]
Output
Formattor
VIN_3_P
VIN_3_N
Y/C
Separation
10-Bit
ADC
Noise Reduction/
Auto Contrast
DVO_C_[7:0]
VIN_4_P
VIN_4_N
Y/C
Separation
DVO_D_[7:0]
10-Bit
ADC
Noise Reduction/
Auto Contrast
ARM/Memory
Registers
Delay Match
and Re-Sync
I2C Host port
Cascade
Input
I2C
AIN_1
AIN_2
AIN_3
AIN_4
BCLK_R
LRCLK_R
Audio
ADC
Decimation Filter
and Mixer
I2S Encoder
SD_R/SD_M
SD_CO
Audio Cascade Input
Figure 1-1. Functional Block Diagram
12
Introduction
Copyright © 2009–2011, Texas Instruments Incorporated
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Product Folder Link(s): TVP5158 TVP5157 TVP5156
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2
Terminal Assignments
2.1 Pinout
128-PIN TQFP PACKAGE
(TOP VIEW)
VDD_1_1
DVO_B_0
DVO_B_1
VSS
97
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OSC_OUT
98
VSSA
XTAL_IN
99
XTAL_REF
XTAL_OUT
VDDA_1_8
VDDA_1_1
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
DVO_B_2
DVO_B_3
VDD_3_3
DVO_B_4
DVO_B_5
VSS
VSSA
VSSA
VDDA_1_1
DVO_B_6
DVO_B_7
VDD_1_1
OCLK_P
OCLK_N/CLKIN
VSS
VDDA_1_8
VIN_1_P
VIN_1_N
VSSA
VSSA
VIN_2_P
I2CA2
VIN_2_N
VDDA_1_8
VDDA_1_8
REXT_2K
VSS
DVO_C_0
DVO_C_1
VDD_1_1
DVO_C_2
DVO_C_3
VDD_3_3
DVO_C_4
DVO_C_5
VSS
VSSA
VSSA
VDDA_1_1
VDDA_1_8
VIN_3_P
VIN_3_N
VSSA
DVO_C_6
DVO_C_7
VDD_1_1
NC
VSSA
VIN_4_P
VIN_4_N
VDDA_1_8
VDAA_3_3
VSS
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Terminal Assignments
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Table 2-1. Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
Analog Section
VIN_1_P
VIN_1_N
VIN_2_P
VIN_2_N
VIN_3_P
VIN_3_N
VIN_4_P
VIN_4_N
REXT_2K
AIN_1
NO.
108
109
112
113
121
122
125
126
116
95
I
I
I
I
I
I
I
I
I
I
I
I
I
Analog video input for ADC channel 1.
Common-mode reference input for ADC channel 1.
Analog video input for ADC channel 2.
Common-mode reference input for ADC channel 2.
Analog video input for ADC channel 3.
Common-mode reference input for ADC channel 3.
Analog video input for ADC channel 4.
Common-mode reference input for ADC channels.
External resistor for AFE bias generator. Connect external 1.8kΩ resistor to ground.
Analog audio input for channel 1 (No Connect for TVP5156 Only)
Analog audio input for channel 2 (No Connect for TVP5156 Only)
Analog audio input for channel 3 (No Connect for TVP5156 Only)
Analog audio input for channel 4 (No Connect for TVP5156 Only)
AIN_2
94
AIN_3
93
AIN_4
92
External clock reference input. It may be connected to external oscillator with 1.8-V compatible
clock signal or 27.0-MHz crystal oscillator.
XTAL_IN
99
I
XTAL_REF
XTAL_OUT
100
101
G
O
Crystal reference. Connected to analog ground internally.
External clock reference output. Not connected if XTAL_IN is driven by an external
single-ended oscillator.
Analog Power
VDDA_1_1
103, 106, 119
P
P
P
1.1-V analog supply
91, 102, 107,
114, 115, 120,
127
VDDA_1_8
VDDA_3_3
1.8-V analog supply
128
3.3-V analog supply for all 4 video channels
96, 98, 104,
105, 110, 111,
117, 118, 123,
124
VSSA
G
Analog ground
Digital ground
Digital Power
1, 6, 12, 14, 20,
26, 33, 38, 47,
49, 55, 61, 65,
73, 79, 82, 87,
90
VSS
G
13, 18, 23, 32,
35, 44, 52, 64,
67, 76, 84
VDD_1_1
VDD_3_3
P
P
Digital core supply. Connect to 1.1-V digital supply.
Digital I/O supply. Connect to 3.3-V digital supply.
15, 29, 41, 58,
70, 81
Digital Section
INTREQ
RESETB
SCL
2
3
O
I
Interrupt request. Interrupt signal to host processor.
Reset. An active low signal that controls the reset state.
I2C serial clock (open drain)
4
I/O
I/O
O
SDA
5
I2C serial data (open drain)
OSC_OUT
OCLK_P
97
51
Buffered crystal oscillator output. 1.8-V compatible.
Output data clock+. All 4 digital video output ports are synchronized to this clock.
O
Output data clock- for 2-Ch time-multiplexed mode or data clock input for 8-Ch video cascade
mode
OCLK_N/CLKIN
DVO_A_[7:0]
50
I/O
O
68, 69, 71, 72,
74, 75, 77, 78
Digital video output data bus.
14
Terminal Assignments
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Table 2-1. Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
53, 54, 56, 57,
59, 60, 62, 63
DVO_B_[7:0]
O
Digital video output data bus.
36, 37, 39, 40,
42, 43, 45, 46
Digital video output data bus. In cascade mode, all pins operate as input from another
TVP5158 device.
DVO_C_[7:0]
DVO_D_[7:0]
I/O
I/O
21, 22, 24, 25,
27, 28, 30, 31
Digital video output data bus. In cascade mode, all pins operate as input from another
TVP5158 device.
I2CA0
I2CA1
I2CA2
80
66
48
I
I
I
I2C slave address bit 0
I2C slave address bit 1
I2C slave address bit 2
Digital Audio Section (Not supported on TVP5156)
I2S bit clock for recording. Also known as I2S serial clock (SCK). Supports master and slave
modes.
I2S left/right clock for recording. Also known as I2S word select (WS). Supports master and
slave modes.
BCLK_R
85
86
I/O
I/O
LRCLK_R
SD_R
88
89
83
16
17
19
O
O
O
I
I2S serial data output for recording.
I2S serial data output for mixed audio or recording.
SD_M
SD_CO
Audio serial data output for cascade mode
LRCLK_CI
BCLK_CI
SD_CI
I2S left/right clock input for cascade mode. Also known as I2S word select (WS).
I2S bit clock input for cascade mode. Also known as I2S serial clock (SCK).
Audio serial data input for cascade mode.
I
I
No Connect Pins
T1, T2, T3, T4,
T5, NC
7, 8, 9, 10, 11,
34
NC
For normal operation, no connect
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Terminal Assignments
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3
Functional Description
3.1 Analog Video Processing and A/D Converters
Each video decoder accepts one composite video input and performs video clamping, anti-aliasing
filtering, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video
signal. Figure 3-1 shows the video analog processing and ADC block diagram.
Output to
Digital
Processing
Analog
CVBS Input
Anti-Aliasing
Filter
ADC
Clamp
Reference & Bias
Figure 3-1. Video Analog Processing and ADC Block Diagram
3.1.1 Analog Video Input
Supports NTSC (J, M, 4.43) and PAL (B, D, G, H, I, M, N, Nc, 60) video standards. Each video decoder
channel supports a composite video input with a pseudo-differential pin which improves the noise
immunity and analog performance.
Each video decoder input should be ac-coupled through a 0.1-µF capacitor. The nominal parallel
termination resistor before the input to the device is 75 Ω.
Each video decoder integrates an anti-aliasing filter to provide good stop-band rejection on the analog
video input signal. Figure 3-2 shows the frequency response of the anti-aliasing filter.
Frequency Response
5
0
-5
-10
-15
-20
-25
-30
-35
-
5
10
15
20
25
Frequency (MHz)
Figure 3-2. Anti-Aliasing Filter Frequency Response
16
Functional Description
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3.1.2 Analog Video Input Clamping
An internal clamping circuit provides dc restoration for all four analog composite video inputs. The dc
restoration circuit (sync-tip clamp) restores sync-tip level of the ac-coupled composite video signal to a
fixed dc level near the bottom of the A/D converter range.
3.1.3 A/D Converter
All ADCs have a resolution of 10 bits and can operate at 27 MSPS. Each A/D channel receives a clock
from the on-chip phase-locked loop (PLL) at a nominal frequency of 27 MHz. All ADC reference voltages
are generated internally.
3.2 Digital Video Processing
Digital Video Processing block receives digitized video signals from the ADCs and performs composite
processing and YCbCr signal enhancements. The digital data output can be programmed to two formats:
ITU-R BT.656 8-bit 4:2:2 with embedded syncs or 16-bit 4:2:2 with embedded syncs. The circuit also
detects pseudo-sync pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected
material.
3.2.1 2x Decimation Filter
All input signals are over-sampled by a factor of 2 (by 27-MHz clock). The A/D outputs initially pass
through decimation filters that reduce the data rate to 1x the pixel rate. The decimation filter is a half-band
filter. Over-sampling and decimation filtering can effectively increase the overall signal-to-noise ratio by
3 dB.
3.2.2 Automatic Gain Control
The automatic gain control (AGC) can be enabled and can adjust the signal amplitude controlled by 14-bit
digital gain stage after the ADC. The AGC algorithms can use up to four amplitude references: sync
height, color burst amplitude, composite peak, and luma peak.
The specific amplitude references being used by the AGC algorithms can be controlled using the AGC
white peak processing register located at subaddress 2Dh. The gain increment speed and gain increment
delay can be controlled using the AGC increment speed register located at subaddress 29h and the AGC
increment delay register located at subaddress 2Ah. The gain decrement speed and gain decrement delay
can be controlled using the AGC decrement speed register located at subaddress 2Bh and the AGC
decrement delay register located at subaddress 2Ch.
3.2.3 Composite Processor
This Composite Processor circuit receives a digitized composite signal from the ADCs and performs sync
and Y/C separation, chroma demodulation for PAL/NTSC, and YUV signal enhancements. The slice levels
of the sync separator are adaptive. The slice levels continually adapt to changes in the back-porch and
sync-tip levels. The 10-bit composite video is multiplied by the sub carrier signals in the quadrature
demodulator to generate U and V color difference signals. The U and V signals are then sent to low-pass
filters to achieve the desired bandwidth. An adaptive 5-line comb filter separates UV from Y based on the
unique property of color phase shifts from line to line. The chroma is re-modulated through a quadrature
modulator and subtracted from line-delayed composite video to generate luma. This form of Y/C
separation is completely complementary, thus there is no loss of information. However, in some
applications, it is desirable to limit the U/V bandwidth to avoid crosstalk. In that case, notch filters can be
turned on. To accommodate some viewing preferences, a peaking filter is also available in the luma path.
Contrast, brightness, sharpness, hue, and saturation controls are programmable through the I2C host port.
Figure 3-3 shows the block diagram of Composite Processor.
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Functional Description
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Y
Delay
CVBS
Peaking
Line
Delay
NTSC/PAL
Remodulation
Y
Contrast
Brightness
Saturation
Cb
Cr
Notch
Filter
Notch
Filter
Adjust
Color LPF
2
Burst
Accumulator
(U)
5 Line
Adaptive
U
V
Notch
Filter
Comb Filter
Delay
Burst
Accumulator
(V)
NTSC/PAL
Demodulation
CVBS
Color LPF
2
Notch
Filter
Delay
Figure 3-3. Composite Processor Block Diagram
3.2.3.1 Color Low-Pass Filter
High filter bandwidth preserves sharp color transitions and produces crisp color boundaries. However, for
nonstandard video sources that have asymmetrical U and V side bands, it is desirable to limit the filter
bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the
three notch filters. Figure 3-4 and Figure 3-5 represent the frequency responses of the wideband color
low-pass filters.
18
Functional Description
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Figure 3-4. Color Low-Pass Filter Frequency Response
Figure 3-5. Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling
3.2.3.2 Y/C Separation
Y/C separation can be done using adaptive 5-line (5-H delay) comb filters or a chroma trap filter. The
comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the
luma path, then chroma trap filters are used which are shown in Figure 3-6 and Figure 3-7. The TI
patented adaptive comb filter algorithm reduces artifacts such as hanging dots at color boundaries. It
detects and properly handles false colors in high-frequency luminance images such as a multiburst pattern
or circle pattern.
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Functional Description
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Figure 3-6. Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling
Figure 3-7. Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling
3.2.4 Luminance Processing
The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter,
either of which removes chrominance information from the composite signal to generate a luminance
signal. The luminance signal is then fed into the input of a peaking circuit. Figure 3-8 shows the basic
functions of the luminance data path. A peaking filter (edge enhancer) amplifies high-frequency
components of the luminance signal. Figure 3-9 shows the characteristics of the peaking filter at four
different gain settings that are user-programmable via the I2C interface.
Gain
Peak
Bandpass
Filter
Peaking
Filter
IN
x
Detector
Delay
+
OUT
Figure 3-8. Luminance Edge-Enhancer Peaking Block Diagram
20
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Figure 3-9. Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling
3.3 AVID Cropping
AVID or active video cropping provides a means to decrease the amount of video data output. This is
accomplished by horizontally blanking a number of AVID pulses and by vertically blanking a number of
lines per frame. Horizontal cropping can be enabled/disabled using bit-6 of address B1h. When line
cropping is enabled, active video is reduced from 720 to 704 pixels for unscaled video and from 360 to
352 pixels for down-scaled video.
When line cropping is enabled, the TVP5158 crops an equal amount from both the start and end of active
video. Register 8Ch can be used to delay both the start and end of active video. It allows selecting which
704 pixels out of 720 are actually being used for active video when line cropping is enabled.
3.4 Embedded Syncs
Standards with embedded syncs insert SAV and EAV codes into the data stream at the beginning and end
of horizontal blanking. These codes contain the V and F bits which also define vertical timing. F and V
change on EAV. Table 3-1 gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line
and field counter varies depending on the standard. Please refer to ITU-R BT.656 for more information on
embedded syncs.
The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 3-1. EAV and SAV Sequence
8-BIT DATA
D7 (MSB)
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Preamble
Preamble
Preamble
Status word
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
V
H
P3
P2
P1
P0
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Functional Description
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3.5 Scaler
Each video decoder has an independent horizontal and vertical scaler, which supports D1 to half-D1 or
CIF conversion. Table 3-2 gives the details of video resolution including un-cropped and cropped.
Table 3-3 shows the video resolutions converted by the scaler.
Table 3-2. Standard Video Resolutions
Uncropped
Cropped
Format
NTSC
PAL
NTSC
PAL
D1
Half-D1
CIF
720 x 480
360 x 480
360 x 240
720 x 576
360 x 576
360 x 288
704 x 480
352 x 480
352 x 240
704 x 576
352 x 576
352 x 288
Table 3-3. Video Resolutions Converted by the Scaler
Active Output
Resolution
Scaling Ratio
Format
Horizontal Scaling
Vertical Scaling
Total Pixel
NTSC
PAL
1:1
1:1
2:1
2:1
2:1
2:1
1:1
1:1
1:1
1:1
2:1
2:1
858 x 525
864 x 625
429 x 525
432 x 625
429 x 262
432 x 312
720 x 480
720 x 576
360 x 480
360 x 576
360 x 240
360 x 288
D1
NTSC
PAL
D1 to Half-D1
D1 to CIF
NTSC
PAL
3.6 Noise Reduction
A video sequence shot under low light condition, which is typical of video surveillance applications, can
contain lots of noise. Human eyes are very sensitive to oscillating signals, the visual quality degenerates
significantly even when the noise level is small.
Each video decoder uses a TI proprietary spatial filter to reduce video noise. For each frame of image, the
video noise filter (VNF) produces an estimate of the Y/U/V noise. Based on the noise estimates, the
firmware adjusts the threshold for Y/U/V filtering. The filtered video shows improved video quality and
lower compression bit-rate. The firmware can also utilize the Y/U/V noise estimates to make decisions to
disable color if the video noise is determined to be too high. This "color killer" decision bit can be used to
control another module that implements the color killing function.
The Noise Reduction can be controlled using I2C registers from 50h to 5Fh. This module can also be set
to bypass mode by I2C register 5Dh (Bit 0).
3.7 Auto Contrast
The Auto Contrast (AC) module can adjust the picture brightness automatically or manually (user
programmable) for better image quality. The goal of AC processing is to make the dark area brighter and
high-light area dimmer. This makes it possible for the viewer to see details hidden in the shadows. It also
prevents loss of details in the washed-out high light area. The AC processing is mostly for video
surveillance applications.
For each frame of image, the auto contrast module collects the statistics of its Y (luminance) values. The
AC algorithm implemented in the firmware processes the statistics and generates a look-up table (LUT).
This LUT is used to map each incoming pixel Y value to an output pixel Y value for the next frame of
image. The LUT is updated during the blanking period between two frames.
The Auto Contrast Mode can be controlled by using I2C registers 0Fh. This module can also be set to
disable mode by I2C register 0Fh (Bit 1:0).
22
Functional Description
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3.8 Output Formatter
The output formatter is responsible for generating the output digital video stream. Table 3-4 provides a
summary of line frequencies, data rates, and pixel counts for different input standards. TVP5158 supports
non-interleaved output mode, pixel-interleaved output mode and line-interleaved output mode. The
non-interleaved mode is similar to the TVP5154A device, except that a single fixed clock output is used. In
the interleaved modes, the video output data from multiple decoder channels are multiplexed together and
then output to a single 8-bit or 16-bit port. The video output data from selected channels can be
interleaved on a pixel or line basis.
Table 3-4. Summary of Line Frequencies, Data Rates and Pixel Counts for Different Standards
Pixel
Frequency
(MHz)
Color Subcarrier
Frequency
(MHz)
Horizontal Line
Rate
Standards
(ITU-R BT.601)
Active Pixels
per Line
Lines per
Frame
Pixels per Line
(kHz)
NTSC-J, M
NTSC-4.43
PAL-M
858
858
858
858
864
864
864
720
720
720
720
720
720
720
525
525
525
525
625
625
625
13.5
13.5
13.5
13.5
13.5
13.5
13.5
3.579545
15.73426
15.73426
15.73426
15.73426
15.625
4.43361875
3.57561149
4.43361875
4.43361875
4.43361875
3.58205625
PAL-60
PAL-B, D, G, H, I
PAL-N
15.625
PAL-Nc
15.625
3.8.1 Non-Interleaved Mode
In the non-interleaved mode, the YCbCr digital output is programmed as 8-bit ITU-R BT.656 parallel
interface standard. Depending on which output mode is selected, the output for each channel can be
un-scaled data or scaled data. Also each video output port can be selected to output the video data from
any 1 of 4 video decoders. Table 3-5 shows the detailed information about non-interleaved mode.
Table 3-5. Output Ports Configuration for Non-Interleaved Mode
Video Output
Format
Cascade
Stage
I2C Address:
B0h
OCLK
(MHz)
Port A
Port B
Port C
Port D
1-Ch D1
1-Ch Half-D1
1-Ch CIF
n/a
n/a
n/a
00h
02h
03h
27
27
27
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
Any 1 of 4 Ch
3.8.2 Pixel-Interleaved Mode
Each video decoder supports multiplexing two or four channels ITU-R BT.656 format data together on a
pixel basis. The output from each video decoder channel is still ITU-R BT.656 format. After the processing
in output formatter, two or four channels video data has been interleaved together by strictly one pixel
from each channel.
The pixel-interleaved mode is dedicated for the backend chip which has limited video input ports.
Table 3-6 gives the output port configuration for pixel-interleaved mode.
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Functional Description
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Port D
Table 3-6. Output Ports Configuration for Pixel-Interleaved Mode
Video Output
Format
Cascade
Stage
I2C Address:
B0h
OCLK
(MHz)
Port A
Port B
Port C
2-Ch D1
4-Ch D1
n/a
n/a
n/a
n/a
50h
60h
62h
63h
54
108
54
Any 2 of 4 Ch
All 4 Ch
Any 2 of 4 Ch
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
4-Ch Half-D1
4-Ch CIF
All 4 Ch
Hi-Z
54
All 4 Ch
Hi-Z
3.8.2.1 2-Ch Pixel-Interleaved Mode
In 2-Ch pixel-interleaved mode, the video output data with D1 resolution from two video channels is
multiplexed pixel by pixel at 54 MHz. The output ports DVO_A and DVO_B are used in this mode. The
output clocks OCLK_P and OCLK_N are synchronized with each channel so that the backend chip can
de-multiplexed each video channel data easily. The video output from each channel is compatible with
ITU-R BT.656 format. Figure 3-10 shows the timing diagram for 2-Ch pixel-interleaved mode.
CLK_P
(27MHz)
CLK_N
(27MHz)
CH1_D
CH2_D
FF
00
00
XY
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
Y3
Cb20
Y20
Y20
Cr20
Y21
Cb22
Y22
Cr22
Y23
Y23
Cb24
Y24
Y24
Cr24
Y25
Y25
DVO_A_
[7:0]
FF Cb20 00
00 Cr20 XY
Y21 Cb0 Cb22 Y0
Y22 Cr0 Cr22 Y1
Cb2 Cb24 Y2
Cr2 Cr24 Y3
Figure 3-10. 2-Ch Pixel-Interleaved Mode Timing Diagram
3.8.2.2 4-Ch Pixel-Interleaved Mode
In 4-Ch pixel-interleaved mode, the video output data with D1 resolution from four video channels is
multiplexed pixel by pixel at 108 MHz. The output DVO_A is used in this mode. The output clock OCLK_P
is synchronized with all four channels data. Each channel video data is compatible with ITU-R BT.656
format. Figure 3-11 shows the timing diagram for 4-Ch pixel-interleaved mode.
CLK (108MHz)
CH1_D
FF
00
00
XY
Cb0
Y0
Cb20
Y 20
Cr20
Y21
Cb22
Y22
CH2_D
Cr50
Y51
Cb52
Y52
Cr52
Y53
CH3_D
Cr94
Cr94
Cr92
Y93
Cb94
Y94
Y95
CH4_D
DVO_A_
[7:0]
FF Cb20 Cr50 Cr92 00
Y 20 Y51 Y93
00 Cr20 Cb52 Cb94 XY Y21 Y52 Y94 Cb0 Cb22 Cr52
Y0
Y22 Y53 Y95
Figure 3-11. 4-Ch Pixel-Interleaved Mode Timing Diagram
24
Functional Description
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In 4-Ch pixel-interleaved mode, TVP5158 also supports Half-D1 and CIF format data multiplexed at 54
MHz. The output DVO_A is used in this mode. The output clock OCLK_P is synchronized with all four
channels data.
3.8.2.3 Metadata Insertion for Non-Interleave Mode and Pixel-Interleaved Mode
In non-interleaved mode and pixel-interleaved mode, the video detection status (VDET) has also been
inserted in MSB of SAV/EAV control byte. Table 3-7 shows VDET status insertion in SAV/EAV codes.
Table 3-7. VDET Statues Insertion in SAV/EAV Codes
CONDITION
V TIME
FVH VALUE
V
SAV/EAV CODE SEQUENCE
4th
FIELD
H TIME
F
H
1st
2nd
3rd
VDET = 1 VDET = 0
1
1
1
1
2
2
2
2
Active
Active
Blank
Blank
Active
Active
Blank
Blank
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
80h
9Dh
ABh
B6h
C7h
DAh
ECh
F1h
00h
1Dh
2Bh
36h
47h
5Ah
6Ch
71h
In the pixel-interleaved mode, Channel ID is inserted in the horizontal blanking code as Table 3-8. The
backend chip can easily identify the video data from which video decoder channel by inserted Channel ID.
Table 3-8. Channel ID Insertion in Horizontal Blanking Code
H BLANKING CODE WITH CHANNEL ID
CHANNEL
Y
Cb
80h
81h
82h
83h
Cr
Ch1
Ch2
Ch3
Ch4
10h
11h
12h
13h
80h
81h
82h
83h
In the pixel-interleaved mode, Channel ID can also be inserted in 4 LSBs of SAV/EAV control byte
replacing protection bits as Table 3-9.
Table 3-9. Channel ID Insertion in SAV/EAV Code Sequence
CONDITION
FVH VALUE
V
SAV/EAV CODE SEQUENCE
4th
FIELD
V TIME H TIME
F
H
1st
2nd
3rd
Ch1
80h
90h
A0h
B0h
C0h
D0h
E0h
F0h
Ch2
81h
91h
A1h
B1h
C1h
D1h
E1h
F1h
Ch3
82h
92h
A2h
B2h
C2h
D2h
E2h
F2h
Ch4
83h
93h
A3h
B3h
C3h
D3h
E3h
F3h
1
1
1
1
2
2
2
2
Active
Active
Blank
Blank
Active
Active
Blank
Blank
SAV
EAV
SAV
EAV
SAV
EAV
SAV
EAV
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
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3.8.3 Line-Interleaved Mode Support (TVP5158 only)
The TVP5158 supports 2-Ch, 4-Ch, and 8-Ch line-interleaved modes. In the line-interleaved mode, the
video channels are multiplexed together on a line-by-line basis. Compared to the pixel-interleaved mode,
the line-interleaved mode significantly reduces the code complexity and MIPS consumption of the backend
processor. The 8-Ch modes require connecting two TVP5158 devices together using a video cascade
interface (see Section 3.8.3.3). The TVP5158 also supports different image resolutions (for example, D1,
Half-D1, and CIF) in the line-interleaved mode. All supported line-interleaved modes are shown in
Table 3-10.
Table 3-10. Output Ports Configuration for Line-Interleaved Mode
Cascade
Stage
I2C Address:
B0h
OCLK
(MHz)
Video Output Format
Port A
Port B
Port C
Port D
2-Ch D1
n/a
n/a
n/a
n/a
n/a
n/a
90h
92h
80h
A0h
A2h
A3h
54
27
Any 2 of 4 Ch Any 2 of 4 Ch
Any 2 of 4 Ch Any 2 of 4 Ch
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
2-Ch Half-D1
3-Ch D1
81/108
108
54
Any 3 of 4 Ch
All 4 Ch
Hi-Z
Hi-Z
Hi-Z
Hi-Z
4-Ch D1
4-Ch Half-D1
4-Ch CIF
All 4 Ch
27
All 4 Ch
All 4 Ch
(Y data)
All 4 Ch
(C data)
4-Ch D1 (16-bit)
n/a
n/a
1st
A8h
AAh
82h
86h
B2h
B6h
B3h
B7h
54
27
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
All 4 Ch
(Y data)
All 4 Ch
(C data)
4-Ch Half-D1 (16-bit)
6-Ch Half-D1
Output
2-Ch Half-D1
Input
81/108
27
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
6-Ch Half-D1
8-Ch Half-D1
8-Ch CIF
2-Ch Half-D1
Output
2nd
1st
Hi-Z
8-Ch Half-D1
Output
4-Ch Half-D1
Input
108
54
4-Ch Half-D1
Output
2nd
1st
Hi-Z
4-Ch CIF Input
Hi-Z
8-Ch CIF
Output
54
4-Ch CIF
Output
2nd
27
4 Ch Half-D1
+ Any 1 of 4
D1
4-Ch Half-D1 +
1-Ch D1
n/a
n/a
1st
E2h
E3h
C2h
81/108
54
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
4-Ch CIF +
Any 1 of 4 D1
4-Ch CIF + 1-Ch D1
6-Ch Half-D1
+ Any 1 of 8
D1
2-Ch Half-D1
Input
108
1-Ch D1 Input
Hi-Z
6-Ch Half-D1 +
1-Ch D1
2-Ch Half-D1
Output
1-Ch D1
Output
2nd
1st
C6h
F3h
F7h
27
81/108
27
Hi-Z
8-Ch CIF +
Any 1 of 8 D1
Hi-Z
1-Ch D1 Input 4-Ch CIF Input
Hi-Z Hi-Z
8-Ch CIF + 1-Ch D1
4-Ch CIF
Output
1-Ch D1
Output
2nd
3.8.3.1 2-Ch Line-Interleaved Mode
TVP5158 supports 2-Ch line-interleaved mode at 54 MHz. The video output data with D1 resolution from
any two video channels is multiplexed together on a line basis. The output ports DVO_A and DVO_B are
used in this mode. The output clock OCLK_P is synchronized with both output ports.
26
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3.8.3.2 4-Ch Line-Interleaved Mode
In 4-Ch line-interleaved mode, the video output data from all 4 channels is multiplexed together on a line
basis. The output resolution of video data can be D1, Half-D1 or CIF. For D1 and Half-D1 output
resolutions, the video output port can be configured to support 8-bit BT.656 or 16-Bit YCbCr 4:2:2 data
with embedded sync. Port DVO_A is used for 8-bit output. Ports DVO_A and DVO_B are used for 16-Bit
output. The output clock OCLK_P is synchronized with all four output ports.
TVP5158 supports multiplexing 4-Ch CIF and 1-Ch D1 data together and then output through DVO_A at
54 MHz. 1-Ch D1 can be from any one of 4 video channels. In typical surveillance applications, CIF
resolution is used for recording and D1 resolution is used for video preview.
TVP5158 also supports multiplexing 4-Ch Half-D1 and 1-Ch D1 data together and then output through
DVO_A at 108 MHz. The backend chip can use Half-D1 to generate CIF format by dropped one field.
Pleas note that the line-interleaved mode does NOT strictly output one line from each decoder channel
sequentially. The order of multiplexed the video line data is based on the availability of video output data
from each decoder channel. Therefore, it is possible to output two consecutive lines from the same
decoder channel or to skip one decoder channel output.
3.8.3.3 8-Ch Line-Interleaved Mode
Two TVP5158 devices can be cascade connected and work as single 8-Ch video decoder. In cascade
mode, the port DVO_C and DVO_D of master TVP5158 (first stage) can be configured as the video input
interface. The DVO_A and DVO_B of master TVP5158 are configured as the output interface for two
devices. This mode is dedicated for the backend chip with extremely limited input ports.
In the video cascade mode, the open-drain interrupt request (INTREQ) outputs from the first and second
stages can be combined using a wired-OR connection.
Typical applications with cascade mode show in the following diagrams.
Figure 3-12 shows the Cascade Connection for 16-Ch CIF Recoding and Multi-Ch CIF Preview.
Figure 3-13 shows the Cascade Connection for 16-Ch CIF Recoding and Multi-Ch Half-D1 Preview.
Figure 3-14 shows the Cascade Connection for 16-Ch CIF Recoding and 2-Ch D1/Multi-Ch CIF
Preview.
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8-Ch CIF
DVO_A_[7:0]
OCLK_P
VIN_1
VIN_2
VPIF_A
8Bit@54MHz
TVP5158
VIN_3
VIN_4
DVO_D_[7:0]
OCLKN/CLKIN
I2C
VIN_1
H.264
DVO_A_[7:0]
OCLK_P
VIN_2
VIN_3
VIN_4
16-Ch CIF Recording
4-Ch CIF
8Bit@27MHz
TVP5158
DM6467
DaVinci HD
VIN_1
VIN_2
8-Ch CIF
DVO_A_[7:0]
OCLK_P
TVP5158
VPIF_B
8Bit@54MHz
Multi-Ch CIF
Preview
VIN_3
VIN_4
DVO_D_[7:0]
OCLKN/CLKIN
I2C
VIN_1
VIN_2
DVO_A_[7:0]
OCLK_P
4-Ch CIF
8Bit@27MHz
TVP5158
VIN_3
VIN_4
Figure 3-12. Cascade Connection for 16-Ch CIF Recoding and Multi-Ch CIF Preview
DVO_A_[7:0]
OCLK_P
VIN_1
8-Ch Half-D1
VPIF_A
VIN_2
VIN_3
VIN_4
8Bit@108MHz
TVP5158
DVO_D_[7:0]
OCLKN/CLKIN
I2C
H.264
VIN_1
VIN_2
DVO_A_[7:0]
OCLK_P
16-Ch CIF Recording
4-Ch Half-D1
8Bit@54MHz
VIN_3 TVP5158
VIN_4
DM6467
DaVinci HD
VIN_1
DVO_A_[7:0]
OCLK_P
8-Ch Half-D1
VPIF_B
VIN_2
8Bit@108MHz
TVP5158
Multi-Ch Half-D1
Preview
VIN_3
DVO_D_[7:0]
VIN_4
OCLKN/CLKIN
I2C
VIN_1
VIN_2
DVO_A_[7:0]
OCLK_P
4-Ch Half-D1
8Bit@54MHz
TVP5158
VIN_3
VIN_4
Figure 3-13. Cascade Connection for 16-Ch CIF Recoding and Multi-Ch Half-D1 Preview
28
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8-Ch CIF + 1-Ch D1
8Bit@108MHz
DVO_A_[7:0]
OCLK_P
VIN_1
VPIF_A
VIN_2
VIN_3
VIN_4
TVP5158
DVO_C_[7:0]
DVO_D_[7:0]
OCLKN/CLKIN
I2C
4-Ch CIF
DVO_A_[7:0] 8Bit@ 27MHz
OCLK_P
VIN_1
VIN_2
VIN_3
VIN_4
DVO_B_[7:0]
1-Ch D1
H.264
TVP5158
16-Ch CIF Recording
8Bit@27MHz
DM6467
DaVinci HD
2-Ch D1/Multi-Ch CIF
Preview
8-Ch CIF + 1-Ch D1
8Bit@108MHz
DVO_A_[7:0]
OCLK_P
VIN_1
VIN_2
VIN_3
VIN_4
VPIF_B
TVP5158
DVO_C_[7:0]
DVO_D_[7:0]
OCLKN/CLKIN
I2C
4-Ch CIF
DVO_A_[7:0] 8Bit@ 27MHz
OCLK_P
VIN_1
VIN_2
VIN_3
VIN_4
DVO_B_[7:0]
1-Ch D1
TVP5158
8Bit@27MHz
Figure 3-14. Cascade Connection for 16-Ch CIF Recoding and 2-Ch D1/Multi-Ch CIF Preview
3.8.3.4 Hybrid Modes
The TVP5158 also supports multiplexing both scaled and unscaled data streams in the line-interleaved
mode. In these hybrid modes (4-Ch Half-D1 + 1-Ch D1, 4-Ch CIF + 1-Ch D1, and 8-Ch CIF + 1-Ch D1),
the D1 line is split into two equal-length half lines and then multiplexed with the other CIF lines. Therefore,
all video data is actually multiplexed by CIF line length. In these hybrid modes, the line cropping mode
affects both the scaled and unscaled data streams. The line cropping mode is controlled by bit 6 of I2C
register B1h.
3.8.3.5 Metadata Insertion for Line-Interleaved Mode
In the line-interleaved mode, the video data is rearranged on a line-by-line basis. There can be no
guaranteed output line order, because all analog video inputs are not synchronized. To be compatible with
general backend BT.656 decoder, the video data is encapsulated on TVP5158 output so that all input data
is preserved and output data is understandable to a BT.656 decoder.
To prevent confusion over image line count and vertical blanking appearing haphazardly, SAV/EAV codes
have FID and V data stripped and replaced with FID = V = 0. Because vertical blanking in the input is
being masked out, artificial vertical sync is inserted every encapsulated frame (a.k.a., super frame). Thus,
to the unaware BT.656 decoder, the stream appears to be progressive data with two lines of vertical
blanking. The default super-frame format and timing for each line-interleaved output format is shown in
Table 3-11.
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Table 3-11. Default Super-Frame Format and Timing
OCLK
(MHz)
EAV
(bytes)
SAV
(bytes)
SF HSIZE SF VSIZE
Video Output Formats
EAV2SAV (bytes)
SAV2EAV (bytes)
(bytes)
(bytes)
Cropping Enable
2-Ch D1
n/a
54
n/a
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
0
n/a
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
0
n/a
n/a
280
128
848
280
280
128
128
136
60
248
112
816
248
248
112
112
120
52
1416
712
1416
1416
1416
712
712
708
356
712
712
712
712
712
712
712
712
712
712
1448
728
1448
1448
1448
728
728
724
364
728
728
728
728
728
728
728
728
728
728
1704
848
1052
1052
1577
1577
2102
2102
1054
2102
2102
3152
3152
4095
2106
4095
3152
3152
2104
3156
3156
2-Ch Half-D1
27
108
81
2272
1704
1704
848
3-Ch D1(1)
4-Ch D1
4-Ch Half-D1
108
54
4-Ch CIF
27
848
4-Ch D1 (16 bit)
4-Ch Half-D1 (16 bit)
54
852
27
424
108
81
416
128
128
128
128
416
128
128
416
128
400
112
112
1121
112
400
112
112
400
112
1136
848
6-Ch Half-D1(1)
8-Ch Half-D1
8-Ch CIF
108
54
848
848
6-Ch Half-D1 + 1-Ch D1
108
108
81
848
1136
848
4-Ch Half-D1 + 1-Ch D1(1)
4-Ch CIF + 1-Ch D1
54
848
108
81
1136
848
8-Ch CIF + 1-Ch D1(1)
(1) The output clock frequency for these output formats can be selected using bit 6 of I2C register B2h. The default clock frequency is 108
MHz.
4-Byte Start Code (SC3:SC0) is inserted immediately after SAV code for encapsulated frame. Figure 3-15
and Figure 3-16 show the start code details.
Horizontal Active Period (SAV2EAV)
Horizontal Blanking Interval
EAV
EAV2SAV
SAV
Start Code
Channel Data
FFh 00h 00h XYh
FFh 00h 00h XYh SC3 SC3 SC2 SC2 SC1 SC1 SC0 SC0
Cb Cr
Y
Y
Start code for
channel data
SAV for
encapsulated
frame
64 clock cycles (fixed)
EAV for
encapsulated
frame
Figure 3-15. Start Code in 8-Bit BT.656 Interface
Horizontal Blanking Interval
Horizontal Active Period (SAV2EAV)
EAV
EAV2SAV
SAV
Start Code
Channel Data
FFh 00h 00h XYh
FFh 00h 00h XYh
FFh 00h 00h XYh SC3 SC2 SC1 SC0
Y
Y
Y
Y
FFh 00h 00h XYh SC3 SC2 SC1 SC0
Cb Cr Cb Cr
SAV for
encapsulated
frame
Start code for
channel data
64 clock cycles (fixed)
EAV for
encapsulated
frame
Figure 3-16. Start Code in 16-Bit YCbCr 4:2:2 Interface
30
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Table 3-12 and Table 3-13 show the bit assignment and field definition of 4-Byte start code for Active
Video Line.
Table 3-12. Bit Assignment of 4-Byte Start Code for Active Video Line
BYTE
SC[3]
SC[2]
SC[1]
SC[0]
7
6
5
4
VDET
H
3
2
1
0
1
BOP
BOL
EOP
EOL
RSVD
VCS_ID
CH_ID[1:0]
LN_ID[8:7]
0
~LD_ID[6]
1
RSVD
LN_ID[6:0]
P3
F
V
P2
P1
P0
Table 3-13. Bit Field Definition of 4-Byte Start Code for Active Video Line
BIT
NAME
FUNCTION
31
1
Always set to 1.
Active-high beginning of period flag. Set high for first line of both active video and vertical blanking interval.
In split-line mode, the BOP bit is the same for both halves of the same line.
30
BOP
0: Not BOP
1: BOP
Active-high end of period flag. Set high for last line of both active video and vertical blanking interval. In
split-line mode, the EOP bit is the same for both halves of the same line.
29
[28:27]
26
EOP
RSVD
0: Not EOP
1: EOP
Reserved
Video cascade stage ID. Set to 0 for normal operation. In cascade mode, the back-end device (for example,
TMS320DM6467) interfaces to the first stage.
VCS_ID
0: First stage (channels 1 to 4)
1: Second stage (channels 5 to 8)
2-bit Channel ID. Video decoder channel number.
00: Channel 1
[25:24]
CH_ID[1:0]
01: Channel 2
10: Channel 3
11: Channel 4
23
22
0
Always set to 0.
Active-high beginning of line flag. Used in split-line mode which may be required for hybrid formats (e.g.
1-Ch D1 + 8-Ch CIF). Set high when the current encapsulated line of channel data includes the beginning of
a video line.
BOL
0: BOL not included (2nd half of split line)
1: BOL included (1st half of split line or full line)
Active-high end of line flag. Used in split-line mode which may be required for hybrid formats (e.g. 1-Ch D1 +
8-Ch CIF). Set high when the current line of channel data includes the end of a video line.
21
20
EOL
0: EOL not included (1st half of split line)
1: EOL included (2nd half of split line or full line)
Active-high video detection status
0: Video not detected
VDET
1: Video detected
[19:18]
[17:16]
15
RSVD
Reserved
Two MSBs of 9-bit Line ID, active video line number. Line counter resets to 000h at beginning of active
video (that is, resets once per field). During the vertical blanking interval, the line counter may either
continue counting or hold the terminal count determined at the end of active video.
LN_ID[8:7]
~LN_ID[6]
Always set to the complement of bit 14 (LN_ID[6]).
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Table 3-13. Bit Field Definition of 4-Byte Start Code for Active Video Line (continued)
BIT
[14:8]
7
NAME
LN_ID[6:0]
1
FUNCTION
Seven LSBs of 9-bit Line ID, active video line number. Line counter resets to 000h at beginning of active
video (that is, resets once per field). During the vertical blanking interval, the line counter may either
continue counting or hold the terminal count determined at the end of active video.
Always set to 1.
F-bit
6
5
4
F
V
H
0: First field of frame
1: Second field of frame
V-bit
0: when not in vertical blanking
1: during vertical blanking
H-bit. Always set to 0.
0: SAV
1: EAV (never used)
3
2
1
0
P3
P2
P1
P0
P3 = V XOR H, Protection bits used for error detection/correction
P2 = F XOR H, Protection bits used for error detection/correction
P1 = F XOR V, Protection bits used for error detection/correction
P0 = F XOR V XOR H, Protection bits used for error detection/correction
NOTE
For line-interleaved output mode, if none of video decoder channels has the data ready at a
given time, TVP5158 outputs the dummy line until any one of video decoder channels is
ready to output a line. The backend chip needs to keep only the active video line and ignore
the dummy line.
The start code of the dummy line is different with active video line. Table 3-14 shows the bit assignment
and field definition of 4-Byte start code for the Dummy Line.
Table 3-14. Bit Assignment of 4-Byte Start Code for the Dummy Line
BYTE
SC[3]
SC[2]
SC[1]
SC[0]
7
0
0
0
0
6
0
0
0
0
5
0
0
0
0
4
0
0
0
0
3
0
0
0
0
2
0
0
0
0
1
0
0
0
0
0
1
1
1
1
NOTE
The Dummy Line can be distinguished from active video line by looking at the MSB of byte
SC[0].
3.9 Audio Sub-System (TVP5157 and TVP5158 Only)
The audio sub-system integrates a 4-Ch audio analog-to-digital converter, digital processing, and I2S
encoder. TVP5158 audio sub-system supports 4-Ch mono analog audio input and standard/multiple I2S
output. TVP5158 also supports audio cascade connection up to four devices cascade connected for 16-Ch
audio input.
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3.9.1 Features
•
Four mono analog audio input channels
Requires external passive attenuator to support 2.828-Vpp analog audio input
Programmable Gain Amplifier (PGA)
Gain range: -12 ~ 0 dB, Gain Step: 1.5 dB
–
•
–
•
•
•
•
Integrated Anti-Aliasing Filter (AAF)
10-Bit Analog-to-Digital Converter
Integrates Audio High-pass filter to eliminate low frequency hum
Digital serial audio interface
–
–
–
–
–
16-Bit Linear PCM, 8-Bit A-Law and 8-Bit µ-Law Data
I2S or DSP Format
Master and Slave mode operation
Up to 16 slots TDM output
64 fs or 256 fs system clock
•
•
Sampling Rate : 16 kHz, 8 kHz
Audio Cascade connection
–
–
–
Up to 4 cascaded devices
I2S format
256 fs system clock
•
Audio Mixing Output
–
–
Audio ADC has one register to set mix ratio
The Mixing output pin SD_M can also be used for recording. Combined with the recording output
pin SD_R, two I2S bit-streams can be output simultaneously.
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3.9.2 Audio Sub-System Functional Diagram
Figure 3-17. Audio Sub-System Functional Diagram
3.9.3 Serial Audio Interface
The timing for the TVP5158 serial audio interface is shown in Figure 3-18. The TVP5158 audio data
output (SD_R) and frame sync pulse (LRCLK) are aligned with the falling edge of the bit clock (BCLK).
The TVP5158 audio data is delayed one BCLK cycles from the falling edge of the frame sync pulse. In the
DSP mode, the TVP5158 frame sync pulse is high for only one BCLK cycle.
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1/fs
LRCLK_R
BCLK_R
SD_R
LSB MSB
LSB MSB
LSB
Data 1
Data 2
(a) I2S Format
1/fs
LRCLK_R
BCLK_R
SD_R
LSB MSB
LSB MSB
LSB
Data 1
(b) DSP Format
Figure 3-18. Serial Audio Interface Timing Diagram
Data 2
3.9.4 Analog Audio Input Clamping
An internal clamping circuit provides mid-level clamping of all four analog audio inputs to a dc level of
approximately 0.625 V.
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3.9.5 Audio Cascade Connection
AIN_1
SD_CO
BCLK_R
LRCLK_R
SD_R
Record Output
(AIN_1-AN_16)
Mix Output
AIN_2
AIN_3
AIN_4
TVP5158
SD_M
XTAL_IN
XTAL
XTAL_OUT
First Stage
BCLK_CI
OSC_OUT
LRCLK_CI
SD_CI
AIN_5
AIN_6
AIN_7
AIN_8
BCLK_R
LRCLK_R
SD_R
SD_CO
BCLK_R
LRCLK_R
SD_R
Record Output
(AIN_5-AN_16)
SD_M
SD_M
TVP5158
Second Stage
XTAL_IN
BCLK_CI
OSC_OUT
LRCLK_CI
SD_CI
AIN_9
BCLK_R
LRCLK_R
SD_R
BCLK_R
LRCLK_R
SD_R
SD_CO
Record Output
AIN_10
AIN_11
AIN_12
(AIN_9-AN_16)
TVP5158
SD_M
SD_M
Third Stage
XTAL_IN
BCLK_CI
OSC_OUT
LRCLK_CI
SD_CI
AIN_13
SD_CO
BCLK_R
BCLK_R
LRCLK_R
SD_R
Record Output
AIN_14
AIN_15
AIN_16
LRCLK_R
SD_R
(AIN_13-AN_16)
TVP5158
SD_M
SD_M
Last Stage
XTAL_IN
OSC_OUT
SD_CI
Figure 3-19. Audio Cascade Connection
TVP5158 supports up to four devices cascaded together for audio cascade connection. The I2S output of
master TVP5158 (1st stage) combines all audio channel data from cascaded TVP5158 devices.
Key Features of Audio Cascade Connection
•
•
•
•
•
•
•
16-Bit linear PCM data
I2S format
Bit Clock: 256 fs
All cascade inputs are always in slave mode
Second to fourth stage serial audio outputs are always in master mode
First stage serial audio output can be in either master or slave mode
Common clock source for all cascaded devices is required
The Serial Audio Output Channel Assignment shown on Table 3-15.
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Table 3-15. Serial Audio Output Channel Assignment
I2S
LRCLK_R Left
Slot 4 Slot 5
LRCLK_R Right
tdm_ch
tdm_out_pin
0
Slot 1
SD_R AIN_1
SD_M
Slot 2
Slot 3
Slot 6
Slot 7
Slot 8
Slot 9 Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Slot 16
AIN_2
0 (2 channel)
1 (4 channel)
2 (8 channel)
3 (12 channel)
4 (16 channel)
SD_R AIN_1
SD_M AIN_2
1
0
1
0
1
0
1
0
1
SD_R AIN_1 AIN_3
SD_M
AIN_2 AIN_4
SD_R AIN_1
SD_M AIN_3
AIN_2
AIN_4
SD_R AIN_1 AIN_3 AIN_5 AIN_7
SD_M
AIN_2 AIN_4 AIN_6 AIN_8
SD_R AIN_1 AIN_5
SD_M AIN_3 AIN_7
AIN_2 AIN_6
AIN_4 AIN_8
SD_R AIN_1 AIN_3 AIN_5 AIN_7 AIN_9 AIN_11
SD_M
AIN_2 AIN_4 AIN_6 AIN_8 AIN_10 AIN_12
SD_R AIN_1 AIN_5 AIN_9
SD_M AIN_3 AIN_7 AIN_11
AIN_2 AIN_6 AIN_10
AIN_4 AIN_8 AIN_12
SD_R AIN_1 AIN_3 AIN_5 AIN_7 AIN_9 AIN_11 AIN_13 AIN_15 AIN_2 AIN_4 AIN_6 AIN_8 AIN_10 AIN_12 AIN_14 AIN_16
SD_M
SD_R AIN_1 AIN_5 AIN_9 AIN_13
SD_M AIN_3 AIN_7 AIN_11 AIN_15
AIN_2 AIN_6 AIN_10 AIN_14
AIN_4 AIN_8 AIN_12 AIN_16
DSP Format
tdm_ch
tdm_out_pin
0
Slot 1
Slot 2
Slot 3
Slot 4
Slot 5
Slot 6
Slot 7
Slot 8
Slot 9 Slot 10 Slot 11 Slot 12 Slot 13 Slot 14 Slot 15 Slot 16
SD_R AIN_1 AIN_2
SD_M
0 (2 channel)
1 (4 channel)
2 (8 channel)
3 (12 channel)
4 (16 channel)
SD_R AIN_1
SD_M AIN_2
1
0
1
0
1
0
1
0
1
SD_R AIN_1 AIN_3 AIN_2 AIN_4
SD_M
SD_R AIN_1 AIN_2
SD_M AIN_3 AIN_4
SD_R AIN_1 AIN_3 AIN_5 AIN_7 AIN_2 AIN_4 AIN_6 AIN_8
SD_M
SD_R AIN_1 AIN_5 AIN_2 AIN_6
SD_M AIN_3 AIN_7 AIN_4 AIN_8
SD_R AIN_1 AIN_3 AIN_5 AIN_7 AIN_9 AIN_11 AIN_2 AIN_4 AIN_6 AIN_8 AIN_10 AIN_12
SD_M
SD_R AIN_1 AIN_5 AIN_9 AIN_2 AIN_6 AIN_10
SD_M AIN_3 AIN_7 AIN_11 AIN_4 AIN_8 AIN_12
SD_R AIN_1 AIN_3 AIN_5 AIN_7 AIN_9 AIN_11 AIN_13 AIN_15 AIN_2 AIN_4 AIN_6 AIN_8 AIN_10 AIN_12 AIN_14 AIN_16
SD_M
SD_R AIN_1 AIN_5 AIN_9 AIN_13 AIN_2 AIN_6 AIN_10 AIN_14
SD_M AIN_3 AIN_7 AIN_11 AIN_15 AIN_4 AIN_8 AIN_12 AIN_16
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3.10 I2C Host Interface
The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line
(SCL), which carry information between the devices connected to the bus. The input pins I2CA0, I2CA1
and I2CA2 are used to select the slave address to which the device responds. Although the I2C system
can be multi-mastered, the TVP5158 decoder functions as a slave device only.
Both SDA and SCL must be connected to IOVDD via pullup resistors. When the bus is free, both lines are
high. The slave address select terminals (I2CA0, I2CA1 and I2CA2) enable the use of up to eight devices
on the same I2C bus. At the trailing edge of reset, the status of the I2CA0, I2CA1 and I2CA2 lines are
sampled to determine the device address used. Table 3-16 summarizes the terminal functions of the I2C
host interface. Table 3-17 shows the device address selection options.
Table 3-16. I2C Terminal Description
SIGNAL
I2CA0
I2CA1
I2CA2
SCL
TYPE
DESCRIPTION
I
Slave address selection
Slave address selection
Slave address selection
Input/output clock line
Input/output data line
I
I
I/O (open drain)
I/O (open drain)
SDA
Table 3-17. I2C Host Interface Device Addresses
A6
1
A5
0
A4
1
A3
1
A2(I2CA2)
A1(I2CA1)
A0 (I2CA0)
R/W
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
HEX
B1/B0
B3/B2
B5/B4
B7/B6
B9/B8
BB/BA
BD/BC
BF/BE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
Data transfer rate on the bus is up to 400 kbit/s. The number of devices connected to the bus is
dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the
high period of the SCL except for start and stop conditions. The high or low state of the data line can only
change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the
SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high
indicates an I2C stop condition.
Every byte placed on the SDA must be 8 bits long. The number of bytes which can be transferred is
unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is
generated by the I2C master.
To simplify programming of each of the 4 decoder channels a single I2C write transaction can be
transmitted to any one or more of the 4 cores in parallel. This reduces the time required to download
firmware or to configure the device when all channels are to be configured in the same manner. It also
enables the addresses for all registers to be common across all decoders.
I2C subaddress FEh contains 4 bits with each bit corresponding to one of the decoder cores. If a decoder
write enable bit is set, then I2C write transactions are sent to the corresponding decoder core. For
multi-byte I2C write transactions, there are options to auto-increment the subaddress or to auto-increment
through the selected decoders or both.
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I2C subaddress FFh contains 4 bits with each bit corresponding to one of the decoder cores. If a decoder
read enable bit is set, then I2C read transactions are sent to the corresponding decoder core.
If more than one decoder is enabled for reads, then the lowest numbered decoder that is enabled
responds to the read transaction. For multi-byte I2C read transactions, there are options to auto-increment
the subaddress or to auto-increment through the selected decoders or both.
3.10.1 I2C Write Operation
Data transfers occur utilizing the following formats.
An I2C master initiates a write operation to the decoder by generating a start condition (S) followed by the
decoder I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle.
After receiving an acknowledge from the decoder, the master presents the subaddress of the register, or
the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The
decoder acknowledges each byte after completion of each transfer. The I2C master terminates the write
operation by generating a stop condition (P).
Step 1
0
I2C Start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
1
0
X
0
Step 3
9
I2C Acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C Write register address (master)
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Step 5
9
I2C Acknowledge (slave)
A
Step 6(1)
7
6
5
4
3
2
1
0
I2C Write data (master)
Data
Data
Data
Data
Data
Data
Data
Data
Step 7(1)
9
I2C Acknowledge (slave)
A
Step 8
0
I2C Stop (master)
P
(1) Repeat steps 6 and 7 until all data have been written.
3.10.2 I2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C
master initiates a write operation to the decoder by generating a start condition (S) followed by the
decoder slave address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving
acknowledge from the decoder, the master presents the subaddress of the register or the first of a block of
registers it wants to read. After the cycle is acknowledged, the master has the option of generating a stop
condition or not.
In the data phase, an I2C master initiates a read operation to the decoder by generating a start condition
followed by the decoder I2C slave address (as shown below for a read operation), in MSB first bit order,
followed by a 1 to indicate a read cycle. After an acknowledge from the decoder, the I2C master receives
one or more bytes of data from the decoder. The I2C master acknowledges the transfer at the end of each
byte. After the last data byte has been transferred from the decoder, the master generates a not
acknowledge followed by a stop.
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Read Phase 1
Step 1
0
I2C Start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
X
X
X
0
Step 3
9
I2C Acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C Read register address (master)
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Addr
Step 5
9
I2C Acknowledge (slave)
A
Step 6(1)
0
I2C Stop (master)
P
(1) Step 6 is optional.
Read Phase 2
Step 7
0
I2C Start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C General address (master)
1
0
1
1
X
X
X
1
Step 9
9
I2C Acknowledge (slave)
A
Step 10(1)
7
6
5
4
3
2
1
0
I2C Read data (slave)
Data
Data
Data
Data
Data
Data
Data
Data
Step 11(1)
9
I2C Not Acknowledge (master)
A
Step 12
0
I2C Stop (master)
P
(1) Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
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3.10.3 VBUS Access
The TVP5158 video decoder has additional internal registers accessible through an indirect access to an
internal 24-bit address wide VBUS. Figure 3-20 shows the VBUS registers access.
I2C Registers
VBUS Registers
00h
00 0000h
40 3E50h
40 3EEFh
Comb
Filter RAM
I2C
VBUS [23:0]
Host
Processor
E0h
VBUS
Data
E1h
E8h
VBUS
Address
EAh
FFh
A0 3FFFh
Figure 3-20. VBUS Access
VBUS Write
Single Byte
S
S
B8
B8
ACK
ACK
E8
E0
ACK
VA0
ACK
VA1
ACK
ACK
P
VA2
VA2
ACK
ACK
P
ACK
Send Data
Multiple Bytes
S
S
B8
B8
ACK
ACK
E8
E1
ACK
ACK
VA0
ACK
VA1
ACK
ACK
. . .
P
Send Data
Send Data
ACK
P
VBUS Read
Single Byte
S
S
B8
B8
ACK
ACK
E8
E0
ACK
ACK
VA0
S
ACK
B9
VA1
ACK
ACK
VA2
ACK
NAK
P
P
Read Data
Multiple Bytes
S
S
B8
B8
ACK
ACK
E8
E1
ACK
ACK
VA0
S
ACK
B9
VA1
ACK
ACK
VA2
ACK
P
Read Data
MACK
. . .
Read Data
NAK
P
NOTE: Examples use default I2C address
ACK: Acknowledge generated by the slave
MACK: Acknowledge generated by the master
NAK: No Acknowledge generated by the master
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3.11 Clock Circuits
An analog clock multiplier PLL is used to generate a system clock from an external 27-MHz crystal
(fundamental resonant frequency) or external clock reference input. A crystal can be connected across
terminals 99 (XTAL_IN) and 101 (XTAL_OUT), or a 1.8-V external clock input can be connected to
terminal 99. Four horizontal PLLs generate the line-locked sample clock for each video decoder core from
the system clock. Four color PLLs generate the color subcarrier frequency for each video decoder core
from the corresponding line-locked clock. Four vertical PLLs generate the field/frame sync for each video
decoder core. A frequency synthesizer generates the 32.768-MHz audio oversampling clock for each
analog audio input from the system clock.
Figure 3-21 shows the reference clock configurations. For the example crystal circuit shown, the external
capacitors must have the following relationship:
CL1 = CL2 = 2CL – CSTRAY
Where,
CSTRAY is the terminal capacitance with respect to ground
CL is the crystal load capacitance specified by the crystal manufacturer
27-MHz
Crystal
0 W
VSSA
27-MHz CLK
Output to other TVP5158
XTAL_IN pin
27-MHz CLK
Output to other TVP5158
XTAL_IN pin
Figure 3-21. Clock and Crystal Connectivity
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3.12 Reset Mode
Terminal 3 (RESETB) is active low signal to hold the decoder into reset. Table 3-18 shows the
configuration of reset mode. Table 3-19 describes the status of the decoder signals during and
immediately after reset. Figure 3-22 shows the reset timing.
After power-up, the device is in an unknown state until properly reset. An active-low reset, Reset B, of
greater than or equal to 20 ms is required following active and stable supply ramp-up. To avoid potential
I2C issues, keep SCL and SDA inactive (high) for at least 260 µs after reset goes high. There are no
power sequencing requirements except that all power supplies should become active and stable within
500 ms of each other.
Table 3-18. Reset Mode
RESETB
CONFIGURATION
Resets the decoder
Normal operation
0
1
Table 3-19. Reset Sequence
SIGNAL NAME
DURING RESET
RESET COMPLETED
DVO_A_[7:0], DVO_B_[7:0], DVO_C_[7:0], DVO_D_[7:0], OCLK_P, OCLK_N,
INTREQ, I2CA[2:0], BCLK_R, LRCLK_R, SD_R, SD_M, SD_CO
Input
High-impedance
RESETB, SDA, SCL, LRCLK_CI, BCLK_CI, SD_CI, XTAL_IN
XTAL_OUT, OSC_OUT
Input
Input
Output
Output
20 ms (min)
Normal operation
RESETB
(Terminal 3)
Reset
260 µs (min)
Invalid I2C Cycle
Valid
Figure 3-22. Reset Timing
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4
Internal Control Registers
4.1 Overview
The decoder is initialized and controlled by a set of internal registers which set all device operating
parameters. Communication between the external controller and the decoder is through I2C. Table 4-1
shows the summary of these registers. The reserved registers must not be written. Reserved bits in the
defined registers must be written with 0s, unless otherwise noted. The detailed programming information
of each register is described in the following sections.
I2C register FEh controls which of the four decoders will receive I2C commands. I2C register FFh controls
which decoder core responds to I2C reads. Note that for a read operation, it is necessary to perform a
write first to set the desired subaddress for reading.
Compared to previous video decoder, TVP5154A, the TVP5158, TVP5157, and TVP5156 add decoder
auto increment and address auto increment bits control. If decoder auto increment bit is set, the next
read/write is from/to the next decoder that is enabled. If address auto-increment bit is set, the address
increments after all the decoders enabled read/writes are completed. The detail of I2C registers FEh and
FFh is shown in their register section.
Table 4-1. Registers Summary
I2C
REGISTER NAME
DEFAULT
R/W(1)
SUBADDRESS
Status 1
00h
R
R
R
Status 2
01h
Color Subcarrier Phase Status
Reserved
02h
03h
ROM Version
04h
R
R
R
RAM Version MSB
RAM Version LSB
Reserved
05h
06h
07h
Chip ID MSB
08h
51h
58h
R
R
Chip ID LSB
09h
Reserved
0Ah - 0Bh
0Ch
0Dh
0Eh
Video Standard Status
Video Standard Select
CVBS Autoswitch Mask
Auto Contrast Mode
Luminance Brightness
Luminance Contrast
R
00h
03h
03h
80h
80h
00h
80h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0Fh
10h
11h
Brightness and Contrast Range Extender
Chrominance Saturation
Chrominance Hue
12h
13h
14h
Reserved
15h
Color Killer
16h
10h
R/W
Reserved
17h
Luminance Processing Control 1
Luminance Processing Control 2
Power Control
18h
40h
00h
00h
00h
0Ch
R/W
R/W
R/W
R/W
R/W
19h
1Ah
Chrominance Processing Control 1
Chrominance Processing Control 2
1Bh
1Ch
(1) R = Read only, W = Write only, R/W = Read and write
44
Internal Control Registers
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Table 4-1. Registers Summary (continued)
I2C
REGISTER NAME
DEFAULT
R/W(1)
SUBADDRESS
1Dh - 1Fh
20h
Reserved
AGC Gain Status 1
AGC Gain Status 2
Reserved
R
R
21h
22h
Back-End AGC Status
Status Request
23h
R
24h
00h
F5h
00h
00h
R/W
R/W
R/W
R/W
AFE Gain Control
Luma ALC Freeze Upper Threshold
Chroma ALC Freeze Upper Threshold
Reserved
25h
26h
27h
28h
AGC Increment Speed
AGC Increment Delay
AGC Decrement Speed
AGC Decrement Delay
AGC White Peak Processing
Back-End AGC Control
Reserved
29h
06h
1Eh
04h
00h
F2h
08h
R/W
R/W
R/W
R/W
R/W
R/W
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh - 33h
34h - 35h
36h - 47h
48h
AFE Fine Gain
086Ah
R/W
Reserved
AVID Start Pixel LSBs
AVID Start Pixel MSBs
AVID Pixel Width
7Ah/84h
00h/00h
R/W
R/W
R/W
49h
4Ah - 4Bh
4Ch - 5Bh
5Ch
02D0h/02D0h
Reserved
NR_Max_Noise
28h
09h
R/W
R/W
R/W
R/W
R/W
NR_Control
5Dh
NR_Noise_Filter
5Eh - 5Fh
60h
0330h
00h
Operation Mode Control
Color PLL Speed Control
Reserved
61h
09h
62h - 7Bh
7Ch
Sync Height Low Threshold
Sync Height High Threshold
Reserved
02h
08h
03h
00h
R/W
R/W
R/W
R/W
7Dh
7Eh - 80h
81h
Clear Lost Lock Detect
Reserved
82h - 84h
85h
V-Sync Filter Shift
Reserved
03h
R/W
86h
656 Version/F Bit Control
F- and V-Bit Decode Control
F- and V-Bit Control
Reserved
87h
00h
00h
16h
R/W
R/W
R/W
88h
89h
8Ah - 8Bh
8Ch
Output Timing Delay
Reserved
00h
R/W
8Dh - 8Fh
8Fh
Auto Contrast User Table Index
Blue Screen Y Control
Blue Screen Cb Control
Blue Screen Cr Control
Blue Screen LSB Control
04h
10h
80h
80h
00h
R/W
R/W
R/W
R/W
R/W
90h
91h
92h
93h
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Table 4-1. Registers Summary (continued)
I2C
REGISTER NAME
DEFAULT
R/W(1)
SUBADDRESS
Noise Measurement LSB
Noise Measurement MSB
Weak Signal High Threshold
Weak Signal Low Threshold
Reserved
94h
R
95h
R
96h
60h
50h
R/W
R/W
97h
98h - 9Dh
9Eh
NR_Y_T0
0Ah
BCh
BCh
R/W
R/W
R/W
NR_U_T0
9Fh
NR_V_T0
A0h
Reserved
A1h
Vertical Line Count Status
Reserved
A2h - A3h
A4h - A7H
A8h
R
Output Formatter Control 1 (write to all four decoder cores)
Output Formatter Control 2 (write to all four decoder cores)
Reserved
44h
40h
R/W
R/W
A9h
AAh - ACh
ADh
Interrupt Control
00h
01h
00h
00h
10h
20h
E4h
E4h
00h
1Bh
04h
40h
00h
00h
00h
00h
88h
88h
C9h
01h
00h
00h
00h
00h
A5h
FFh
7Eh
01h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Embedded Sync Offset Control 1 (write to all four decoder cores)
Embedded Sync Offset Control 2 (write to all four decoder cores)
AVD Output Control 1
AEh
AFh
B0h
AVD Output Control 2
B1h
OFM Mode Control
B2h
OFM Channel Select 1
B3h
OFM Channel Select 2
B4h
OFM Channel Select 3
B5h
OFM Super-Frame Size LSBs
OFM Super-Frame Size MSBs
OFM H-Blank Duration LSBs
OFM H-Blank Duration MSBs
Misc Ofm Control
B6h
B7h
B8h
B9h
BAh
Reserved
BBh - BFh
C0h
Audio Sample Rate Control
Analog Audio Gain Control 1
Analog Audio Gain Control 2
Audio Mode Control
C1h
C2h
C3h
Audio Mixer Select
C4h
Audio Mute Control
C5h
Audio Mixing Ratio Control 1
Audio Mixing Ratio Control 2
Audio Cascade Mode Control
Reserved
C6h
C7h
C8h
C9h
Reserved
CAh
Reserved
CBh
Reserved
CCh
Reserved
CDh - CFh
D0h
Super-frame EAV2SAV duration status LSBs
Super-frame EAV2SAV duration status MSBs
Super-frame SAV2EAV duration status LSBs
Super-frame SAV2EAV duration status MSBs
R
R
R
R
D1h
D2h
D3h
46
Internal Control Registers
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Table 4-1. Registers Summary (continued)
I2C
REGISTER NAME
DEFAULT
R/W(1)
SUBADDRESS
D4h - DFh
E0h
Reserved
VBUS Data Access With No VBUS Address Increment
R/W
R/W
VBUS Data Access With VBUS Address Increment
Reserved
E1h
E2h - E7h
E8h - EAh
EBh - F1h
F2h
VBUS Address Access
Reserved
00 0000h
R/W
R/W
R
Interrupt Status
Reserved
F3h
Interrupt Mask
F4h
00h
R/W
Reserved
F5h
Interrupt Clear
F6h
00h
0Fh
01h
R/W
R/W
R/W
Decoder Write Enable
Decoder Read Enable
FEh
FFh
4.2 Register Definitions
Table 4-2. Status 1
Subaddress
Default
00h
Read only
7
6
5
4
3
2
1
0
Color
Line-alternating
status
Field rate
status
Vertical sync
lock status
Horizontal sync
lock status
Reserved
Lost lock detect subcarrier lock
status
TV/VCR status
Line-alternating status
0
Non line alternating
1
Line alternating
Field rate status
0
60 Hz
50 Hz
1
Lost lock detect
0
1
No lost lock since this bit was last cleared
Lost lock since this bit was last cleared
Color subcarrier lock status
0
1
Color subcarrier is not locked
Color subcarrier is locked
Vertical sync lock status
0
1
Vertical sync is not locked
Vertical sync is locked
Horizontal sync lock status
0
Horizontal sync is not locked
1
Horizontal sync is locked
TV/VCR status
0
1
TV
VCR
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Table 4-3. Status 2
Subaddress
Default
01h
Read only
7
6
5
4
3
2
1
0
Weak signal
detection
PAL switch
polarity
Field sequence
status
Signal present
Color killed
Macrovision detection [2:0]
Signal present
0
1
Signal is not present
Signal is present
Weak signal detection
0
1
No weak signal
Weak signal mode
PAL switch polarity
0
1
PAL switch is zero
PAL switch is one
Field sequence status
0
Even field
Odd field
1
Color killed
0
1
Color killer is not active
Color killer is active
Macrovision detection [2:0]
000
001
010
011
100
101
110
111
No copy protection
AGC pulses/pseudo syncs present (Type 1)
2-line colorstripe only present
AGC pulses/pseudo syncs and 2-line colorstripe present (Type 2)
Reserved
Reserved
4-line colorstripe only present
AGC pulses/pseudo syncs and 4-line colorstripe present (Type 3)
Table 4-4. Color Subcarrier Phase Status
Subaddress
Default
02h
Read only
7
6
5
4
3
2
1
0
Color subcarrier phase [7:0]
This register shows the color subcarrier phase.
Table 4-5. ROM Version
Subaddress
Default
04h
Read only
7
6
5
4
3
2
1
0
ROM version [7:0]
ROM Version [7:0]
ROM revision number = 02h for PG 1.1
48
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Table 4-6. RAM Version MSB
Subaddress
Default
05h
Read only
7
6
5
4
3
2
1
0
RAM version MSB [7:0]
RAM version MSB [7:0]
This register identifies the MSB of the RAM code revision number.
Table 4-7. RAM Version LSB
Subaddress
Default
06h
Read only
7
6
5
4
3
2
1
0
RAM version LSB [7:0]
RAM version LSB [7:0]
This register identifies the LSB of the RAM code revision number.
Example:
Patch Release = v02.01.22
ROM Version = 02h
RAM Version MSB = 01h
RAM Version LSB = 22h
Table 4-8. Chip ID MSB
Subaddress
Default
08h
Read only
7
6
5
4
3
2
1
0
Chip ID MSB [7:0]
Chip ID MSB[7:0]
This register identifies the MSB of device ID. Value = 51h
Table 4-9. Chip ID LSB
Subaddress
Default
09h
Read only
7
6
5
4
3
2
1
0
Chip ID LSB [7:0]
Chip ID LSB [7:0]
This register identifies the LSB of device ID. This value equals 58h for TVP5158, 57h for TVP5157, and 56h for
TVP5156.
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Table 4-10. Video Standard Status
Subaddress
Default
0Ch
Read only
7
6
5
4
3
2
1
0
Autoswitch
Reserved
Video standard [2:0]
This register contains information about the detected video standard that the device is currently operating. When in autoswitch mode, this
register can be tested to determine which video standard as has been detected. See subaddress: 0Dh.
Autoswitch Mode
0
1
Single standard set
Autoswitch mode enabled
Video Standard [2:0]
00h
01h
02h
03h
04h
05h
06h
07h
Reserved
(M, J) NTSC
(B, D, G, H, I, N) PAL
(M) PAL
(Combination-N) PAL
NTSC 4.43
Reserved
PAL 60
Table 4-11. Video Standard Select
Subaddress
Default
0Dh
00h
7
6
5
4
3
2
1
0
Reserved
CVBS Standard [2:0]
The user can force the device to operate in a particular video standard mode by writing the appropriate value into this register. Changing
these bits causes some register settings to be reset to their defaults. See subaddress: 0Ch.
CVBS Standard [2:0]
00h
01h
02h
03h
04h
05h
06h
07h
CVBS Autoswitch mode (default)
(M, J) NTSC
(B, D, G, H, I, N) PAL
(M) PAL
(Combination-N) PAL
NTSC 4.43
Reserved
PAL 60
50
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Table 4-12. CVBS Autoswitch Mask
Subaddress
Default
0Eh
03h
7
6
5
4
3
2
1
0
Reserved
PAL 60
Reserved
NTSC 4.43
(Nc) PAL
(M) PAL
PAL
(M, J) NTSC
Autoswitch mode mask
Limits the video formats between which autoswitch is possible.
PAL 60
0
1
0
1
0
1
0
1
0
1
0
1
Autoswitch does not include PAL 60 (default)
Autoswitch includes PAL 60
NTSC 4.43
(Nc) PAL
(M) PAL
PAL
Autoswitch does not include NTSC 4.43 (default)
Autoswitch includes NTSC 4.43
Autoswitch does not include (Nc) PAL (default)
Autoswitch includes (Nc) PAL
Autoswitch does not include (M) PAL (default)
Autoswitch includes (M) PAL
Reserved
Autoswitch includes (B, D, G, H, I, N) PAL (default)
Reserved
(M, J) NTSC
Autoswitch includes (M, J) NTSC (default)
Table 4-13. Auto Contrast Mode
Subaddress
Default
0Fh
03h
7
6
5
4
3
2
1
0
Reserved
Auto Contrast Mode [1:0]
Auto Contrast Mode [1:0]
00h
01h
02h
03h
Enabled
Reserved
User Mode
Disabled (default)
Table 4-14. Luminance Brightness
Subaddress
Default
10h
80h
7
6
5
4
3
2
1
0
Brightness [7:0]
Brightness [7:0]
This register works for the luminance. See subaddress 12h.
0000 0000 0 (dark)
1000 0000 128 (default)
1111 1111 255 (bright)
The output black level relative to the nominal black level (64 out of 1024) as a function of the Brightness[7:0] setting is as follows:
Black Level = nominal_black_level + (MB + 1) × (Brightness[7:0] - 128)
Where MB is the brightness multiplier setting in the Brightness and Contrast Range Extender register at I2C subaddress 12h.
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Table 4-15. Luminance Contrast
Subaddress
Default
11h
80h
7
6
5
4
3
2
1
0
Contrast [7:0]
Contrast [7:0]
This register works for the luminance. See subaddress 12h.
0000 0000 0 (minimum contrast)
1000 0000 128 (default)
1111 1111 255 (maximum contrast)
The total luminance gain relative to the nominal luminance gain as a function of the Contrast [7:0] setting is as follows:
Luminance Gain = (nominal_luminance_gain) × [Contrast[7:0] / 64 / (2MC) + MC - 1]
Where MC is the contrast multiplier setting in the Brightness and Contrast Range Extender register at I2C subaddress 12h.
Table 4-16. Brightness and Contrast Range Extender
Subaddress
Default
12h
00h
7
6
5
4
3
2
1
0
Contrast
multiplier
Reserved
Brightness multiplier [3:0]
Contrast multiplier [4] (MC)
Increases the contrast control range.
0
1
2x contrast control range (default), Gain = n/64 – 1 where n is the contrast control and 64 ≤ n ≤255
Normal contrast control range, Gain = n/128 where n is the contrast control and 0 ≤ n ≤ 255
Brightness multiplier [3:0] (MB)
Increases the brightness control range from 1x to 16x.
0h 1x (default)
1h 2x
3h
7h
Fh
4x
8x
16x
NOTE: The brightness multiplier should be set to 3h for 8-bit outputs.
Table 4-17. Chrominance Saturation
Subaddress
Default
13h
80h
7
6
5
4
3
2
1
0
Saturation [7:0]
Saturation [7:0]
This register works for the chrominance.
0000 0000 0 (no color)
1000 0000 128 (default)
1111 1111 255 (maximum)
The total chrominance gain relative to the nominal chrominance gain as a function of the Saturation [7:0] setting is as follows:
Chrominance Gain = (nominal_chrominance_gain) × (Saturation[7:0] / 128)
52
Internal Control Registers
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Table 4-18. Chrominance Hue
Subaddress
Default
14h
80h
7
6
5
4
3
2
1
0
Hue [7:0]
Saturation [7:0]
This register works for the chrominance.
0000 0000 -180°
1000 0000 0° (default)
1111 1111 +180°
Table 4-19. Color Killer
Subaddress
Default
16h
10h
7
6
5
4
3
2
1
0
Reserved
Automatic color killer
Color killer threshold [4:0]
Automatic color killer
00
01
Automatic mode (default)
Reserved
Color killer enabled, The UV terminals are forced to a zero
color state.
10
11
Color killer disabled
Color killer threshold [4:0]:
Controls the upper and lower color killer hysteresis thresholds.
NTSC-M,J(1)(2)
PAL-B,D,G,H,I,M,N(1)(2)
Lower Threshold
Upper Threshold
1.4%
Lower Threshold
Upper Threshold
1.2%
0 0000
0 1000
1 0000
1 1000
1 1111
1.0%
3.0%
5.0%
7.0%
8.8%
0.8%
2.4%
4.0%
5.6%
7.0%
4.3%
3.5%
7.2%
5.8%
10.0%
8.0%
12.6%
10.0%
(1) Expressed as a percent of the nominal color burst amplitude (measured after front-end AGC).
(2) For proper color killer operation, the color PLL must be locked to the color burst frequency.
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Table 4-20. Luminance Processing Control 1
Subaddress
Default
18h
40h
7
6
5
4
3
2
1
0
NTSC_Ped
Reserved
Luminance signal delay [2:0]
NTSC_Ped
Specifies whether NTSC composite video inputs are compliant with NTSC-M or NTSC-J.
0
1
NTSC-M (714/286 ratio, w/ pedestal) - default
NTSC-J (714/286 ratio, w/o pedestal)
Luminance signal delay [2:0]
Luminance signal delays respect to chroma signal in 1x pixel clock increments.
011
010
001
000
111
110
101
100
3 pixel clocks delay
2 pixel clocks delay
1 pixel clocks delay
0 pixel clocks delay (default)
-1 pixel clocks delay
-2 pixel clocks delay
-3 pixel clocks delay
0 pixel clocks delay
Table 4-21. Luminance Processing Control 2
Subaddress
Default
19h
00h
7
6
5
4
3
2
1
0
Luma filter select [1:0]
Reserved
Peaking gain [1:0]
Trap filter select [1:0]
Luma filter selected [1:0]
00
01
10
11
Luminance adaptive comb enable (default)
Luminance adaptive comb disable (trap filter selected)
Luma comb/trap filter bypassed
Reserved
Peaking gain [1:0]
00
01
10
11
0 (default)
0.5
1
2
Trap filter select [1:0]
Selects one of the four trap filters to produce the luminance signal by removing the chrominance signal from the composite video
signal. The stop band of the chroma trap filter is centered at the chroma subcarrier frequency with the stop-band bandwidth
controlled by the two control bits.
Trap filter stop-band bandwidth (MHz)
Filter select [1:0]
NTSC ITU-R BT.601
1.2129
PAL ITU-R BT.601
1.2129
00 = (default)
01
10
11
0.8701
0.8701
0.7183
0.7383
0.5010
0.5010
54
Internal Control Registers
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Table 4-22. Power Control
Subaddress
Default
1Ah
00h
7
6
5
4
3
2
1
0
Pwd_ach4
Pwd_ach3
Pwd_ach2
Pwd_ach1
Pwd_vpll
Pwd_ref
Pwd_ofm_clk
Pwd_video
Pwd_ach4
Power down audio channel 4, active high
0
1
Normal operation (default)
Audio channel 4 power down
Pwd_ach3
Power down audio channel 3, active high
0
1
Normal operation (default)
Audio channel 3 power down
Pwd_ach2
Power down audio channel 2, active high
0
1
Normal operation (default)
Audio channel 2 power down
Pwd_ach1
Power down audio channel 1, active high
0
1
Normal operation (default)
Audio channel 1 power down
Pwd_vpll
Power down video PLL, active high
0
1
Normal operation (default)
Video PLL power down
Pwd_ref
Power down bandgap reference, active high
0
1
Normal operation (default)
Bandgap reference power down
Pwd_ofm_clk
Power down OFM clock, active high
0
1
Normal operation (default)
OFM clock power down
Pwd_video
Power down video channel corresponding to current decoder core, active high
0
1
Normal operation (default)
Power down video channel corresponding to current decoder core
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Table 4-23. Chrominance Processing Control 1
Subaddress
Default
1Bh
00h
7
6
5
4
3
2
1
0
Chroma
Reserved
Color PLL reset adaptive comb
enable
Reserved
Automatic color gain control [1:0]
Color PLL reset
0
1
Color subcarrier PLL not reset (default)
Color subcarrier PLL reset
Chrominance adaptive comb enable
This bit is effective on composite video only.
0
1
Enabled (default)
Disabled
Automatic color gain control (ACGC) [1:0]
00
01
10
11
ACGC enabled (default)
Reserved
ACGC disabled, ACGC set to the nominal value
ACGC frozen to the previously set value
Table 4-24. Chrominance Processing Control 2
Subaddress
Default
1Ch
0Ch
7
6
5
4
3
2
1
0
PAL
compensation
Reserved
WCF
Chrominance filter select [1:0]
PAL compensation
This bit is not effective to NTSC mode.
0
1
Disabled
Enabled (default)
Wideband chroma LPF filter (WCF)
0
1
Disabled
Enabled (default)
Chrominance filter select [1:0]
This register trades chroma bandwidth for less false color.
00
01
10
11
Disabled (default)
Notch 1
Notch 2
Notch 3
56
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Table 4-25. AGC Gain Status
Subaddress
Default
20h-21h
Read Only
Subaddress
20h
7
6
5
4
3
2
1
0
Fine Gain [7:0]
21h
Reserved
Fine Gain [13:8]
These AGC gain status registers are updated automatically when the AGC is enabled; in manual gain control mode these register values
are not updated.
Because this register is a multi-byte register, it is necessary to "capture" the setting into the register to ensure that the value is not updated
between reading the lower and upper bytes. To cause this register to "capture" the current settings bit 0 of I2C register 24h (Status
Request) should be set to a 1. After the internal processor has updated this register, bit 0 of register 24h is cleared, indicating that both
bytes of the AGC gain status register have been updated and can be read. Either byte may be read first, because no further update occurs
until bit 0 of 24h is set to 1 again.
Table 4-26. Back-End AGC Status
Subaddress
Default
23h
Read Only
7
6
5
4
3
2
1
0
Gain [7:0]
Current back-end AGC ratio = Gain/128.
Table 4-27. Status Request
Subaddress
Default
24h
00h
7
6
5
4
3
2
1
0
Reserved
Capture
Capture
Setting a 1 in this register causes the inter processor to capture the current settings of the AGC status, noise measurement, and
the vertical line count registers. Because this capture is not immediate, it is necessary to check for completion of the capture by
reading the "capture" bit repeatedly after setting it and waiting for it to be cleared by the internal processor. After the "capture" bit is
0, the AGC status, noise measurement, and vertical line counters (20h/21h, 94h/95h, and A2h/A3h) have been updated, and can
be safely read in any order.
Table 4-28. AFE Gain Control
Subaddress
Default
25h
F5h
7
6
5
4
3
2
1
0
Reserved
ALC
Reserved
AGC
Reserved
For future compatibility, all reserved bits must be set to logic 1.
ALC
Active-high automatic level control (ALC) enable
0
1
ALC disabled (manual level control)
ALC enabled (default)
AGC
Active-high automatic gain control (AGC) enable
0
1
AGC disabled (manual gain control)
AGC enabled (default)
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Table 4-29. Luma ALC Freeze Upper Threshold
Subaddress
Default
26h
00h
7
6
5
4
3
2
1
0
Luma ALC freeze [7:0]
Upper hysteresis threshold for luma ALC freeze function. The lower hysteresis threshold for the ALC freeze function is fixed at 1 count out
of 4096. Setting the upper threshold to 00h (default condition) disables the ALC freeze function.
Table 4-30. Chroma ALC Freeze Upper Threshold
Subaddress
Default
27h
00h
7
6
5
4
3
2
1
0
Chroma ALC freeze [7:0]
Upper hysteresis threshold for chroma ALC freeze function. The lower hysteresis threshold for the ALC freeze function is fixed at 1 count
out of 4096. Setting the upper threshold to 00h (default condition) disables the ALC freeze function. Recommend a setting of 02h or greater
when enabled.
Table 4-31. AGC Increment Speed
Subaddress
Default
29h
06h
7
6
5
4
3
2
1
0
Reserved
AGC increment speed [3:0]
AGC increment speed
Controls the filter coefficient of the first-order, recursive automatic gain control (AGC) algorithm whenever incrementing the gain.
000
110
111
0 (fastest)
6 (default)
7 (slowest)
Table 4-32. AGC Increment Delay
Subaddress
Default
2Ah
1Eh
7
6
5
4
3
2
1
0
AGC increment delay [7:0]
AGC increment delay [7:0]
Number of frames to delay gain increments. Also see AGC decrement delay at subaddress 2Ch.
00000000
0
00011110 30 frames (default)
11111111 255 frames
58
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Table 4-33. AGC Decrement Speed
Subaddress
Default
2Bh
04h
7
6
5
4
3
2
1
0
Reserved
AGC decrement speed [2:0]
AGC decrement speed
Controls the filter coefficient of the first-order recursive automatic gain control (AGC) algorithm when decrementing the gain.
NOTE: This register affects the decrement speed only when the amplitude reference used by the AGC is either the composite peak
or the luma peak.
Also see AGC increment speed at subaddress 29h.
111
110
000
7 (slowest)
6 (default)
0 (fastest)
Table 4-34. AGC Decrement Delay
Subaddress
Default
2Ch
00h
7
6
5
4
3
2
1
0
AGC decrement delay [7:0]
AGC decrement delay [7:0]
Number of frames to delay gain decrements.
NOTE: This register affects the decrement delay only when the amplitude reference used by the AGC is either the composite peak
or the luma peak.
Also see AGC increment delay at subaddress 2Ah.
111
110
000
0
30 (default)
255
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Table 4-35. AGC White Peak Processing
Subaddress
Default
2Dh
F2h
7
6
5
4
3
2
1
0
Composite
peak
Luma peak A
Reserved
Color burst A
Sync height A
Luma peak B
Color burst B
Sync height B
If all four bits of the lower nibble are set to logic 1 (that is, no amplitude reference selected), then the front-end analog and digital gains are
automatically set to nominal values.
If all four bits of the upper nibble are set to logic 1 (that is, no amplitude reference selected), then the back-end gain is set automatically to
unity. If the input sync height is greater than 100% and the AGC-adjusted output video amplitude becomes less than 100%, then the
back-end scale factor attempts to increase the contrast in the back-end to restore the video amplitude to 100%.
Luma peak A
Use of the luma peak as a video amplitude reference for the back-end feed-forward type AGC algorithm
0
1
Enabled (default)
Disabled
Color burst A
Use of the color burst amplitude as a video amplitude reference for the back-end
0
1
Enabled (default)
Disabled
Sync height A
Use of the sync-height as a video amplitude reference for the back-end feed-forward type AGC algorithm
0
1
Enabled (default)
Disabled
Luma peak B
Use of the luma peak as a video amplitude reference for front-end feedback type AGC algorithm
0
Enabled (default)
Disabled
1
Composite peak
Use of the composite peak as a video amplitude reference for front-end feedback type AGC algorithm
0
1
Enabled (default)
Disabled
Color burst B
Use of the color burst amplitude as a video amplitude reference for front-end feedback type AGC algorithm
0
1
Enabled (default)
Disabled
Sync height B
Use of the sync-height as a video amplitude reference for front-end feedback type AGC algorithm
0
1
Enabled (default)
Disabled
60
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Table 4-36. Back-End AGC Control
Subaddress
Default
2Eh
08h
7
6
5
4
3
1
2
1
0
Reserved
Peak
Color
Sync
This register allows disabling the back-end AGC when the front-end AGC uses specific amplitude references (sync-height, color burst or
composite peak) to decrement the front-end gain. For example, writing 09h to this register disables the back-end AGC whenever the
front-end AGC uses the sync-height to decrement the front-end gain.
Peak
Disables back-end AGC when the front-end AGC uses the composite peak as an amplitude reference.
0
1
Enabled (default)
Disabled
Color
Sync
Disables back-end AGC when the front-end AGC uses the color burst as an amplitude reference.
0
1
Enabled (default)
Disabled
Disables back-end AGC when the front-end AGC uses the sync height as an amplitude reference.
0
1
Enabled (default)
Disabled
Table 4-37. AFE Fine Gain
Subaddress
Default
34h-35h
086Ah
Subaddress
34h
7
6
5
4
3
2
1
0
FGAIN [7:0]
35h
Reserved
FGAIN [13:8]
FGAIN [13:0]
This fine gain applies to CVBS. Fine Gain = (1/2048) × FGAIN where 0 ≤ FGAIN ≤ 16383. This register works only in manual gain
control mode. When AGC is active, writing to any value is ignored.
00 0000 0000 0000 to
Reserved
00 0011 1111 1111
00 0100 0000 0000
00 1000 0000 0000
00 1000 0110 1010
00 1100 0000 0000
11 1111 1111 1111
0.5
1
1.052 (default)
1.5
7.9995
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Table 4-38. AVID Start Pixel
Subaddress
Default
48h-49h
007Ah/0084h
Subaddress
48h
7
6
5
4
3
2
1
0
AVID start [7:0]
AVID active
49h
Reserved
Reserved
AVID start [9:8]
AVID start [9:0]
AVID start pixel number, this is a absolute pixel location from HS start pixel 0.
The TVP5158 updates the AVID start only when the AVID start MSB byte is written to. AVID start pixel register also controls the
position of SAV code. If these registers are modified, then the TVP5158 retains the values for each video standard until the device
is reset. The values for a particular video standard should be set by forcing the TVP5158 to the desired video standard first using
register 0Dh then setting this register. This should be repeated for each video standard where the default values need to be
changed.
AVID active
0
AVID out active in VBLK (default)
AVID out inactive in VBLK
1
Table 4-39. AVID Pixel Width
Subaddress
Default
4Ah-4Bh
02D0h
Subaddress
4Ah
7
6
5
4
3
2
1
0
AVID Width [7:0]
4Bh
Reserved
AVID Width [9:8]
AVID Width [9:0]
AVID pixel width. The number of pixels width of active video must be an even number. This is an absolute pixel location from HS
start pixel 0.
The TVP5158 updates the AVID pixel width only when the AVID pixel width MSB byte is written to. AVID Pixel Width register also
controls the position of EAV code. If these registers are modified, then the TVP5158 retains the values for each video standard
until the device is reset. The values for a particular video standard should be set by forcing the TVP5158 to the desired video
standard first using register 0Dh then setting this register. This should be repeated for each video standard where the default
values need to be changed.
Table 4-40. Noise Reduction Max Noise
Subaddress
Default
5Ch
28h
7
6
5
4
3
2
1
0
Reserved
NR_Max_Noise [6:0]
NR_Max_Noise [6:0]
User-defined maximum noise level
0010 1000 40 (default)
62
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Table 4-41. Noise Reduction Control
Subaddress
Default
5Dh
09h
7
6
5
4
3
2
1
0
NR_Color_
Killer_En
Block_Width_
UV
Reserved
Block_Width_Y Test_ Bypass
NR_ Bypass
NR_Color_Killer_En
Noise reduction color killer enabled
0
Disabled (default)
Enabled
1
Block_Width_UV
Number of UV pixel values which the algorithm uses to generate the noise average.
0
128 pixels
1
256 pixels (default)
Block_Width_Y
Number of Y pixel values which the algorithm uses to generate the noise average.
0
1
256 pixels (default)
512 pixels
Test_Bypass
Test mode bypass. This test bypass mode bypasses the Noise Reduction module completely via hard wires and has zero delay for
processing.
0
1
Bypass disabled (default)
Bypass enabled
NR_Bypass
Noise reduction module bypass. The noise reduction module has a bypass capability which enables it to pass through the incoming
data during the output active video period, while matching the delay in operation mode.
0
1
Bypass disabled
Bypass enabled (default)
Table 4-42. Noise Reduction Noise Filter Beta
Subaddress
Default
5Eh-5Fh
0330h
Subaddress
5Eh
7
6
5
4
3
2
1
0
NR_NoiseFilter [7:0]
5Fh
Reserved
NR_NoiseFilter [9:8]
NR_NoiseFilter [9:0]
Noise reduction noise filter setting
0000 0011 0011 0000
816 (default)
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Table 4-43. Operation Mode Control
Subaddress
Default
60h
00h
7
6
5
4
3
2
1
0
V-PLL free run
Reserved
H-PLL Response Time
V-bit control
Freeze C-PLL
Reserved
V-PLL free run mode
0
1
Disabled (default)
Enabled
H-PLL Response Time
When in the Normal mode, the horizontal PLL (H-PLL) response time is set to its slowest setting. This mode improves noise
immunity and provides a more stable output line frequency for standard TV signal sources (for example, TV tuners, DVD players,
video surveillance cameras, etc.).
When in the Fast mode, the H-PLL response time is set to its fastest setting. This mode enables the H-PLL to respond more
quickly to large variations in the horizontal timing (for example, VCR head switching intervals). This mode is recommended for
VCRs and also cameras locked to the AC power-line frequency.
When in the Adaptive mode, the H-PLL response time is automatically adjusted based on the measured horizontal phase error. In
this mode, the H-PLL response time typically approaches its slowest setting for most standard TV signal sources and approaches
its fastest setting for most VCR signal sources.
00
01
10
11
Adaptive (default)
Reserved
Fast
Normal
V-bit control mode
0
Vertical blanking interval remains constant as total number of lines per frame varies (default)
1
Active video interval remains constant as total number of lines per frame varies
Freeze C-PLL
0
1
Normal operation (default)
Freeze color PLL
Table 4-44. Color PLL Speed Control
Subaddress
Default
61h
09h
7
6
5
4
3
2
1
0
Reserved
CPLL speed [3:0]
CPLL speed [3:0]
Color PLL speed control
0000
to
Reserved
1000
1001
1010
1011
9: Faster (default)
10
11: Slower
1100
to
Reserved
1111
64
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Table 4-45. Sync Height Low Threshold
Subaddress
Default
7Ch
02h
7
6
5
4
3
2
1
1
1
0
0
0
VSync upper thres [7:0]
Lower hysteresis threshold for vertical sync-height detection (value/32×target sync height).
Table 4-46. Sync Height High Threshold
Subaddress
Default
7Dh
08h
7
6
5
4
3
2
VSync upper thres [7:0]
Upper hysteresis threshold for vertical sync-height detection (value/32×target sync height).
Table 4-47. Clear Lost Lock Detect
Subaddress
Default
81h
00h
7
6
5
4
3
2
Clear lost lock
detect
Reserved
Clear lost lock detect
Clear bit 4 (lost lock detect) in the status 1 register at subaddress 00h
0
1
No effect (default)
Clears bit 4 in the status 1 register (00h)
Table 4-48. VSYNC Filter Shift
Subaddress
Default
85h
03h
7
6
5
4
3
2
1
0
Reserved
VSYNC filter shift [1:0]
VSYNC filter shift [1:0]
Used for adaptation of VPLL time constant
00
01
10
11
0 (fast)
1
2
3 (slow)
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Table 4-49. 656 Version/F-bit Control
Subaddress
Default
87h
00h
7
6
5
4
3
2
1
0
Reserved
656 version
F-control
656 version
0
Timing confirms to ITU-R BT.656-4 specifications (default)
Timing confirms to ITU-R BT.656-3 specifications
1
F-control
0
1
Odd field causes 0 → 1 transition in F-bit when in TVP5146 F/V mode (see register 88h)
Even field causes 0 → 1 transition in F-bit when in TVP5146 F/V mode (see register 88h)
66
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Table 4-50. F-Bit and V-Bit Decode Control
Subaddress
Default
88h
03h
7
6
5
4
3
2
1
0
Reserved
VPLL
Adaptive
Reserved
F-Mode [1:0]
VPLL
VPLL time constant control
0
1
VPLL adapts time constants to input signal
VPLL time constants fixed
Adaptive
0
1
Enable F and V bit adaptation to detected lines per frame
Disable F and V bit adaptation to detected lines per frame
F-Mode [1:0]
F-bit control mode
Auto: If lines per frame is standard decode F and V bits as per 656 standard from line count else decode F bit from
VSYNC input and set V bit = 0
00
01
10
11
Decode F and V from input syncs
Reserved
Always decode F and V bits from line count (TVP5146 compatible)
This register is used in conjunction with register 89h as shown:
Reg 88h
Reg 89h
Standard LPF
Non-standard LPF
Mode
Bit 1
Bit 0
0
Bit 3
Bit 2
0
F
V
F
V
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Reserved
TVP5158
TVP5158
Reserved
Reserved
Reserved
656
Reserved
656
Reserved
Toggle
Reserved
Switch9
0
0
1
0
0
656
656
Pulse
0
1
Reserved
Reserved
656
Reserved
Reserved
656
Reserved
Reserved
Toggle
Reserved
Reserved
Switch9
0
1
0
1
1
1
0
656
656
Pulse
1
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
1
0
0
0
1
Even = 1
Odd = toggle
1
1
0
0
TVP5146
656
656
Switch
1
1
1
1
1
1
0
1
1
1
0
1
TVP5146
TVP5146
Reserved
656
656
656
656
Toggle
Pulse
Switch
Switch
Reserved
Reserved
Reserved
Reserved
656
ITU-R BT.656 standard
Toggles from field to field
Toggle
Pulse
Pulses low for 1 line prior to field transition
Switch
V bit switches high before the F bit transition and low after the F bit transition
V bit switches high 1 line prior to F bit transition, then low after 9 lines
Not used
Switch9
Reserved
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Table 4-51. F-Bit and V-Bit Control
Subaddress
Default
89h
16h
7
6
5
4
3
2
1
0
Rabbit
Reserved
Fast lock
F and V [1:0]
Phase Det
HPLL
Rabbit
Enable "rabbit ear"
0
1
Disabled (default)
Enabled
Fast lock
Enable fast lock where vertical PLL is reset and a 2 second timer is initialized when vertical lock is lost; during timeout the detected
input VS is output.
0
1
Disabled
Enabled (default)
F and V [1:0]
F and V control bits are only enabled for F-bit control mode 01 and 10 (see register 88h)
F and V Lines Per Frame F Bit
V Bit
Standard
ITU-R BT.656
Forced to 1
Toggles
ITU-R BT.656
00
Non standard-even
Non standard-odd
Standard
Switch at field boundary
Switch at field boundary
ITU-R BT.656
ITU-R BT.656
Toggles
01 (default)
10
Non standard
Standard
Switch at field boundary
ITU-R BT.656
ITU-R BT.656
Pulsed mode
Non standard
Reserved
Switch at field boundary
11
Phase Det
Enable integral-window phase detector
0
1
Disabled
Enabled (default)
HPLL
Enable horizontal PLL to free run
0
1
Disabled (default)
Enabled
Table 4-52. Output Timing Delay
Subaddress
Default
8Ch
00h
7
6
5
4
3
2
1
0
Output timing delay [7:0]
Output timing delay [7:0]
Adjusts delay for AVID start and stop.
0000 1111
0000 0001
0000 0000
1111 1111
1111 0000
+15 pixel delay
+1 pixel delay
0 pixel delay (default)
-1 pixel delay
-16 pixel delay
68
Internal Control Registers
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Table 4-53. Auto Contrast User Table Index
Subaddress
Default
8Fh
04h
7
6
5
4
3
2
1
0
Reserved
AC_User_Mode_Table [2:0]
Reserved
AC_User_Mode_Table [2:0]
User table selection for auto contrast user mode when the register 0Fh sets to 02h.
000
001
010
011
100
101
Brighter 1
Brighter 2
Brighter 3 (Brightest)
Darker 1
Darker 2
Darker 3 (Darkest)
110 to
111
Reserved
Table 4-54. Blue Screen Y Control
Subaddress
Default
90h
10h
7
6
5
4
3
2
1
0
Y value [9:2]
The Y value of the color screen output when enabled by bit 2 or 3 of the Output Formatter 2 register is programmable using a 10-bit value.
The 8 MSBs, bits [9:2], are represented in this register. The remaining two LSB are found in the Blue Screen LSB register. The default color
screen output is black.
The following table shows the values for registers 90h, 91h, 92h and 93h for several different screen colors.
Screen Color
Black (default)
Blue
Reg 90h
10h
Reg 91h
80h
Reg 92h
80h
Reg 93h
00h
29h
F0h
6Eh
00h
Green
91h
36h
22h
00h
Cyan
AAh
51h
A6h
10h
00h
Red
5Ah
F0h
00h
Magenta
Yellow
6Ah
CAh
10h
DEh
92h
00h
D2h
EBh
00h
White
80h
80h
00h
NOTE: The blue screen output mode can be enabled or disabled using bits 3:2 of I2C register A9h.
Table 4-55. Blue Screen Cb Control
Subaddress
Default
91h
80h
7
6
5
4
3
2
1
0
Cb value [9:2]
The Cb value of the color screen output when enabled by bit 2 or 3 of the Output Formatter 2 register is programmable using a 10-bit value.
The 8 MSBs, bits[9:2], are represented in this register. The remaining two LSB are found in the Blue screen LSB register. The default color
screen output is black. See Table 4-54 for example colors.
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Table 4-56. Blue Screen Cr Control
Subaddress
Default
92h
80h
7
6
5
4
3
2
1
0
Cr value [9:2]
The Cr value of the color screen output when enabled by bit 2 or 3 of the Output Formatter 2 register is programmable using a 10-bit value.
The 8 MSBs, bits[9:2], are represented in this register. The remaining two LSB are found in the Blue Screen LSB register. The default color
screen output is black. See Table 4-54 for example colors.
Table 4-57. Blue Screen LSB Control
Subaddress
Default
93h
00h
7
6
5
4
3
2
1
0
Reserved
Y value LSB [1:0]
Cb value LSB [1:0]
Cr value LSB [1:0]
The two LSBs for the Blue screen Y, Cb, and Cr values are represented in this register. See Table 4-54 for example colors.
Table 4-58. Noise Measurement
Subaddress
Default
94h-95h
Read Only
Subaddress
94h
7
6
5
4
3
2
1
0
Noise Measurement [7:0]
Noise Measurement [15:8]
95h
Noise measurement [15:0]
Used by the weak signal detection algorithm.
Because this register is a double-byte register, it is necessary to "capture" the setting into the register to ensure that the value is
not updated between reading the lower and upper bytes. To cause this register to "capture" the current settings bit 0 of I2C register
24h (status request) should be set to a 1. After the internal processor has updated this register, bit 0 of register 24h is cleared,
indicating that both bytes of the noise measurement register have been updated and can be read. Either byte may be read first,
because no further update occurs until bit 0 of 24h is set to 1 again.
Table 4-59. Weak Signal High Threshold
Subaddress
Default
96h
60h
7
6
5
4
3
2
1
0
Level [7:0]
This register controls the upper threshold of the noise measurement used to determine whether the input signal should be considered a
weak signal.
Table 4-60. Weak Signal Low Threshold
Subaddress
Default
97h
50h
7
6
5
4
3
2
1
0
Level [7:0]
This register controls the lower threshold of the noise measurement used to determine whether the input signal should be considered a
weak signal.
70
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Table 4-61. Noise Reduction Y/U/V T0
Subaddress
Default
9Eh
0Ah
9Fh
A0h
BCh
BCh
Subaddress
9Eh
7
6
5
4
3
2
1
0
Noise Reduction Y T0 [7:0]
Noise Reduction U T0 [7:0]
Noise Reduction V T0 [7:0]
9Fh
A0h
These registers control how much noise filtering is done for Y/U/V channels. The higher the value is, the more noise filtering at the expense
of video details.
Table 4-62. Vertical Line Count Status
Subaddress
Default
A2h-A3h
Read Only
Subaddress
A2h
7
6
5
4
3
2
1
0
Vertical line [7:0]
A3h
Reserved
Vertical line [9:8]
This status register is only updated when a status request is initiated via bit 0 of subaddress 24h.
Vertical line [9:0] represent the detected a total number of lines from the previous frame. This can be used with nonstandard video signals
such as a VCR in trick mode to synchronize downstream video circuitry.
NOTE: This register is not double buffered.
Because this register is a double-byte register, it is necessary to "capture" the setting into the register to ensure that the value is not
updated between reading the lower and upper bytes. To cause this register to "capture" the current settings bit 0 of I2C register 24h (Status
Request) should be set to a 1. After the internal processor has updated this register, bit 0 of register 24h is cleared, indicating that both
bytes of the vertical line count register have been updated and can be read. Either byte may be read first, because no further update occurs
until bit 0 of 24h is set to 1 again.
Table 4-63. Output Formatter Control 1
Subaddress
Default
A8h
44h
7
6
5
4
3
2
1
0
YCbCr code
range
Reserved
CbCr range
Reserved
This register should be written to all four video decoder cores.
YCbCr output code range
0
1
ITU-R BT.601 coding range (Y ranges from 16 to 235. Cb and Cr range from 16 to 240.)
Extended coding range (Y, Cb and Cr range from 1 to 254.) (default)
CbCr range format
0
1
Offset binary code (2's complement + 512) (default)
Straight binary code (2's complement)
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Table 4-64. Output Formatter Control 2
Subaddress
Default
A9h
40h
7
6
5
4
3
2
1
0
Reserved
Blue screen output [1:0]
Reserved
This register should be written to all four video decoder cores.
Blue screen output [1:0]
Fully programmable color of "blue screen" to support clean input/channel switching. When enabled, in case of lost lock, or when
forced, the TVP5158 waits until the end of the current frame, then switches the output data to a programmable color. Once
displaying the "blue screen", the inputs can be switched without causing snow or noise to be displayed on the digital output data.
Once the inputs have settled the "blue screen" can be disabled, where the TVP5158 then waits until the end of the current video
frame before re-enabling the video stream data to the output ports.
00
01
10
11
Normal operation (default)
Blue screen out when TVP5158 detects lost lock
Force Blue screen out
Reserved
Table 4-65. Interrupt Control
Subaddress
Default
ADh
00h
7
6
5
4
3
2
1
0
Int_Pol
Int_Type
Reserved
Int_Pol
Interrupt polarity
0
1
Active low (default)
Active high (do not use with open-drain output)
NOTE: Active-high output should be used only when push-pull output type is selected (Int_Type = 1).
Int_Type
Interrupt output type
0
Open-drain output (default)
Push-pull output
1
NOTE: An external pullup resistor is required when open drain output is selected (Int Type = 0).
Table 4-66. Embedded Sync Offset Control 1
Subaddress
Default
AEh
01h
7
6
5
4
3
2
1
0
Offset [7:0]
Offset [7:0]
This register allows the line position of the embedded F and V bit signals to be offset from the 656 standard positions. This register
is only applicable to input video signals with a standard number of lines per frame.
01111111
⋮
+127 lines
00000001
00000000
11111111
⋮
+1 line (default)
0 line
-1 line
10000000
-128 lines
72
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Table 4-67. Embedded Sync Offset Control 2
Subaddress
Default
AFh
00h
7
6
5
4
3
2
1
0
Offset [7:0]
Offset [7:0]
This register allows the line relationship between the embedded F and V bit signals to be offset from the 656 standard positions,
and moves F relative to V. This register is only applicable to input video signals with a standard number of lines per frame.
0000 0010
⋮
+2 lines (maximum setting for NTSC and PAL)
0000 0001
0000 0000
1111 1111
⋮
+1 line
0 line
-1 line
1111 0001
⋮
-15 lines (minimum setting for NTSC)
-21 lines (minimum setting for PAL)
1110 1011
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Table 4-68. AVD Output Control 1
Subaddress
Default
B0h
00h
7
6
5
4
3
2
1
0
Interleave_mode
Channel_Mux_Number
Output_ type
VCS_ID
Video_Res_Sel
This register should be written to all four video decoder cores.
Interleave_mode
Interleave mode for multi-channel formats
00
01
10
11
Non-interleaved (a.k.a. 1-Ch mode) – (default)
Pixel-interleaved mode (2-Ch and 4-Ch only)
Line-interleaved mode
Line-interleaved, hybrid mode (adds 1-Ch D1 to selected 4-Ch Half-D1, 4-Ch CIF or 8-Ch CIF format)
Channel_Mux_Number
Number of time-multiplexed channels
00
01
10
1-Ch (reserved)
2-Ch
4-Ch (or 4-Ch Half-D1 or CIF + 1-Ch D1 for line-interleaved, hybrid mode)
8-Ch cascade (format depends on VCS_ID, line-interleaved mode only)
•
Line-interleaved mode
–
–
1st stage: 8-Ch Half-D1 or 8-Ch CIF (video port A)
2nd stage: 4-Ch Half-D1 or 4-Ch CIF (video port A)
11
•
Line-interleaved, hybrid mode
–
–
1st stage: 8-Ch CIF + 1-Ch D1 (video port A)
2nd stage: 4-Ch CIF (video port A) and 1-Ch D1 (video port B)
Output_type
Output interface type
0
1
8-bit ITU-R BT.656 interface (default)
16-bit ITU-R BT.601 interface (4-Ch D1 and 4-Ch Half-D1 line-interleaved modes only)
VCS_ID
Video cascade stage ID. Set to 0 for normal operation. For line-interleaved mode only.
0
1
1st stage (channels 1 to 4) (default)
2nd stage (channels 5 to 8)
Video_Res_Sel
Video resolution select. Effects multi-channel OFM only.
00
01
10
11
D1 (default)
Reserved
Half-D1
CIF
74
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Table 4-69. AVD Output Control 2
Subaddress
Default
B1h
10h
7
6
5
4
3
2
1
0
Chan_ID_
SAVEAV_En
Chan_ID_
Blank_En
Video_Det_
SAVEAV_En
LLC_En
Line_Crop_En
Quan_Ctrl
Line_ID_Ctrl
This register should be written to all four video decoder cores.
LLC_En
Line-locked clock enable, active high. For non-interleaved mode only. For use with Port A only. For D1 resolution only.
0
Line-locked clock disabled (default)
Line-locked clock enabled
1
Line_ Crop_En
AVD line cropping enable, active high. Effects both scaled and unscaled AVD outputs.
0
1
Cropping disabled (unscaled: 720 pixels/line, down-scaled: 360 pixels/line) – (default)
Cropping enabled (unscaled: 704 pixels/line, down-scaled: 352 pixels/line)
Quan_Ctrl
10-bit to 8-bit quantization control. Dithering algorithm based on truncation error from previous pixel.
00
Enable simple truncation
Enable dithering (default)
Enable simple rounding
Reserved
01
10
11
Line_ID_Ctrl
Line ID control. For line-interleaved mode only.
0
1
Line ID continues counting through the vertical blanking interval - (default)
Line ID holds the terminal count from the end of active video through the vertical blanking interval
Chan_ID_SAVEAV_En
Channel ID inserted in SAV/EAV codes enable, active high. For pixel-interleaved mode only. Always disabled for
non-interleaved and line-interleaved modes.
0
1
Disabled (default)
Enabled
Chan_ID_Blank_En
Channel ID inserted in blanking level enable, active high. For pixel-interleaved mode only. Always disabled for non-interleaved and
line-interleaved modes.
0
1
Disabled (default)
Enabled
Video_Det_SAVEAV_En
Video detection status inserted in SAV/EAV codes enable, active high. For non-interleaved and pixel-interleaved
modes. Always enabled for line-interleaved mode.
0
1
VDET insertion disabled (default)
VDET insertion enabled
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Table 4-70. OFM Mode Control
Subaddress
Default
B2h
20h
7
6
5
4
3
2
1
0
Video_Port_B_
En
Out_CLK_
Freq_Ctl
Out_CLK_
Pol_Sel
Out_CLK_
Freq_Sel
Out_CLK_N_E
n
OSC_OUT_En
Out_CLK_P_En
Video_Port_En
This register only needs to be written to video decoder core 0.
Video_Port_B_En
Video port B output enable for 6-Ch Half-D1 (2nd stage), active high
0
1
Video Port B disabled (default)
Video Port B enabled
Out_CLK_Freq_Ctl
Output clock frequency control for 4-Ch Half-D1 + 1-Ch D1 and 8-Ch CIF + 1-Ch D1 line-interleaved, hybrid output formats only.
Affects both OCLK_P and OCLK_N.
0
108 MHz (default)
81 MHz
1
OSC_OUT_En
Oscillator output enable, active high
0
1
OSC_OUT disabled
OSC_OUT enabled (default)
Out_CLK_Pol_Sel
Output clock polarity select. Affects both OCLK_P and OCLK_N.
0
1
Non-inverted (default)
Inverted
Out_CLK_Freq_Sel
Output clock frequency select for 2-ch pixel-interleaved mode only. Affects both OCLK_P and OCLK_N.
0
54 MHz (default)
27 MHz
1
Out_CLK_P_En
Output data clock+ (OCLK_P) enable, active high
0
OCLK_P disabled (default)
OCLK_P enabled
1
Out_CLK_N_En
Output data clock- (OCLK_N) enable, active high
0
OCLK_N disabled (default)
1
OCLK_N enabled (for 2-Ch mode only)
Video_Port_En
Video port output enable, active high
0
1
All four video ports disabled (default)
All video ports required for selected output format enabled
76
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Table 4-71. OFM Channel Select 1
Subaddress
Default
B3h
E4h
7
6
5
4
3
2
1
0
Chan_Sel_Port_D
Chan_Sel_Port_C
Chan_Sel_Port_B
Chan_Sel_Port_A
This register only needs to be written to video decoder core 0. OFM channel select by video port in 1-Ch mode.
Chan_Sel_Port_D
Channel select for port D
00
01
10
11
Ch 1
Ch 2
Ch 3
Ch 4 (default)
Chan_Sel_Port_C
Channel select for port C
00
01
10
11
Ch 1
Ch 2
Ch 3 (default)
Ch 4
Chan_Sel_Port_B
Channel select for port B
00
01
10
11
Ch 1
Ch 2 (default)
Ch 3
Ch 4
Chan_Sel_Port_A
Channel select for port A
00
01
10
11
Ch 1 (default)
Ch 2
Ch 3
Ch 4
NOTE: Each video port must be set to a different channel.
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Table 4-72. OFM Channel Select 2
Subaddress
Default
B4h
E4h
7
6
5
4
3
2
1
0
2nd_Chan_Sel_Port_B
1st_Chan_Sel_Port_B
2nd_Chan_Sel_Port_A
1st_Chan_Sel_Port_A
This register only needs to be written to video decoder core 0. OFM channel select by video port in 2-Ch mode.
2nd_Chan_Sel_Port_B
Second channel select for port B
00
01
10
11
Ch 1
Ch 2
Ch 3
Ch 4 (default)
1st_Chan_Sel_Port_B
First channel select for port B
00 Ch 1
01 Ch 2
10
11
Ch 3 (default)
Ch 4
2nd_Chan_Sel_Port_A
Second channel select for port A
00 Ch 1
01 Ch 2 (default)
10
11
Ch 3
Ch 4
1st_Chan_Sel_Port_A
First channel select for port A
00
01
10
11
Ch 1 (default)
Ch 2
Ch 3
Ch 4
NOTE: Each video port must be set to a different channel.
Table 4-73. OFM Channel Select 3
Subaddress
Default
B5h
00h
7
6
5
4
3
2
1
0
Reserved
Hybrid_Chan_Sel [2:0]
This register only needs to be written to video decoder core 0.
Hybrid_Chan_Sel [2:0]
OFM channel select for 1-Ch D1 channel in video cascade mode and hybrid format mode.
000
001
010
011
100
101
110
111
Ch 1 (default)
Ch 2
Ch 3
Ch 4
Cascade input from Port C (for video cascade 1st stage only)
Reserved
Reserved
Reserved
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Table 4-74. OFM Super-Frame Size
Subaddress
Default
B6h-B7h
041Bh
Subaddress
B6h
7
6
5
4
3
2
1
0
Super_Frame_Size [7:0]
Ctrl_Mode [1:0]
B7h
Reserved
Super_Frame_Size [11:8]
These registers write to decoder core 0 only.
Ctrl_Mode [1:0]
Super-frame size control mode
00
01
10
11
Super-frame size based on 525-line standard (default)
Super-frame size based on 625-line standard
Reserved
Super-frame size based on manual setting (see subaddress B6h/B7h)
Super_Frame_Size [11:0]
Total number of lines per super-frame. For line-interleaved mode only.
0100 0001 1011 1051 (default)
NOTE: Has no effect on port B in the video cascade interface.
Table 4-75. OFM EAV2SAV Duration
Subaddress
Default
B8h-B9h
0040h
Subaddress
B8h
7
6
5
4
3
2
1
0
OFM_EAV2SAV_Duration [7:0]
EAV2SAV_
OFM_EAV2SAV_ Duration
[9:8]
B9h
Horizontal_Freq_Tol
Duration_
Mode
Reserved
These registers only need to be written to video decoder core 0.
Horizontal_Freq_Tol
Nominal horizontal frequency tolerance (%). Only has an affect when bit 4 is set to 0.
000
001
010
011
100
101
110
111
0.5% (longest EAV2SAV duration) (default)
1.0%
1.5%
2.0%
2.5%
3.0%
3.5%
4.0% (shortest EAV2SAV duration)
EAV2SAV_Duration_Mode
EAV2SAV duration control mode.
0
1
EAV2SAV duration automatically controlled
EAV2SAV duration based on manual setting (see subaddress B8h/B9h)
OFM_EAV2SAV_Duration [9:0]
EAV2SAV duration in OCLK_P clock cycles. For non-interleaved and line-interleaved modes.
00 0100 0000 64 (default)
NOTE
See result of automatic EAV2SAV duration algorithm at status registers D0h-D1h.
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Table 4-76. Misc OFM Control
Subaddress
Default
BAh
00h
7
6
5
4
3
2
1
0
OFM_Soft_
Reset
Reserved
OFM_Soft_Reset
Soft reset for OFM logic.
NOTE: This bit is automatically cleared by firmware when the reset is completed.
0
1
Normal operation (default)
Reset output formatter logic
NOTE: In cascade mode, the OFM reset of the 1st stage should be asserted after the OCLK_N output of the 2nd stage is enabled.
Table 4-77. Audio Sample Rate Control
Subaddress
Default
C0h
00h
7
6
5
4
3
2
1
0
Reserved
Aud_SamRate_Set[2:0]
Reserved
Aud_SamRate_Set[2:0]
Audio sample rate control bits
000
001
010
011
100
101
110
111
16 kHz (default)
8 kHz
22.05 kHz
11.025 kHz
24 kHz
12 kHz
Reserved
Reserved
80
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Table 4-78. Analog Audio Gain Control 1
Subaddress
Default
C1h
88h
7
6
5
4
3
2
1
0
Audio_Gain_Ctrl_CH2
Audio_Gain_Ctrl_CH1
Audio_Gain_Ctrl_CH2
Analog audio gain control for audio Ch 2. See values below.
Audio_Gain_Ctrl_CH1
Analog audio gain control for audio Ch 1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
-12.0 dB
-10.5 dB
-9 dB
-7.5 dB
-6 dB
-4.5 dB
-3 dB
-1.5 dB
0 dB (default)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Table 4-79. Analog Audio Gain Control 2
Subaddress
Default
C2h
88h
7
6
5
4
3
2
1
0
Audio_Gain_Ctrl_CH4
Audio_Gain_Ctrl_CH3
Audio_Gain_Ctrl_CH4
Analog audio gain control for audio Ch 4. See values below.
Audio_Gain_Ctrl_CH3
Analog audio gain control for audio Ch 3
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
-12.0 dB
-10.5 dB
-9 dB
-7.5 dB
-6 dB
-4.5 dB
-3 dB
-1.5 dB
0 dB (default)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
82
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Table 4-80. Audio Mode Control
Subaddress
Default
C3h
C9h
7
6
5
4
3
2
1
0
Serial_IF_Form
at
SD_M_En
SD_R_En
I2S_Mode
BCLK_R_Freq
Audio_Data_Format
TDM_Pin_Sel
SD_M_En
SD_M output enable, active high
0
1
SD_M output disabled
SD_M output enabled (default)
SD_R_En
SD_R output enable, active high.
0
1
SD_R output disabled
SD_R output enabled (default)
I2S_Mode
Audio serial I2S interface mode
0
Slave mode (default)
Master mode
1
Serial_IF_Format
Audio serial interface format
0
1
I2S justified mode (default)
DSP justified mode
BCLK_R_Freq
Audio serial interface BCLK_R clock frequency
0
1
256 fs
64 fs (stand alone operation only) (default)
Audio_Data_Format
Audio serial interface data format
00
16-bit PCM (default)
8-bit µ-Law
01
10
11
8-bit A-Law
Reserved
TDM_Pin_Sel
TDM output pin select
0
1
SD_R only
SD_R and SD_M (default)
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Table 4-81. Audio Mixer Select
Subaddress
Default
C4h
01h
7
6
5
4
3
2
1
0
Audio_Mixer_Sel [4:0]
TDM_Chan_Number [2:0]
Audio_Mixer_Sel [4:0]
Audio mixer output select
00000 Mix channel (default)
00001 Ch 1
00010 Ch 2
00011 Ch 3
00100 Ch 4
00101 Ch 5
00110 Ch 6
00111 Ch 7
01000 Ch 8
01001 Ch 9
01010 Ch 10
01011 Ch 11
01100 Ch 12
01101 Ch 13
01110 Ch 14
01111 Ch 15
10000 Ch 16
10001
to
Reserved
11111
TDM_Chan_Number [2:0]
Number of Audio channels to TDM
000 2 channels
001 4 channels (default)
010
011
100
101
110
111
8 channels
12 channels
16 channels
Reserved
Reserved
Reserved
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Table 4-82. Audio Mute Control
Subaddress
Default
C5h
00h
7
6
5
4
3
2
1
0
Reserved
Ch4_Mute
Ch3_Mute
Ch2_Mute
Ch1_Mute
Ch4_Mute
Ch 4 Audio mute enable, active high. Affects the audio mixer output (SD_M) only (see Figure 3-17).
0
1
Disabled (default)
Enabled
Ch3_Mute
Ch 3 Audio mute enable, active high. Affects the audio mixer output (SD_M) only (see Figure 3-17).
0
1
Disabled (default)
Enabled
Ch2_Mute
Ch 2 Audio mute enable, active high. Affects the audio mixer output (SD_M) only (see Figure 3-17).
0
1
Disabled (default)
Enabled
Ch1_Mute
Ch 1 Audio mute enable, active high. Affects the audio mixer output (SD_M) only (see Figure 3-17).
0
1
Disabled (default)
Enabled
Table 4-83. Analog Mixing Ratio Control 1
Subaddress
Default
C6h
00h
7
6
5
4
3
2
1
0
Audio_Mixing_Ratio_CH2
Audio_Mixing_Ratio_CH2
Audio mixing ratio for audio channel 2. See values below.
Audio_Mixing_Ratio_CH1
Audio mixing ratio for audio channel 1
Audio_Mixing_Ratio_CH1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.25 (default)
0.31
0.38
0.44
0.5
0.63
0.75
0.88
1.00
1.25
1.5
1.75
2.00
2.25
2.5
2.75
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Table 4-84. Analog Mixing Ratio Control 2
Subaddress
Default
C7h
00h
7
6
5
4
3
2
1
0
Audio_Mixing_Ratio_CH4
Audio_Mixing_Ratio_CH4
Audio mixing ratio for audio channel 4. See values below.
Audio_Mixing_Ratio_CH3
Audio mixing ratio for audio channel 3
Audio_Mixing_Ratio_CH3
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0.25 (default)
0.31
0.38
0.44
0.5
0.63
0.75
0.88
1.00
1.25
1.5
1.75
2.00
2.25
2.5
2.75
Table 4-85. Audio Cascade Mode Control
Subaddress
Default
C8h
00h
7
6
5
4
3
2
1
0
Reserved
Audio_Cas_Mode_Ctrl
Audio_Cas_Mode_Ctrl
Audio Cascade Mode control which is cascade stage ID. Set to 00 for standalone operation.
00
01
10
11
First stage (channels 1 to 4) (default)
Second stage (channels 5 to 8)
Third stage (channels 9 to 12)
Fourth stage (channels 13 to 16)
Table 4-86. Super-Frame EAV2SAV Duration Status
Subaddress
Default
D0h-D1h
Read Only
Subaddress
D0h
7
6
5
4
3
2
1
0
EAV2SAV [7:0]
D1h
Reserved
EAV2SAV [9:8]
EAV2SAV [9:0]
Super-frame EAV2SAV duration (bytes). For line-interleaved mode only.
86
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Table 4-87. Super-Frame SAV2EAV Duration Status
Subaddress
Default
D2h-D3h
Read Only
Subaddress
D2h
7
6
5
4
3
2
1
0
SAV2EAV [7:0]
D3h
Reserved
EAV2SAV [10:8]
SAV2EAV [10:0]
Super-frame SAV2EAV duration (bytes). For line-interleaved mode only.
Table 4-88. VBUS Data Access With No VBUS Address Increment
Subaddress
Default
E0h
00h
7
6
5
4
3
2
1
0
VBUS data [7:0]
VBUS data [7:0]
VBUS data register for VBUS single-byte read/write transaction
Table 4-89. VBUS Data Access With VBUS Address Increment
Subaddress
Default
E1h
00h
7
6
5
4
3
2
1
0
VBUS data [7:0]
VBUS data [7:0]
VBUS data register for VBUS multi-byte read/write transaction. VBUS address is auto-incremented after each data byte read/write.
Table 4-90. VBUS Address Access
Subaddress
Default
E8h
00h
E9h
00h
EAh
00h
Subaddress
E8h
7
6
5
4
3
2
1
0
VBUS address [7:0]
VBUS address [15:8]
VBUS address [23:16]
E9h
EAh
VBUS access address [23:0]
VBUS is a 24-bit wide internal bus. The user needs to program the 24-bit address of the internal register to be accessed via host
port indirect access mode.
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Table 4-91. Interrupt Status
Subaddress
Default
F2h
Read Only
7
6
5
4
3
2
1
0
Reserved
Sig_Present
Weak_Sig
V_Lock
Macrovision
Vid_Std
Reserved
The host interrupt status register represents the interrupt status after applying mask bits. Therefore, the status bits are the result of a logical
AND between the raw status and mask bits. The external interrupt pin is derived from this register as an OR function of all non-masked
interrupts in this register.
Reading data from the corresponding register does not clear the status flags automatically. These flags are reset using the corresponding
bits in the interrupt clear register.
Sig_Present
Signal present change interrupt. This interrupt is asserted whenever there is a change in the signal present status (bit 7 of register
01h).
0
1
Not available
Available
Weak_Sig
Weak signal change interrupt. This interrupt is asserted whenever there is a change in the weak signal status (bit 6 of register 01h).
0
1
Not available
Available
V_Lock
Vertical lock change interrupt. This interrupt is asserted whenever there is a change in the vertical lock status (bit 2 of register 00h).
0
1
Not available
Available
Macrovision
Macrovision change interrupt. This interrupt is asserted whenever there is a change in the Macrovision detection status (bits 2:0 of
register 01h).
0
1
Not available
Available
Vid_Std
Video standard change interrupt. This interrupt is asserted whenever there is a change in the detected video standard (bits 2:0 of
register 0Ch).
0
1
Not available
Available
88
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Table 4-92. Interrupt Mask
Subaddress
Default
F4h
00h
7
6
5
4
3
2
1
0
Reserved
Sig_Present
Weak_Sig
V_Lock
Macrovision
Vid_Std
Reserved
The host interrupt mask register can be used by the external processor to mask unnecessary interrupt sources for the interrupt status
register bits, and for the external interrupt pin. The external interrupt is generated from all non-masked interrupt flags.
Sig_Present
Signal present change interrupt mask
0
1
Interrupt disabled (default)
Interrupt enabled
Weak_Sig
Weak signal change interrupt mask
0
1
Interrupt disabled (default)
Interrupt enabled
V_Lock
Vertical lock change interrupt mask
0
1
Interrupt disabled (default)
Interrupt enabled
Macrovision
Macrovision change interrupt mask
0
1
Interrupt disabled (default)
Interrupt enabled
Vid_Std
Video standard change interrupt mask
0
1
Interrupt disabled (default)
Interrupt enabled
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Table 4-93. Interrupt Clear
Subaddress
Default
F6h
00h
7
6
5
4
3
2
1
0
Reserved
Sig_Present
Weak_Sig
V_Lock
Macrovision
Vid_Std
Reserved
The host interrupt clear register is used by the external processor to clear the interrupt status bits in the host interrupt status register. When
no non-masked interrupts remain set in the register, the external interrupt pin also becomes inactive.
Sig_Present
Signal present change interrupt clear
0
1
No effect (default)
Clear interrupt bit
Weak_Sig
Weak signal change interrupt clear
0
1
No effect (default)
Clear interrupt bit
V_Lock
Vertical lock change interrupt clear
0
1
No effect (default)
Clear interrupt bit
Macrovision
Macrovision change interrupt clear
0
1
No effect (default)
Clear interrupt bit
Vid_Std
Video standard change interrupt clear
0
1
No effect (default)
Clear interrupt bit
Table 4-94. Decoder Write Enable
Subaddress
Default
FEh
0Fh
7
6
5
4
3
2
1
0
Decoder Auto
Incr
Reserved
Addr Auto Incr
Decoder 4
Decoder 3
Decoder 2
Decoder 1
This register controls which of the four decoder cores receives I2C write transactions. A 1 in the corresponding Decoder bit enables the
decoder to receive write commands. Any combination of decoders can be configured to receive write commands, allowing all four decoders
to be programmed concurrently.
The following table shows how the address auto-increment and decoder auto-increment functions operate when a multi-byte I2C write
transaction occurs. For this example, decoders 2, 3 and 4 are enabled for writes, the subaddress is 0xA0 and 8 bytes of data are written.
Decoder Auto Incr
0
0
0
1
1
0
1
1
Addr Auto Incr
Data
1st
Dec
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
Addr
A0
Dec
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
2,3,4
Addr
A0
Dec
2
Addr
A0
Dec
2
Addr
A0
2nd
3rd
4th
5th
6th
7th
8th
A0
A1
3
A0
3
A0
A0
A2
4
A0
4
A0
A0
A3
2
A0
2
A1
A0
A4
3
A0
3
A1
A0
A5
4
A0
4
A1
A0
A6
2
A0
2
A2
A0
A7
3
A0
3
A2
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Table 4-95. Decoder Read Enable
Subaddress
Default
FFh
01h
7
6
5
4
3
2
1
0
Decoder Auto
Incr
Reserved
Addr Auto Incr
Decoder 4
Decoder 3
Decoder 2
Decoder 1
This register controls which of the four decoder cores responds to I2C read transactions. A 1 in the corresponding bit position enables the
decoder to respond to read commands. A 1 in Decoder Auto Increment reads the next byte from the next enabled decoder. If Decoder Auto
Increment is 0 and more than one decoder is enabled for reading, then only the lowest numbered decoder responds. A 1 in Address Auto
Increment causes the subaddress to increment after read(s) of the current subaddress are completed.
The following table shows how the address auto-increment and decoder auto-increment functions operate when a multi-byte I2C read
transaction occurs. For this example, decoders 2, 3 and 4 are enabled for reads, the subaddress is 0xA0, and 8 bytes of data are read.
Decoder Auto Incr
0
0
0
1
1
0
1
1
Addr Auto Incr
Data
1st
Dec
2
Addr
A0
Dec
2
Addr
A0
Dec
2
Addr
A0
Dec
2
Addr
A0
2nd
3rd
4th
5th
6th
7th
8th
2
A0
2
A1
3
A0
3
A0
2
A0
2
A2
4
A0
4
A0
2
A0
2
A3
2
A0
2
A1
2
A0
2
A4
3
A0
3
A1
2
A0
2
A5
4
A0
4
A1
2
A0
2
A6
2
A0
2
A2
2
A0
2
A7
3
A0
3
A2
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5
Electrical Specifications
5.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VDD_3_3 to VSS_3_3
0.5 V to 4.0 V
VDD_1_1 to VSS_1_1
-0.2 V to 1.2 V
-0.3 V to 3.6 V
-0.2 V to 2.0 V
-0.2 V to 1.2 V
-0.5 V to 4.5 V
-0.5 V to 4.5 V
-0.2 V to 2.5 V
-0.2 V to 2.0 V
0°C to 70°C
VDD
Supply voltage range
VDDA_3_3 to VSSA_3_3
VDDA_1_8 to VSSA_1_8
VDDA_1_1 to VSSA_1_1
VI to DGND
VI
Digital input voltage range
VO
Digital output voltage range
Analog video input voltage range
Analog audio input voltage range
VO to DGND
AIN to AGND
AIN to AGND
Commercial range
Industrial range
TA
Operating free-air temperature range
Storage temperature range
-40°C to 85°C
-65°C to 150°C
>500 V
Tstg
All pins
JEDEC(3)
Excluding VSSA, VDD1_1,
XTAL_REF pins
>1000 V
>500 V
>1000 V
>250 V
>500 V
>400 V
Human-body model
(HBM)
All pins
AEC-Q100(4)
Excluding VSSA, VDD1_1,
XTAL_REF pins
VESD
ESD stress voltage(2)
All pins
JEDEC(5)
Charged-device
model (CDM)
Excluding VSSA, VDD1_1,
XTAL_REF pins
AEC-Q100(6)
All pins
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic discharges into the device.
(3) Level listed is the passing level per ANSI/ESDA/JEDEC JS-001-2010. JEDEC document JEP155 states that 500V HBM allows safe
manufacturing with a standard ESD control process, and manufacturing with less than 500V HBM is possible if necessary precautions
are taken. Pins listed as 1000V may actually have higher performance.
(4) Tested per AEC Q100-002 rev D
(5) Level listed is the passing level per EIA-JEDEC JESD22-C101E. JEDEC document JEP157 states that 250V CDM allows safe
manufacturing with a standard ESD control process. Pins listed s 250V may actually have higher performance.
(6) Tested per AEC Q100-011 rev B
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5.2 Recommended Operating Conditions
MIN NOM
MAX UNIT
VDD_3_3
VDD_1_1
VDDA_3_3
VDDA_1_8
VDDA_1_1
VI(pp)
Supply voltage, digital
3
1
3.3
1.1
3.3
1.8
1.1
1.2
0.8
3.6
1.2
V
V
Supply voltage, digital
Supply voltage, analog
3
3.6
V
Supply voltage, analog
1.65
1
1.95
1.2
V
Supply voltage, analog
V
Analog video input voltage (ac-coupling necessary)(1)
Analog audio input voltage (ac-coupling necessary)
Input voltage high, digital(2) (3)
Input voltage low, digital(4) (3)
Output current: DVO outputs/OCLK_N(3)
Output current: DVO outputs/OCLK_N(3)
Output current, OCLK_P(3)
V
VI(pp)
V
VIH
0.7 VDD_3_3
V
VIL
0.3 VDD_3_3
V
IOH
VOUT = 2.4 V
VOUT = 0.4 V
VOUT = 2.4 V
VOUT = 0.4 V
Commercial
Industrial
-4
4
mA
mA
mA
mA
°C
°C
IOL
IOH
-8
8
IOL
Output current, OCLK_P(3)
0
70
85
TA
Operating free-air temperature
-40
(1) Specified based on a typical 100% Color Bar Signal
(2) Exception: 0.7 VDDA_1_8 for XTAL_IN terminal
(3) Specified by design
(4) Exception: 0.3 VDDA_1_8 for XTAL_IN terminal
5.3 Reference Clock Specifications
MIN NOM
MAX UNIT
MHz
Frequency
27
(1)
Frequency tolerance
-50
50 ppm
(1) This number is the required specification for the external crystal/oscillator and is not tested.
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5.4 Electrical Characteristics
5.5 DC Electrical Characteristics
For minimum/maximum values: VDD_1_1 = 1.0 to 1.2 V, VDD_3_3 = 3.0 V to 3.6 V, VDDA_1_1 = 1.0 V to 1.2 V,
VDDA_1_8 = 1.65 V to 1.95 V, VDDA_3_3 = 3.0 V to 3.6 V
For typical values (TA = 25°C): VDD_1_1 = 1.1 V, VDD_3_3 = 3.3 V, VDDA_1_1 = 1.1 V, VDDA_1_8 = 1.8 V,
VDDA_3_3 = 3.3 V(1)
PARAMETER
TEST CONDITIONS
2-Ch D1 mode at 54 MHz
4-Ch D1 mode at 108 MHz
2-Ch D1 mode at 54 MHz
4-Ch D1 mode at 108 MHz
2-Ch D1 mode at 54 MHz
4-Ch D1 mode at 108 MHz
2-Ch D1 mode at 54 MHz
4-Ch D1 mode at 108 MHz
2-Ch D1 mode at 54 MHz
4-Ch D1 mode at 108 MHz
2-Ch D1 mode at 54 MHz
4-Ch D1 mode at 108 MHz
MIN
TYP
33
MAX UNIT
mA
IDD(33D)
IDD(11D)
IDD(33A)
IDD(18A)
IDD(11A)
PTOT
3.3-V I/O digital supply current
41
mA
143
156
4.5
4.5
172
168
14
mA
1.1-V core digital supply current
3.3-V analog supply current
1.8-V analog supply current
1.1-V analog supply current
mA
mA
mA
mA
mA
mA
17
mA
606
643
mW
mW
Total power dissipation, normal
operation
Power dissipation with audio powered
down
PAPWD
PDOWN
4-Ch D1 mode at 108 MHz
619
90
mW
mW
Total power dissipation with power
down (I2C register 1Ah set to FFh)
Ilkg
Input leakage current
Input capacitance(2)
Output voltage high
Output voltage low
20
8
µA
pF
V
CI
VOH
VOL
IOH = -4 mA
IOL = 4 mA
0.8 VDD_3_3
0.2 VDD_3_3
V
(1) Typical current measurements made with 4-Ch D1 video output at 108 MHz with 4-Ch audio.
(2) Specified by design
94
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5.6 Video A/D Converters Electrical Characteristics
ADC sample rate = 27 MSPS for video Ch 1, Ch 2, Ch 3, Ch 4
PARAMETER
TEST CONDITIONS
MIN
200
1.4
TYP
MAX UNIT
Video ADC conversion rate
27
MHz
Zi
Input impedance, analog video inputs(1)
Input capacitance, analog video inputs(1)
Full-scale input range of ADC(2)
Nominal analog video gain(1)
Absolute differential non-linearity(3)
Absolute integral non-linearity
Frequency response
kΩ
Ci
10
pF
V
Vi(PP)
G
Ccoupling = 0.1 µF
-2.9
0.75
1
dB
LSB
LSB
dB
dB
dB
dB
deg
%
DNL
INL
FR
AFE only
1
AFE only
2.5
Multiburst (60 IRE)
1 MHz
-0.9
-50
54
XTALK Input crosstalk(1)
SNR
NS
Signal-to-noise ratio (all channels)(4)
Fin = 1 MHz, 1.0 Vpp
Luma ramp (100 kHz to full, tilt null)
Modulated ramp
Modulated ramp
Noise spectrum
Differential phase
Differential gain
-51
0.5
±1.5
DP
DG
(1) Specified by design
(2) Full range video
(3) No missing codes
(4) Based on 10-bit internal ADC test mode
5.7 Audio A/D Converters Electrical Characteristics
ADC sample rate = 32.768 MSPS for audio Ch 1, Ch 2, Ch 3, Ch 4
PARAMETER
TEST CONDITIONS
MIN
20
1
TYP
MAX UNIT
Audio ADC conversion rate
fS = 16 kHz
32.768
MHz
Zi
Input impedance, analog audio inputs(1)
Input capacitance, analog audio inputs(1)
Full-scale input voltage range of ADC
Absolute differential non-linearity(2)
Absolute integral non-linearity
0-dB PGA gain
kΩ
Ci
10
pF
V
Vi(PP)
DNL
INL
Ccoupling = 2.2 µF, 0-dB PGA gain
AFE only
AFE only
0.75
1
1
LSB
LSB
dB
2.5
XTALK Crosstalk between any two channels
-50
SNR
Signal-to-noise ratio (all channels)
System clock frequency per channel
fS = 16 kHz, VIN = -60 dB, 1 kHz
56
dB
512 fS
Hz
(1) Specified by design
(2) No missing codes
Copyright © 2009–2011, Texas Instruments Incorporated
Electrical Specifications
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MAX UNIT
5.8 Video Output Clock and Data Timing
10-pF load for 27 MHz and 54 MHz, 6-pF load for 108 MHz
NO.
PARAMETER
TEST CONDITIONS
≤50%, OCLK_P/OCLK_N = 108 MHz
90% to 10%, OCLK_P/OCLK_N = 27 MHz
90% to 10%, OCLK_P/OCLK_N = 108 MHz
10% to 90%, OCLK_P/OCLK_N = 27 MHz
10% to 90%, OCLK_P/OCLK_N = 108 MHz
90% to 10%, Data = 27 MHz
MIN
TYP
Duty cycle, OCLK_P/OCLK_N
44
50
55
1.4
%
ns
ns
ns
ns
ns
t3
t4
t1
t2
t5
Fall time, OCLK_P/OCLK_N
Rise time, OCLK_P/OCLK_N
Fall time, Data
1.15
1.4
1.15
3.4
90% to 10%, Data = 108 MHz
2.9
10% to 90%, Data = 27 MHz
4.2
ns
Rise time, Data
10% to 90%, Data = 108 MHz
3.4
50%, OCLK_P/OCLK_N = 27 MHz
50%, OCLK_P/OCLK_N = 108 MHz
1.9
4.86
1.5
ns
ns
Propagation delay from falling edge of
OCLK_P/OCLK_N
0.22
t3
t4
90%
OCLK_P
10%
t5
t1,t2
90%
10%
DVO_x_[7:0]
Valid Data
Valid Data
Figure 5-1. Video Output Clock and Data Timing
5.8.1 Video Input Clock and Data Timing
NOTE
Video Cascade Modes: Timing is ensured by design at 27/54MHz input frequency with input trace
delays < 2 ns.
96
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5.9 I2C Host Port Timing(1)
NO.
PARAMETER
Bus free time between STOP and START
MIN
1.3
0
TYP
MAX UNIT
t1
t2
µs
Data Hold time
Data Setup time
0.9
µs
ns
t3
100
0.6
0.6
0.6
t4
Setup time for a (repeated) START condition
Setup time for a STOP condition
Hold time (repeated) START condition
Rise time SDA and SCL signal
Fall time SDA and SCL signal
Capacitive load for each bus line
I2C clock frequency
µs
t5
ns
t6
µs
t7
250
250
400
400
ns
t8
ns
Cb
fI2C
pF
kHz
(1) Specified by design
Stop
Start
Stop
Data
SDA
t1
t4
t2
t3
t5
Change
Data
SCL
t6
t7
t8
t6
Figure 5-2. I2C Host Port Timing
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5.9.1 I2S Port Timing
NOTE
Philips I2S bus compliant (specified by design) – See the Philips I2S bus specification
5.10 Miscellaneous Timings
PARAMETER
tRESET RESETB Signal Low Time for valid reset
tvalid
I2C valid time, Initialization time after reset until I2C ready
MIN
20
TYP
MAX UNIT
ms
260
µs
5.11 Power Dissipation Ratings
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX UNIT
Thermal PAD soldered to 4-layer
High-K PCB
θJA
θJC
Junction-to-ambient thermal resistance, still air
Junction-to-case thermal resistance, still air
17.17
°C/W
Thermal PAD soldered to 4-layer
High-K PCB
0.12
°C/W
TJ (max) Maximum junction temperature for reliable operation
(1) Exposed thermal pad must be soldered to JEDEC High-K PCB with adequate ground plane (see Section 6.5).
105
°C
98
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6
Application Information
6.1 4-Ch D1 Applications
4-Ch D1
8Bit@108MHz
Figure 6-1. 4-Ch D1 Application (Single BT.656 Interface)
4-Ch D1
DVO_A_[7:0]
DVO_B_[7:0]
OCLK_P
VPIF-A
VPIF-B
VIN_1
VIN_2
H.264/MPEG-4
16Bit@54MHz
4-Ch D1 Recording
TVP5158
Multi-Ch
Video Decoder
I2C
DM6467
DaVinci HD
VIN_3
VIN_4
Multi-Ch D1
Preview
Figure 6-2. 4-Ch D1 Application (16-Bit YCbCr 4:2:2 Interface)
6.2 8-Ch CIF Applications
VIN_1
VIN_2
VIN_3
4-Ch CIF + 1-Ch D1
8Bit@54MHz
DVO_A_[7:0]
OCLK_P
VPIF-A
H.264/MPEG-4
TVP5158
I2C
VIN_4
8-Ch CIF Recording
I2C
DM6467
DaVinci HD
Multi-Ch D1
Preview
VIN_1
VIN_2
4-Ch CIF + 1-Ch D1
8Bit@54MHz
DVO_A_[7:0]
OCLK_P
VPIF-B
VIN_3
VIN_4
TVP5158
Figure 6-3. 8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application
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4-Ch Half-D1 + 1-Ch D1
8Bit@108MHz
4-Ch Half-D1 + 1-Ch D1
8Bit@108MHz
NOTE: The backend DSP drops one field of Half-D1 to get CIF format video
Figure 6-4. 8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application
6.3 16-Ch CIF Applications
See Section 3.8.3.3 for the details of 16-Ch CIF applications.
100
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SLES243F–JULY 2009–REVISED JULY 2011
6.4 Application Circuit Examples
U1A
78
DVO_A_0
77
DVO_A_1
75
C70
0.1 µF
DVO_A_2
74
DVO_A_3
72
108
109
VIN_1_P
VIN_1_N
DVO_A_4
DVO_A_5
DVO_A_6
DVO_A_7
71
69
68
R54
R50
J1B
37.4 W
C71
0.1 µF
75 W
9
112
113
VIN_2_P
VIN_2_N
3
63
62
60
59
57
56
54
53
R55
DVO_B_0
DVO_B_1
DVO_B_2
DVO_B_3
DVO_B_4
DVO_B_5
DVO_B_6
DVO_B_7
R51
10
37.4 W
75 W
C72
0.1 µF
11
121
122
VIN_3_P
VIN_3_N
4
R56
R52
75 W
12
37.4 W
C73
0.1 µF
RCA_Octal_stack
125
126
46
45
43
42
40
39
37
36
VIN_4_P
VIN_4_N
DVO_C_0
DVO_C_1
DVO_C_2
DVO_C_3
DVO_C_4
DVO_C_5
DVO_C_6
DVO_C_7
R57
R53
75 W
37.4 W
116
REXT_2K
Place R50, R51, R52 and R53 close to J1
Place R54, R55, R56 and R57 close to J1
R58
1.8 kW
31
30
28
27
25
24
22
21
DVO_D_0
DVO_D_1
DVO_D_2
DVO_D_3
DVO_D_4
DVO_D_5
DVO_D_6
DVO_D_7
51
50
OCLK_P
OCLK_N/CLKIN
TVP5158
NOTE: System level ESD protection is not included in above application circuit but is recommended.
Figure 6-5. Video Input Connectivity
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U1B
C65
J1A
95
94
93
92
AIN_1
AIN_2
AIN_3
AIN_4
2.2 µF
C66
R60
5
89
88
86
85
SD_M
SD_R
1
2
5.6 kW
R61
6
7
8
2.2 µF
C67
5.6 kW
R62
LRCLK_R
BCLK_R
2.2 µF
C68
5.6 kW
R63
5.6 kW
2.2 µF
RCA_Octal_stack
83
SD_CO
16
17
19
R64
R65
R66
R67
LRCLK_CI
BCLK_CI
SD_CI
5.6 kW 5.6 kW 5.6 kW 5.6 kW
TVP5158
NOTE: System level ESD protection is not included in above application circuit but is recommended.
NOTE: Resistor divider may vary dependent on expected max input audio levels. Desired analog audio input levels should
not exceed 1Vpp.
Figure 6-6. Audio Input Connectivity
6.5 Designing with PowerPAD™ Devices
The TVP5158 device is housed in a high-performance, thermally enhanced, 128-terminal PowerPAD
package. Use of the PowerPAD package does not require any special considerations except to note that
the thermal pad, which is an exposed die pad on the bottom of the device, is a metallic thermal and
electrical conductor. Therefore, if not implementing the PowerPAD PCB features, the use of solder masks
(or other assembly techniques) can be required to prevent any inadvertent shorting by the exposed
thermal pad of connection etches or vias under the package. The recommended option, however, is not to
run any etches or signal vias under the device, but to have only a grounded thermal land as in the
following explanation. Although the actual size of the exposed die pad may vary, the minimum size
required for the keep-out area for the 128-terminal PFP PowerPAD package is 9mm x 9mm.
It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the
PowerPAD package. The thermal land varies in size, depending on the PowerPAD package being used,
the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may
or may not contain numerous thermal vias depending on PCB construction.
Other requirements for using thermal lands and thermal vias are detailed in the TI application note
PowerPAD Thermally Enhanced Package application report (SLMA002).
For the TVP5158 device, this thermal land must be grounded to the low-impedance ground plane of the
device. This improves not only thermal performance but also the electrical grounding of the device. It is
also recommended that the device ground terminal landing pads be connected directly to the grounded
thermal land. The land size should be as large as possible without shorting device signal terminals. The
thermal land can be soldered to the exposed thermal pad using standard reflow soldering techniques.
While the thermal land can be electrically floated and configured to remove heat to an external heat sink, it
is recommended that the thermal land be connected to the low-impedance ground plane for the device.
More information can be obtained from the TI application note PHY Layout (SLLA020).
102
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SLES243F–JULY 2009–REVISED JULY 2011
Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
REVISION
COMMENTS
SLES243
Initial release
SLES243A
Table 2-1, XTAL_REF description change.
Figure 3-21, 0-Ω resistor added inline between XTAL_REF pin and VSSA.
YUV references changed to YCbCr.
SLES243B
SLES243C
Section 1, Trademarks added.
Table 2-1, XTAL_IN, XTAL_REF, and XTAL_OUT terminal descriptions moved to Analog Section.
Section 3.1.2, Analog Video Input Clamping description changed.
Section 3.9.4, Analog Audio Input Clamping description added.
Section 3.11, Clock Circuit description changed.
Section 1.5, Trademarks added.
Section 1.6, Document Conventions added.
Section 1.7, Package options added.
Section 3.9.3, Serial Audio Interface added.
Figure 3-18, Serial Audio Interface Timing Diagram added.
Table 4-14, Luminance Brightness description modified.
Table 4-15, Luminance Contrast description modified.
Table 4-16, Brightness and Contrast Range Extender register added.
Table 4-17, Chrominance Saturation description modified.
Table 4-65, Interrupt Control register added.
Minor editorial changes throughout.
SLES243D
AEC-Q100 qualification added.
Section 3.8.3.3, Added comment about INTREQ outputs in video cascade mode
Section 3.10.3, Added VBUS access information.
Table 4-1, Added VBUS data and address registers.
Table 4-89, Added VBUS data register description.
Table 4-90, Added VBUS address register description.
Table 3-5, Added output format settings for I2C address B0h.
Table 3-6, Added output format settings for I2C address B0h.
Table 3-10, Combined original Table 3-11 with Table 3-10.
Table 3-10, Added output format settings for I2C address B0h.
Section 3.8.3.4, Added Hybrid Mode section.
Table 3-11, Added default super-frame output format table.
Figure 3-15, Made minor editorial changes.
Figure 3-16, Made minor editorial changes.
Table 4-1, Added super-frame EAV2SAV and SAV2EAV duration status (D0h-D3h)
Table 4-43, Modified TV/VCR mode detection description.
Table 4-19, Modified definition for color killer threshold control.
Table 4-43, Deleted obsolete stable sync control bits.
Table 4-50, Changed the default value for I2C address 88h from 00h to 03h.
Table 4-86, Added super-frame EAV2SAV duration status (subaddress: D0h-D1h)
Table 4-87, Added super-frame SAV2EAV duration status (subaddress: D2h-D3h)
Section 5.11, Modified package thermal specifications.
Minor editorial changes throughout
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Application Information
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SLES243F–JULY 2009–REVISED JULY 2011
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REVISION
COMMENTS
SLES243E
SLES243F
Table 4-1, Added RAM version MSB and LSB registers (subaddress: 05h-06h).
Table 4-6, Added RAM version MSB register (subaddress: 05h).
Table 4-7, Added RAM version LSB register (subaddress: 06h).
Section 5.1, Updated VESD limits.
Table 3-11, Super-frame format and timing information modified.
Table 3-10, 6-Ch Half-D1, 6-Ch Half-D1 + 1-Ch D1 and 3-Ch D1 formats added
Table 3-12, Added BOP and EOP bits.
Table 3-13, Added definitions for BOP and EOP bits.
Table 4-1, Changed default setting for I2C register AEh from 00h to 01h.
Table 4-1, Corrected register name for I2C register 06h.
Table 4-43, Definitions for bits 7 and 3 of I2C register 60h added.
Table 4-52, Output timing delay control range modified.
Table 4-54, Register settings for several different screen colors provided.
Table 4-63, YCbCr output code range modified.
Table 4-67, Embedded sync offset control range modified.
Table 4-69, Definition for bit 7 of I2C register B1h modified.
Table 4-70, Definition for bit 7 of I2C register B2h added.
Table 4-75, Definition for bits 7:5 of I2C register B9h added.
Table 4-77, 11.025kHz, 12kHz, 22.05kHz and 24kHz audio sample rates added.
Table 4-82, Definition for bits 3:0 of I2C register C5h modified.
Table 4-91, Definition for bits 5:0 of I2C register F2h modified.
Table 4-92, Definition for bits 5:0 of I2C register F4h modified.
Table 4-93, Definition for bits 5:0 of I2C register F6h modified.
104
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PACKAGE OPTION ADDENDUM
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5-May-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TVP5156PNP
TVP5156PNPR
TVP5157PNP
TVP5157PNPR
TVP5158IPNP
TVP5158IPNPR
TVP5158PNP
TVP5158PNPR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
HTQFP
PNP
PNP
PNP
PNP
PNP
PNP
PNP
PNP
128
128
128
128
128
128
128
128
90
1000
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
CU NIPDAU Level-3-260C-168 HR
Green (RoHS
& no Sb/Br)
1000
90
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
1000
90
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
1000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
5-May-2011
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TVP5156PNPR
TVP5157PNPR
TVP5158IPNPR
TVP5158PNPR
HTQFP
HTQFP
HTQFP
HTQFP
PNP
PNP
PNP
PNP
128
128
128
128
1000
1000
1000
1000
330.0
330.0
330.0
330.0
24.4
24.4
24.4
24.4
17.0
17.0
17.0
17.0
17.0
17.0
17.0
17.0
1.5
1.5
1.5
1.5
20.0
20.0
20.0
20.0
24.0
24.0
24.0
24.0
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TVP5156PNPR
TVP5157PNPR
TVP5158IPNPR
TVP5158PNPR
HTQFP
HTQFP
HTQFP
HTQFP
PNP
PNP
PNP
PNP
128
128
128
128
1000
1000
1000
1000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
55.0
55.0
55.0
55.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
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