TVP7000_技术文档

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO

AND GRAPHICS DIGITIZER WITH ANALOG PLL

FEATURES

APPLICATIONS

•

LCD TV/Monitors/Projectors

DLP TV/Projectors

PDP TV/Monitors

PCTV Set-Top Boxes

Digital Image Processing

Video Capture/Video Editing

Scan Rate/Image Resolution Converters

Video Conferencing

•

Analog Channels

– -6 dB to 6 dB Analog Gain

– Analog Input MUXs

– Auto Video Clamp

– Three Digitizing Channels, Each With

Independently Controllable Clamp, PGA,

and ADC

– Clamping: Selectable Clamping Between

Bottom Level and Mid-level

Video/Graphics Digitizing Equipment

– Offset: 1024-Step Programmable RGB or

YPbPr Offset Control

DESCRIPTION

TVP7000 is a complete solution for digitizing video

and graphic signals in RGB or YPbPr color spaces.

The device supports pixel rates up to 150 MHz.

Therefore, it can be used for PC graphics digitizing

up to the VESA standard of SXGA (1280 × 1024)

resolution at 75 Hz screen refresh rate, and in video

environments for the digitizing of digital TV formats,

including HDTV up to 1080p. TVP7000 can be used

to digitize CVBS and S-Video signal with 10-bit

ADCs.

– PGA: 8-Bit Programmable Gain Amplifier

– ADC: 8/10-Bit 150/110 MSPS A/D Converter

– Automatic Level Control Circuit

– Composite Sync: Integrated Sync-on-Green

Extraction From GreenLuminance Channel

– Support for DC and AC-Coupled Input

Signals

•

PLL

– Fully Integrated Analog PLL for Pixel Clock

Generation

The TVP7000 is powered from 3.3-V and 1.8-V

supply and integrates a triple high-performance A/D

converter with clamping functions and variable gain,

independently programmable for each channel. The

clamping timing window is provided by an external

pulse or can be generated internally. The TVP7000

includes analog slicing circuitry on the Y or G input to

support sync-on-luminance or sync-on-green extrac-

tion. In addition, TVP7000 can extract discrete

HSYNC and VSYNC from composite sync using a

sync slicer.

– 12-150 MHz Pixel Clock Generation From

HSYNC Input

– Adjustable PLL Loop Bandwidth for

Minimum Jitter

– 5-Bit Programmable Subpixel Accurate

Positioning of Sampling Phase

•

Output Formatter

– Support for RGB/YCbCr 4:4:4 and YCbCr

4:2:2 Output Modes to Reduce Board Traces

TVP7000 also contains a complete analog PLL block

to generate a pixel clock from the HSYNC input. Pixel

clock output frequencies range from 12 MHz to 150

MHz.

– Dedicated DATACLK Output for Easy

Latching of Output Data

System

All programming of the part is done via an indus-

try-standard I²C interface, which supports both read-

ing and writing of register settings. The TVP7000 is

available in a space-saving TQFP 100-pin PowerPAD

package.

– Industry-Standard Normal/Fast I²C Interface

With Register Readback Capability

– Space-Saving TQFP-100 Pin Package

– Thermally-Enhanced PowerPAD™ Package

for Better Heat Dissipation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

ORDERING INFORMATION

PACKAGED DEVICES

T_A

100-PIN PLASTIC FLATPACK PowerPAD™

0°C to 70°C

TVP7000PZP

FUNCTIONAL BLOCK DIAGRAM

RIN_1

RIN_2

RIN_3

10−bit

ADC

Clamp

PGA

ROUT[9:0]

GOUT[9:0]

BOUT[9:0]

GIN_1

GIN_2

GIN_3

GIN_4

10−bit

ADC

Output

Formatter

BIN_1

BIN_2

BIN_3

10−bit

ADC

SOGIN_1

SOGIN_2

SOGIN_3

DATACLK

SOGOUT

HSOUT

HSYNC_A

HSYNC_B

VSOUT

VSYNC_A

VSYNC_B

COAST

Timing Processor

and Clock generation

CLAMP

EXT_CLK

FILT1

FILT2

PWDN

RESETB

SCL

SDA

Host

Interface

I2CA

2

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

TERMINAL ASSIGNMENTS

SOGIN_1

GIN_1

1

2

3

4

5

6

7

8

75

SDA

SCL

I2CA

TMS

RESETB

PWDN

DVDD

GND

IOGND

IOVDD

R_0

R_1

R_2

R_3

R_4

IOGND

R_5

R_6

R_7

R_8

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

A18GND

A18VDD

A18GND

A18VDD

A18GND

RIN_3

9

RIN_2

RIN_1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

TVP7000

A33GND

A33VDD

A33GND

BIN_3

BIN_2

BIN_1

A18VDD

A18GND

NSUB

100−Pin TQFP Package

(Top View)

R_9

TEST

IOGND

IOVDD

G_0

VSOUT

HSOUT

SOGOUT

G_1

3

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

ANALOG VIDEO

Analog video input for R/Pr 1

RIN_1

RIN_2

RIN_3

GIN_1

GIN_2

GIN_3

GIN_4

BIN_1

BIN_2

BIN_3

11

10

9

I

Analog video input for R/Pr 2

Analog video input for R/Pr 3

Analog video input for G/Y 1

Analog video input for G/Y 2

Analog video input for G/Y 3

Analog video input for G/Y 4

Analog video input for B/Pb 1

Analog video input for B/Pb 2

Analog video input for B/Pb 3

2

100

98

96

18

17

16

The inputs must be AC coupled. The recommended coupling capacitor is 0.1 µF. Unused analog

inputs should be connected to ground using a 10 nF capacitor.

CLOCK SIGNALS

DATACLK

28

80

22

O

I

Data clock output

EXT_CLK

External clock input for free running mode

Internal 5 MHz clock output, coast output, high-Z, or SOG output

TEST

O

DIGITAL VIDEO

ROUT [9:0]

GOUT [9:0]

BOUT [9:0]

55–59, 61–65

43-52

O

Digital video output of R/Cr, ROUT [9] is MSB.

Digital video output of G/Y, GOUT [9] is MSB.

Digital video output of B/Cb, BOUT [9] is MSB. For a 4:2:2 mode BOUT outputs CbCr data.

29-38

Unused outputs can be left unconnected.

MISCELLANEOUS SIGNALS

PWDN

70

71

I

Power down input. 1: Power down 0: Normal mode

Reset input, active low

RESETB

Test Mode Select input. Used to enable JTAG test mode. Active high. Normal mode, this terminal

should be connected to a ground.

TMS

72

I

FILT1

87

88

O

External filter connection for PLL. The recommended capacitor is 0.1 µF. see Figure 4

FILT2

External filter connection for PLL. The recommended capacitor is 4.7 nF. See Figure 4

HOST INTERFACE

I²C A

73

74

75

I

I²C Address input

I²C Clock input

SCL

SDA

I/O I²C Data bus

POWER SUPPLIES

NSUB

21, 91

I

Substrate ground. Connect to analog ground.

A33VDD

A33GND

A18GND

A18VDD

PLL_A18VDD

PLL_F

13, 14, 93, 94

12, 15, 92, 95

3, 5, 8, 20

4, 6, 7, 19

84, 85

Analog power. Connect to 3.3 V.

Analog 3.3 V return. Connect to Ground.

Analog 1.8V return. Connect to Ground

Analog power. Connect to 1.8 V.

PLL analog power. Connect to 1.8 V.

PLL filter internal supply connection

PLL analog power return. Connect to Ground.

Digital return. Connect to Ground.

Digital power. Connect to 1.8 V

89

PLL_A18GND

GND

83, 86, 90

40, 68

DVDD

39, 69

27, 42, 54, 60,

67

Digital power return. Connect to Ground.

IOGND

I

IOVDD

26, 41, 53, 66

Digital power. Connect to 3.3 V or less for reduced noise.

SYNC SIGNALS

CLAMP

76

77

I

External Clamp input. Unused inputs can be connected to ground.

COAST

External PLL COAST signal input. Unused inputs can be connected to ground

4

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

TERMINAL FUNCTIONS (continued)

TERMINAL

I/O

DESCRIPTION

NAME

NO.

VSYNC_A

VSYNC_B

78

79

I

Vertical sync input A

Vertical sync input B. Unused inputs can be connected to ground.

HSYNC_A

HSYNC_B

81

82

I

Horizontal Sync input A

Horizontal Sync input B. Unused inputs can be connected to ground.

SOGIN1

SOGIN2

SOGIN3

1

99

97

I

i

Sync-on-green input 1

Sync-on-green input 2

Sync-on-green input 3. Unused inputs should be connected to ground using a 10 nF capacitor.

VSOUT

HSOUT

SOGOUT

23

24

25

O

Vertical sync output

Horizontal sync output

Sync-on-green slicer output

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

UNIT

IOVDD to IOGND

–0.5 V to 4.5 V

–0.5 V to 2.3 V

– 0.5 V to 4.5 V

–0.5 V to 4.5 V

–0.2 V to 2.3 V

–0.5 V to 4.5 V

0°C to 70°C

DVDD to GND

Supply voltage range

PLL_A18VDD to PLL_A18GND and A18VDD to A18GND

A33VDD to A33GND

VI to GND

Digital input voltage range

Analog input voltage range

Digital output voltage range

Operating free-air temperature

AI to A33GND

VO to GND

TA

Tstg Storage temperature

–65°C to 150°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range, T_A= 0°C to 70°C (unless otherwise noted)

MIN

3.0

NOM

3.3

MAX

3.6

1.9

3.6

2.0

UNIT

V

IOVDD

DVDD

Digital I/O supply voltage

Digital supply voltage

1.70

1.8

V

PLL_A18VDD Analog PLL supply voltage

1.70

1.8

V

A18VDD

A33VDD

V_I(P–P)

V_IH

Analog supply voltage

1.70

1.8

V

Analog supply voltage

3.0

3.3

V

Analog input voltage (ac–coupling necessary)

Digital input voltage high

0.5

V

0.7 IOVDD

V

V_IL

Digital input voltage low

0.3 IOVDD

V

I_OH

High–level output current

2

–2

4

mA

°C

I_OL

Low–level output current

I_{OH_DATACLK}

I_{OL_DATACLK}

T_A

DATACLK high–level output current

DATACLK low–level output current

Operating free–air temperature

–4

70

0

5

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS

IOVDD = 3.3 V, DVDD = 1.8 V, PLL_A18VDD = 1.8 V, A18VDD = 1.8 V, A33VDD = 3.3 V, T_A= 25°C

PARAMETER

TEST CONDITIONS

MIN TYP⁽¹⁾

MAX⁽²⁾

UNIT

POWER SUPPLY

I_IOVDDD

I_DVDD

P_TOT

3.3-V supply current

1.8-V supply current

78.75 MHz

80

253

719

101

261

803

128

250

872

1

130

mA

78.75 MHz

108 MHz

260

897

mA

mW

mA

mW

mA

mW

Total power dissipation, normal mode

3.3-V supply current

I_IOVDDD

I_DVDD

P_TOT

160

1.8-V supply current

108 MHz

275

Total power dissipation, normal mode

3.3-V supply current

108 MHz

1023

240

I_IOVDDD

I_DVDD

P_TOT

148.5 MHz

1.8-V supply current

280

Total power dissipation, normal mode

Total power dissipation, power–down mode

1296

P_DOWN

(1) SMPTE color bar RGB input pattern used.

(2) Worst case vertical line RGB input pattern used.

6

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS

IOVDD = 3.3 V, DVDD = 1.8 V±0.1, PLL_A18VDD = 1.8 V±0.1, A18VDD = 1.8 V±0.1, A33VDD = 3.3 V, T_A= 0°C to 70°C

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INTERFACE

Input voltage range

Input impedance, analog video inputs

DIGITAL LOGIC INTERFACE

By design

0.5

1.0

2.0

Vpp

Z_I

By design

500

kΩ

C_i

Input capacitance

By design

I_OH= 2 mA

I_OL= –2 mA

I_OH= 4 mA

I_OH= –2 mA

By design

10

pF

kΩ

V

Z_i

Input impedance

500

V_OH

Output voltage high

0.8 IOVDD

0.7 IOVDD

V_OL

Output voltage low

0.2 IOVDD

0.3 IOVDD

V

V_{OH_SCLK}

V_{OL_SCLK}

V_IH

DATACLK output voltage high

DATACLK output voltage low

High-level input voltage

Low-level input voltage

V

V_IL

V

A/D CONVERTERS

Conversion rate

12

-1

-4

150

+1

+4

MSPS

LSB

10 bit, 110 MHz

8 bit, 150 MHz

10 bit, 110 MHz

8 bit, 150 MHz

±0.5

±1

DNL

INL

DC differential nonlinearity

DC integral nonlinearity

LSB

±1

Missing code

none

52

SNR

Signal-to-noise ratio

10 MHz, 1.0 V_P–Pat 110

MSPS

dB

Analog bandwidth

By design

500

MHz

PLL

Clock jitter

500

ps

Phase adjustment

VCO frequency range

11.6

degree

MHz

12

150

7

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

TIMING REQUIREMENTS

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

TYP

MAX

UNIT

CLOCKS, VIDEO DATA, SYNC TIMING

Duty cycle DATACLK

50%

t₁

t₂

t₃

DATACLK rise time

DATACLK fall time

Output delay time

10% to 90%

1

ns

90% to 10%

1.5

3.5

(1) Measured with a load of 15 pF.

t1

DATACLK

t2

R, R, B, HSOUT

Valid Data

t3

Figure 1. Clock, Video Data, and Sync Timing

8

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

TIMING REQUIREMENTS

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

I²C HOST PORT TIMING

t₁

Bus free time between STOP and START

Specified by design

1.3

0.6

100

0

µs

ns

t₂

Setup time for a (repeated) START condition

Hold time (repeated) START condition

Setup time for a STOP condition

Data setup time

Specified by design

t₃

t₄

t₅

ns

t₆

Data hold time

0.9

250

400

µs

ns

t₇

Rise time SDA and SCL signal

Fall time SDA and SCL signal

Capacitive load for each bus line

I²C clock frequency

t₈

ns

C_b

f_12C

pF

kHz

Stop Start

Stop

SDA

SCL

Data

t7

t1

t6

t3

t6

t2

t5

t4

t8

Figure 2. I²C Host Port Timing

9

TVP7000

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SLES143–SEPTEMBER 2005

FUNCTIONAL DESCRIPTION

Analog Channel

The TVP7000 contains three identical analog channels that are independently programmable. Each channel

consists of a clamping circuit, a programmable gain amplifier, automatic offset control and an A/D converter.

Analog Input Switch Control

TVP7000 has 3 analog channels that accept up to 10 video inputs. The user can configure the internal analog

video switches via the I2C interface. The 10 analog video inputs can be used for different input configurations

some of which are:

•

Up to 10 selectable individual composite video inputs

Up to 2 selectable RGB graphics inputs

Up to 3 selectable YPbPr video HD/SD inputs

The input selection is performed by the input select register at I²C subaddress 0×19 and 0×1A (see Input Mux

Select 1 and Input Mux Select 2)

Analog Input Clamping

An internal clamping circuit restores the AC-coupled video/graphic signal to a fixed DC level. The clamping circuit

provides line-by-line restoration of the signal black level to a fixed DC reference voltage. The selection between

bottom and mid level clamping is performed by I²C subaddress 0×10 (see Sync On_Green Threshold)

The internal clamping time can be adjusted by I²C clamp start and width registers at subaddress 0×05 and 0×06

(see Clamp Start and Clamp Width)

Programmable Gain Amplifier (PGA)

The TVP7000 PGA can scale a signal with a voltage-input compliance of 0.5-Vpp to 2-Vpp to a full-scale 10-bit

A/D output code range. A 4-bit code sets the coarse gain (Red Coarse Gain, Green Coarse Gain, Blue Coarse

Gain) with individual adjustment per channel. Minimum gain corresponds to a code 0×0 (2-Vpp full-scale input,

–6 dB gain) while maximum gain corresponds to code 0×F (0.5-Vpp full-scale, +6 dB gain). TVP7000 also has

8-bit fine gain control (Red Fine Gain, Green Fine Gain, Blue Fine Gain) for RGB independently ranging from 1

to 2. For a normal PC graphics input, the fine gain will be used mostly.

Programmable Offset Control and Automatic Level Control (ALC)

The TVP7000 supports a programmable offset control for RGB independently. A 6-bit code sets the coarse offset

(Red Coarse Offset, Green Coarse Offset, Blue Coarse Offset) with individual adjustment per channel. The

coarse offset ranges from –32 LSB to +31 LSB. The coarse offset registers apply before the ADC. A 10-bit fine

offset registers (Red Fine Offset, Green Fine Offset, Blue Fine Offset) apply after the ADC. The fine offset ranges

from –512 LSB to +511 LSB.

ALC circuit maintains the level of the signal to be set at a value which is programmed at fine offset I²C register. It

consists of pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by I²C register

address at 0×26. ALC circuit needs a timing pulse generated internally but user should program the position

properly. The ALC pulse must be positioning after the clamp pulse. The position of ALC pulse is controlled by

ALC placement I²C register at address 0×31. This is available only for internal ALC pulse timing. For external

clamp, the timing control of clamp is not applicable so the ALC pulse control is also not applicable. Therefore it is

suggested to keep the external clamp pulse as long as possible. ALC is applied as same position of external

clamp pulse.

A/D Converters

All ADCs have a resolution of 10-bits and can operate up to 150 MSPS. All A/D channels receive an identical

clock from the on-chip phase-locked loop (PLL) at a frequency between 12 MHz and 150 MHz. All ADC

reference voltages are generated internally. Also the external sampling clock can be used.

10

TVP7000

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SLES143–SEPTEMBER 2005

Analog PLL

The analog PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to

derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal

sync signal supplied on the HSYNC input or from extracted horizontal sync of sync slicer block for embedded

sync signals. The analog PLL consisted of phase detector, loop filter, voltage controlled oscillator (VCO), divider

and phase select. The analog block diagram is shown at Figure 3.

PLL Control

Register 0x03

Bit [5:3]

PLL Control

Register 0x03

Bit [7:6]

Phase Select

Register 0x04

Bit [7:3]

COAST

HSYNC

Phase

Detector

Charge

Pump

Loop

Filter

Phase

Select

VCO

÷ N

ADC

Sampling

CLK

N = 1 or 2

Divider

External

Clock

PLL Divide

Register 0x01

and 0x02

Bit [11:0]

Figure 3. PLL Block Diagram

The COAST signal is used to allow the PLL to keep running at the same frequency, in the absence of the

incoming HSYNC signal or disordered HSYNC period. This is useful during the vertical sync period, or any other

time that the HSYNC is not available.

There are several PLL controls to produce the correct sampling clock. The 12-bit divider register is

programmable to select exact multiplication number to generate the pixel clock in the range of 12 MHz to 150

MHz. The 3-bit loop filter current control register is to control the charge pump current that drives the low-pass

loop filter. The applicable current values are listed in the Table 1.

The 2-bit VCO range control is to improve the noise performance of the TVP7000. The frequency ranges for the

VCO are shown in Table 1. The phase of the PLL generated clock can be programmed in 32 uniform steps over

a single clock period (360/32=11.25 degrees phase resolution) so that the sampling phase of the ADC can be

accurately controlled.

In addition to sourcing the ADC channel clock from the PLL, an external pixel clock can be used (from pin 80).

The PLL characteristics are determined by the loop filter design, by the PLL charge pump current, and by the

VCO range setting. The loop filter design is shown in Figure 4. Supported settings of VCO range and charge

pump current for VESA standard display modes are listed in Table 1.

11

TVP7000

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SLES143–SEPTEMBER 2005

89

PLL_F

4.7 nF

88

87

1.5 kΩ

FILT2

FILT1

0.1 µF

TVP7000

Figure 4. PLL Loop Filter

Table 1. Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display

Formats

STANDARD

RESOL-

UTION

REFRESH

RATE

HORIZON-

TAL

FRE-

PIXEL RATE PLL Divider

PLLDIV

MSB Reg

01h

PLLDIV LSB

Reg 02h

[11:4]

Reg 03h

Output Div-

ider Reg

04h [0]

VCO

RANGE Reg

03h [7:6]

CP CUR-

RENT Reg

03h [5:3]

(MHz)

Total

pix/line

QUENCY

(kHz)

VGA

640 × 480

800 × 600

60 Hz

72 Hz

75 Hz

85 Hz

56 Hz

60 Hz

72 Hz

75 Hz

85 Hz

60 Hz

70 Hz

75 Hz

85 Hz

60 Hz

75 Hz

60 Hz

50 Hz

60 Hz

50 Hz

60 Hz

50 Hz

60 Hz

31.5

37.9

37.5

43.3

35.1

37.9

48.1

46.9

53.7

48.4

56.5

60

25.175

31.5

36

1600(2×)

1664(2×)

1680(2×)

832

64h

68h

69h

34h

40h

42h

41h

42h

41h

54h

53h

52h

56h

69h

6Bh

6Ch

67h

7Bh

89h

A5h

89h

00h

80h

00h

80h

40h

00h

20h

C0h

80h

00h

80h

68h

58h

68h

58h

A8h

98h

68h

A8h

D8h

1

0

1

0

Low (01b)

Med (10b)

Low (01b)

Med (10b)

High (11b)

101b

011b

101b

011b

101b

011b

101b

011b

SVGA

36

1024

40

1056

50

1040

49.5

56.25

65

1056

1048

XGA

1024 × 768

1344

75

1328

78.75

94.5

108

1312

68.7

64

1376

SXGA

Video

1280 × 1024

1688

80

135

1688

720 × 480p

720 × 576p

31.468

31.25

45

27

1716(2×)

1728(2×)

1650

27

1280 × 720p

1920 × 1080i

74.25

148.5

37.5

33.75

28.125

67.5

1980

2200

2640

1920 ×

2200

1080p

1920 ×

50 Hz

56.25

148.5

2640

A5h

00h

D8h

0

High (11b)

011b

1080p

Sync Slicer

TVP7000 includes a circuit that compares the input signal on Green channel to a level 150mV (typical value)

above the clamped level (sync tip). The slicing level is programmable by I²C register subaddress at 0x10. The

digital output of the composite sync slicer is available on the SOGOUT pin.

Sync Separator

The sync separator automatically extracts VSYNC and HSYNC from the sliced composite sync input supplied at

the SOG input. The G or Y input containing the composite sync must be AC coupled to the SOG input pin using

a 10-nF capacitor. Support for PC graphics, SDTV, and HDTV up to 1080p is provided.

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Activity

Detect

SOGOUT

SYNC

Slicer

SOG

SYNC

Separator

Activity

Detect

5MHz

CLK

HSYNC

VSYNC

COAST

Activity

Detect

VSOUT

Polarity

Detect

HSYNC

Clock

Generation

HSOUT

COAST

DATACLK

Phase

Select

DIV

ADC

Figure 5. Sync Processing

Timing

The TVP7000 supports RGB/YCbCr 4:4:4 and YCbCr 4:2:2 modes. Output timing is shown in Figure 6. All timing

diagrams are shown for operation with internal PLL clock at phase 0. For a 4:2:2 mode, CbCr data outputs at

BOUT[9:0] pins.

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RGBin

P0

P1

P3

P10 P11

P12

HSYNC

DATACLK

13 clocks latency

D0

D1

D3

D4

D5

RGBout

HSOUT

Programmable Width

4:4:4: RGB/YCbCr Output Timing

RGBin

P0

P1

P3

P10 P11

P12

HSYNC

DATACLK

13 clocks latency

GOUT

Y0

Y1

Y2

Y3

Y4

BOUT

Cb0 Cr0 Cb2 Cr2 Cb4

Programmable Width

HSOUT

4:2:2 YCbCr Output Timing

Figure 6. Output Timing Diagram

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I²C Host Interface

Communication with the TVP7000 device is via an I²C host interface. The I²C standard consists of two signals,

serial input/output data (SDA) line and input clock line (SCL), which carry information between the devices

connected to the bus. A third signal (I²CA) is used for slave address selection. Although an I²C system can be

multi-mastered, the TVP7000 can function as a slave device only.

Since SDA and SCL are kept open-drain at logic high output level or when the bus is not driven, the user should

connect SDA and SCL to a positive supply voltage via a pull up resistor on the board. SDA is implemented

bi-directional. The slave addresses select, terminal 73 (I²CA), enables the use of two TVP7000 devices tied to

the same I²C bus since it controls the least significant bit of the I²C device address

Table 2. I²C Host Interface Terminal Description

SIGNAL

I²C A

SCL

TYPE

DESCRIPTION

Slave address selection

Input clock line

I

SDA

I/O

Input/output data line

Reset and I²C Bus Address Selection

TVP7000 can respond to two possible chip addresses. The address selection is made at reset by an externally

supplied level on the I²C A pin. The TVP7000 device samples the level of terminal 73 at power- up or at the

trailing edge of RESETB and configures the I²C bus address bit A0. The I²C A terminal has an internal pull-down

resistor to pull the terminal low to set a zero.

Table 3. I²C Host Interface Device Addresses

A6

1

A5

0

A4

1

A3

1

A2

1

A1

0

A0 (I²C A)

0 (default)

1⁽¹⁾

R/W

1/0

HEX

B9/B8

BB/BA

1

0

1

0

1/0

(1) If terminal 73 strapped to DVDD via a 2.2 kΩ resistor, I²C device address A0 is set to 1.

I²C Operation

Data transfers occur utilizing the following illustrated formats.

S

10111000

ACK

subaddress

ACK

send data

ACK

P

Read from I²C control registers

S

10111000

ACK

subaddress

ACK

S

10111001

ACK

receive data

NAK

P

S =

I²C Bus Start condition

I²C Bus Stop condition

P =

ACK =

NAK =

Acknowledge generated by the slave

Acknowledge generated by the master, for multiple byte read master with ACK each byte except last byte

Subaddress byte

Subaddress =

Data =

Data byte, if more than one byte of DATA is transmitted (read and write), the subaddress pointer is automatically

incremented

I²C bus address = Example shown that I²C A is in default mode. Write (B8h), Read (B9h)

Power-up, Reset, and Initialization

No specific power-up sequence is required, but all power supplies should be active and stable within 500 ms of

each other. Reset may be low during power-up, but must remain low for at least 1 µs after the power supplies

become stable. Alternately reset may be asserted any time with minimum 5 ms delay after power-up and must

remain asserted for at least 1 µs. Reset timing is shown in Figure 7. It is also recommended that any I²C

operation starts 1 µs after reset ended. Table 4 describes the status of the TVP7000 terminals during and

immediately after reset.

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Table 4. Reset Sequence

SIGNAL NAME

DURING RESET

RESET COMPLETED

ROUT[9:0], BOUT[9:0], BOUT[9:0]

HSOUT, VSOUT, SOGOUT

DATACLK

High impedence

Output

5 ms

1 µs

Power

Reset

I2C

Figure 7. Reset Timing

Control Registers

The TVP7000 is initialized and controlled by a set of internal registers that define the operating parameters of the

entire device. Communication between the external controller and the TVP7000 is through a standard I²C host

port interface, as described earlier.

Table 5 shows the summary of these registers. Detailed programming information for each register is described

in the following sections.

Table 5. Control Registers Summary⁽¹⁾⁽²⁾

Register Name

I²C Subaddress

Default

R/W

R

Chip Revision

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

PLL Divide MSB

PLL Divide LSB

PLL Control

69h

D0h

48h

80h

20h

80h

40h

4Eh

R/W

Phase Select

Clamp Start

Clamp Width

HSYNC Output Width

Blue Fine Gain

Green Fine Gain

Red Fine Gain

Blue Fine Offset

Green Fine Offset

Red Fine Offset

Sync Control 1

PLL and Clamp Control

(1) Register addresses not shown in the register map summary are reserved and must not be written to.

(2) Writing to or reading from any value labeled “Reserved” register may cause erroneous operation of the TVP7000. For registers with

reserved bits, a 0b must be written to reserved bit locations unless otherwise stated.

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Table 5. Control Registers Summary (continued)

Register Name

I²C Subaddress

Default

R/W

R

Sync On Green Threshold

Sync Separator Threshold

Pre-Coast

10h

B8h

20h

00h

11h

12h

Post-Coast

13h

Sync Detect Status

Output Formatter

Test Register

14h

15h

00h

R/W

16h

Reserved

17h–18h

19h

Input Mux Select 1

Input Mux Select 2

Blue and Green Coarse Gain

Red Coarse Gain

Fine Offset LSB

Blue Coarse Offset

Green Coarse Offset

Red Coarse Offset

HSOUT Output Start

MISC Control

00h

55h

05h

00h

20h

09h

00h

R/W

1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

20h

21h

22h

Reserved

23h–25h

26h

Automatic Level Control Enable

Reserved

00h

R/W

27h

Automatic Level Control Filter

Reserved

28h

29h

Fine Clamp Control

Power Control

2Ah

2Bh

ADC Setup

2Ch

00h

R/W

Coarse Clamp Control 1

SOG Clamp

2Dh

2Eh

Reserved

2Fh–30h

31h

ALC Placement

00h

R/W

R = Read only

W = Write only

R/W = Read Write

Register Definitions

Chip Revision

Subaddress

00h

Read Only

0

7

6

5

4

3

2

1

Chip revision [7:0]

Chip revision [7:0]: Chip revision number

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PLL Divide

Subaddress

01h–02h

Default (69D0h)

0

7

6

5

4

3

2

1

PLL divide MSB [11:4]

PLL divide LSB [3:0]

Reserved

PLL divide [11:0]: PLL divide number sets the number of pixels per line. Controls the PLL feedback divider. MSB [11:4] bits should be

loaded first whenever a change is required

PLL Control

Subaddress

03h

Default (48h)

7

6

5

4

3

2

1

0

VCO[1:0]

Charge Pump Current [3:1]

Reserved

VCO [1:0]: Selects VCO frequency range

00 = Ultra low

01 = Low (default)

10 = Medium

11 = High

Charge Pump Current [3:0]: Selects charge current of PLL LPF

000 = Small (default)

111 = Large

Phase Select

Subaddress

04h

Default (80h)

7

6

5

4

3

2

1

0

Phase Select [4:0]

Reserved

DIV2

Phase Select [4:0]: ADC Sampling clock phase select. (1 LSB = 360/32 = 11.25°)

DATACLK Divide-by-2

0 = DATACLK/1

1 = DATACLK/2

Clamp Start

Subaddress

05h

Default (80h)

0

7

6

5

4

3

2

1

Clamp Start [7:0]

Clamp Start [7:0]: Positions the clamp signal an integer number of clock periods after the HSYNC signal. If external clamping is selected

this value has no meaning

Clamp Width

Subaddress

06h

Default (80h)

0

7

6

5

4

3

2

1

Clamp Width [7:0]

Clamp Width [7:0]: Sets the width in pixels for clamp. See register Clamp Start.

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Table 6. Recommended Fine Clamp Settings

VIDEO STANDARD

CLAMP START

50 (32h)

CLAMP WIDTH

HDTV (tri-level)

SDTV (bi-level)

PC Graphics

32 (20h)

16 (10h)

6 (06h)

HSYNC Output Width

Subaddress

07h

Default (20h)

0

7

6

5

4

3

2

1

HSOUT Width [7:0]

HSOUT Width [7:0]: Sets the width in pixels for HSYNC output.

Blue Fine Gain

Subaddress

08h

Default (80h)

0

7

6

5

4

3

2

1

Blue Gain [7:0]

Blue Gain [7:0]: PGA digital gain (contrast) for Blue channel applied after the ADC. Gain = 1 + Blue Gain[7:0]/256

80h = Recommended setting for 700 mVp-p input and default Coarse Gain (default).

Green Fine Gain

Subaddress

09h

Default (80h)

0

7

6

5

4

3

2

1

Green Gain [7:0]

Green Gain [7:0]: PGA digital gain (contrast) for Green channel applied after the ADC. Gain = 1 + Green Gain[7:0]/256

80h = Recommended setting for 700 mVp-p input and default Coarse Gain (default).

Red Fine Gain

Subaddress

0Ah

Default (80h)

0

7

6

5

4

3

2

1

Red Gain [7:0]

Red Gain [7:0]: Sets PGA digital gain (contrast) for Red channel applied after the ADC. Gain = 1 + Red Gain[7:0]/256

80h = Recommended setting for 700 mVp-p input and default Coarse Gain (default).

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Blue Fine Offset

Subaddress

0Bh

Default (80h)

0

7

6

5

4

3

2

1

Blue Offset [9:2]

Blue Offset [9:2]: DC digital offset (brightness) for Blue channel applied after the ADC.

The default setting of 80h will place the bottom-level (YRGB) clamped output blank levels at 0 and mid-level clamped (PbPr) output blank

levels at 512.

Blue Offset

11111111

100000001

10000000

01111111

00000000

Description

maximum

1 LSB

0 (default)

–1 LSB

minimum

Green Fine Offset

Subaddress

0Ch

Default (80h)

0

7

6

5

4

3

2

1

Green Offset [9:2]

Green Offset [9:2]: DC digital offset (brightness) for Green channel applied after the ADC. See Red Fine Offset register at I²C address 0x0B

Red Fine Offset

Subaddress

0Dh

Default (80h)

0

7

6

5

4

3

2

1

Red Offset [9:2]

Red Offset [9:2]: DC digital offset (brightness) for Red channel applied after the ADC. See Blue Fine Offset register at I²C address 0x0B.

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Sync Control 1

Subaddress

0Eh

Default (40h)

7

6

5

4

3

2

1

0

HSPO

HSIP

HSOP

AHSO

AHSS

VSOI

AVSO

AVS

HSPO: HSYNC Polarity Override

0 = Polarity determined by chip (default)

1 = Polarity set by Bit 6 in register 0Eh

HSIP: HSYNC Input Polarity

0 = Indicates input HSYNC polarity active low

1 = Indicates input HSYNC polarity active high (default)

HSOP: HSYNC Output Polarity

0 = Active low (default)

1 = Active high

AHSO: Active HSYNC Override

0 = The active interface is selected via Bit 6 in register 14h, selected by chip (default)

1 = The user can select HSYNC to be used via Bit 3

AHSS: Active HSYNC Select. The indicated HSYNC will be used only if Bit 4 is set to 1 or both syncs are active (Bits 1,7 =1 in 14h)

0 = Select HSYNC as the active sync (default)

1 = Select Sync-on-green as the active sync

VSOI: VSYNC Output Invert (relative to VSYNC IN polarity)

0 = No invert (default)

1 = Invert

AVSO: Active VSYNC Override

0 = The active interface is selected via Bit3 in register 14h, selected by chip (default)

1 = The user can select the VSYNC to be used via Bit 0

AVS: Active VSYNC select, This bit is effective when AVSO Bit 1 is set to 1.

0 = Raw VSYNC (default)

1 = Sync separated VSYNC

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PLL and Clamp Control

Subaddress

0Fh

Default (4Eh)

7

6

5

4

3

2

1

0

CF

CP

Coast Sel

CPO

CPC

Reserved

FCPD

Free run

Clamp Function:

0 = Internal Clamp(default)

1 = External Clamp

Clamp Polarity:

0 = Active high

1 = Active low (default)

Coast Select:

0 = External coast (default)

1 = Internal Coast

Coast Polarity Override:

0 = Polarity determined by chip (default)

1 = Polarity set be Bit 3 in register 0Fh

Coast Polarity Change:

0 = Active low

1 = Active high (default)

Full Chip Power-Down:

0 = Power-down mode

1 = Normal operation (default)

Free run: Also ADC test mode, ADC uses external clock

0 = PLL normal operation (default)

1 = Enabled

Sync On_Green Threshold

Subaddress

10h

Default (B8h)

7

6

5

4

3

2

1

0

SOG Threshold [4:0]

Blue CS

Green CS

Red CS

SOG Threshold [4:0]: Sets the voltage level of the SOG slicer comparator. The minimum setting is 0 mV and the maximum is 350 mV. The

step is 11 mV. (default 17h, 10h recommended)

Blue Clamp Select: When free running mode this bit is no effect

0 = Bottom level clamp (default)

1 = Mid level clamp

Green Clamp Select: When free running mode this bit is no effect

0 = Bottom level clamp (default)

1 = Mid level clamp

Red Clamp Select: When free running mode this bit is no effect.

0 = Bottom level clamp (default)

1 = Mid level clamp

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Sync Separator Threshold

Subaddress

11h

Default (20h)

7

6

5

4

3

2

1

0

Sync Separator Threshold [7:0]

Sync Separator Threshold [7:0]: Sets how many internal 5 MHz clock periods the sync separator will count to before toggling high or low.

The selection of this register affects the VSYNC out position relative to HSYNC out.

Pre-Coast

Subaddress

12h

Default (00h)

0

7

6

5

4

3

2

1

Pre-Coast [7:0]

Pre-Coast [7:0]: Sets the number of HSYNC periods that coast becomes active prior to VSYNC.

Post-Coast

Subaddress

13h

Default (00h)

0

7

6

5

4

3

2

1

Post-Coast [7:0]

Post-Coast [7:0]: Sets the number of HSYNC periods that coast stays active following VSYNC.

Table 7. Recommended Pre and Post-Coast Settings

STANDARD

PRE_COAST

POST-COAST

480i/p with Macrovision

3

0

0Ch

0

576i/p with Macrovision

1080i

1080p

720p

0

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Sync Detect Status

Subaddress

14h

Read Only

7

6

5

4

3

2

1

0

HSD

AHS

IHSPD

VSD

AVS

VSPD

SOGD

ICPD

HSYNC Detect:

0 = No HSYNC detected

1 = HSYNC detected

Active HSYNC:

0 = HSYNC input pin

1 = HSYNC from SOG

Input HSYNC Polarity Detect:

0 = Active low

1 = Active high

VSYNC Detect:

0 = No VSYNC detected

1 = VSYNC detected

AVS:

0 = VSYNC input pin

1 = VSYNC from Sync separator

VSYNC Polarity Detect:

0 = Active low

1 = Active high

SOG Detect:

0 = No SOG detected

1 = SOG is present on the SOG interface

Input Coast Polarity Detect:

0 = Active low

1 = Active high

Output Formater

Subaddress

15h

Default (00h)

7

6

5

4

3

2

1

0

Reserved

Clamp REF

CbCr order

422/444

Reserved

Clamp REF:

0 = Clamp pulse placement respect to the trailing edge of HSYNC (default)

1 = Clamp pulse placement respect to the leading edge of HSYNC

CbCr order: This bit is effective when Bit 1 is set to 1.

0 = CrCb (default)

1 = CbCr

422/444:

0 = Output is in 4:4:4 format (default)

1 = Output is in 4:2:2 format

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Test Register

Subaddress

16h

Default (00h)

7

6

5

4

3

2

1

0

Pixel tolerance [2:0]

Reserved

Test ouptut

PLL PD

STRTB

Pixel tolerance:

000 = No tolerance (default)

001 = 1 pixel tolerance (recommended setting for best SOG performance)

111 = 7 pixel tolerance (maximum)

Test output: Controls TEST 1 pin output

00 = 5 MHz clock (default)

01 = Coast output

10 = Clamp

11 = High impedance

PLL PD: PLL power-down

0 = Normal operation (default)

1 = PLL powered down

STRTB: PLL start-up circuit enable

0 = Disabled (default)

1 = Enabled

Input Mux Select 1

Subaddress

19h

Default (00h)

0

7

6

5

4

3

2

1

SOG Select [1:0]

Red Select [1:0]

Green Select [1:0]

Blue Select [1:0]

SOG Select [1:0]:

00 = CH1 selected (default)

01 = CH2 selected

10 = CH3 selected

11 = Reserved

Red Select [1:0]:

00 = CH1 selected (default)

01 = CH2 selected

10 = CH3 selected

11 = Reserved

Green Select [1:0]:

00 = CH1 selected (default)

01 = CH2 selected

10 = CH3 selected

11 = CH4 selected

Blue Select [1:0]:

00 = CH1 selected (default)

01 = CH2 selected

10 = CH3 selected

11 = Reserved

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Input Mux Select 2

Subaddress

1Ah

Default (00h)

7

1

6

5

4

3

2

1

0

Reserved

VSYNC Select

Reserved

HSYNC Select

Bit 7: It must be written to 1.

VSYNC Select:

0 = VSYNC_A selected (default)

1 = VSYNC_B selected

HSYNC Select [1:0]:

0 = HSYNC_A selected (default)

1 = HSYNC_B selected

Blue and Green Coarse Gain

Subaddress

1Bh

Default (55h)

7

6

5

4

3

2

1

0

Green Gain [3:0]

Blue Gain [3:0]

Green Coarse Gain [3:0]: Coarse analog gain for Green channel applied before the ADC.

Gain [3:0] Description

0000 = 0.5

0001 = 0.6

0010 = 0.7

0011 = 0.8

0100 = 0.9

0101 = 1.0

0110 = 1.1

0111 = 1.2

1000 = 1.3

1001 = 1.4

1010 = 1.5

1011 = 1.6

1100 = 1.7

1101 = 1.8

1110 = 1.9

1111 = 2.0

Maximum recommended gain for 700mVp-p input.

Blue Coarse Gain [3:0]: Coarse gain for Blue channel

Red Coarse Gain

Subaddress

1Ch

Default (05h)

0

7

6

5

4

3

2

1

Reserved

Red Gain [3:0]

Red Coarse Gain [3:0]: Coarse analog gain for Red channel applied before the ADC.

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Fine Offset LSB

Subaddress

1Dh

Default (00h)

7

6

5

4

3

2

1

0

Reserved

Red Offset [1:0]

Green Offset [1:0]

Blue Offset [1:0]

Red Offset [1:0] : Offset LSB for red channel. This is LSB of register 0x0D

Green Offset [1:0] : Offset LSB for green channel. This is LSB of register 0x0C

Blue Offset [1:0] : Offset LSB for blue channel. This is LSB of register 0x0B

Blue Coarse Offset

Subaddress

1Eh

Default (20h)

0

7

6

5

4

3

2

1

Reserved

Blue offset [5:0]

Blue Coarse offset [5:0]: Coarse analog offset for blue channel applied before the ADC.

1Fh = +31 LSB (Recommended for optimum ALC performance)

00h = 0 LSB

20h = -1 LSB (default)

3Fh = -32 LSB

Green Coarse Offset

Subaddress

1Fh

Default (20h)

0

7

6

5

4

3

2

1

Reserved

Coarse Green offset [5:0]

Green Coarse offset [5:0]: Coarse analog offset for green channel applied before the ADC.

1Fh = +31 LSB (Recommended for optimum ALC performance)

Red Coarse Offset

Subaddress

20h

Default (20h)

0

7

6

5

4

3

2

Reserved

Coarse Red offset [5:0]

Red Coarse offset [5:0]: Coarse analog offset for blue channel applied before the ADC.

1Fh = +31 LSB (Recommended for optimum ALC performance)

HSOUT Output Start

Subaddress

21h

Default (09h)

0

7

6

5

4

3

2

HSOUT Start [7:0]

HSOUT Start [7:0]: HSYNC output Start pixel number.

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MISC Control

Subaddress

22h

Default (00h)

7

6

5

4

3

2

1

0

Reserved

MAC_EN

Reserved

VS_ALIGN

Reserved

MAC_EN:

0 = Macrovision compatibility disabled (default)

1 = Macrovision compatibility enabled

VS_ALIGN

0 = VSOUT alignment relative to HSOUT varies with SyncSep Threshold

1 = VSOUT alignment not affected by SyncSep Threshold

Automatic Level Control Enable

Subaddress

26h

Default (00h)

0

7

6

5

4

3

2

1

ALC enable

Reserved

ALC enable: Automatic level control enable

0 = Disabled (default)

1 = Enabled

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Automatic Level Control Filter

Subaddress

28h

Default (00h)

7

6

5

4

3

2

1

0

Reserved

NSV[3:0]

NSH [2:0]

The horizonal ALC coefficient (NSH) specifies the number of the horizonal samples (N) used to calculate the average blank level per

horizonal line. Offset error correction is applied immediately based on the vertical (NSV) coefficient.

The vertical coefficient (NSV) specifies the amount of offset error correction (derived from NSH) that is applied to each line update.

NSV [3:0]: ALC vertical filter coefficient

NSV [3:0]

0000 =

0001 =

0010 =

0011 =

0100 =

0101 =

0110 =

0111 =

1000 =

1001 =

1010 =

1011 =

1100 =

1101 =

1110 =

1111 =

Description

1 (default)

1/2

Maximum error correction applied per line update

1/4

1/8

1/16

1/32

1/64

1/128

1/256

1/512

1/1024

1/2048

1/4096

1/8192

1/16384

1/32768

Minimum error correction applied per line update

Minimum number of pixels used in horizonal filter

NSH [2:0]: ALC horizontal sample filter coefficient

NSH [2:0]

000 =

001 =

010 =

011 =

100 =

101 =

110 =

111 =

Description

1 (default)

1/2

1/4

1/8

1/16

1/32

1/64

1/128

Maximum number of pixels used in horizonal filter

29

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

Fine Clamp Control

Subaddress

2Ah

Default (00h)

7

6

5

4

3

2

1

0

Reserved

Fine swsel[1:0]

Fine B

Fine G

Fine R

Fine swsel: Fine clamp time constant adjustment

00 = Highest (default)

01 =

10 =

11 = Lowest

Fine B:

0 = Blue channel fine clamp is off (default)

1 = Blue channel fine clamp is on

Fine G:

0 = Green channel fine clamp is off (default)

1 = Green channel fine clamp is on

Fine R:

0 = Red channel fine clamp is off (default)

1 = Red channel fine clamp is on

Power Control

Subaddress

2Bh

(Default 00h)

7

6

5

4

REF

3

2

1

0

SOG

SLICER

CURRENT

PW ADC B

PW ADC G

PW ADC R

SOG:

0 = Normal operation (default)

1 = SOG power-down

Slicer:

0 = Normal operation (default)

1 = Slicer power-down

Reference:

0 = Normal operation (default)

1 = Reference block power-down

Current control:

0 = Normal operation (default)

1 = Current control block power-down

PW ADC B: Power-down ADC blue channel

0 = PW ADC R: Power-down ADC red channel

1 = ADC channel 1 power-down

PW ADC G: Power-down ADC green channel

0 = PW ADC R: Power-down ADC red channel

1 = ADC channel 2 power-down

PW ADC R: Power-down ADC red channel

0 = PW ADC R: Power-down ADC red channel

1 = ADC channel 3 power-down

30

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

ADC Setup

Subaddress

2Ch

(Default 00h)

7

0

6

1

5

1

4

0

3

0

2

0

1

0

50h = Recommended setting

Coarse Clamp Control

Subaddress

2Dh

Default (00h)

7

6

5

4

3

2

1

0

CCCLP_cur_CH1

Reserved

Coarse B

Coarse G

Coarse R

Coarse clamp charge current switch selection:

00 = Highest (default)

01 =

10 =

11 = Lowest

Course B:

0 = Coarse clamp off at BLUE channel (default)

1 = Coarse clamp on at BLUE channel

Coarse G :

Coarse R :

0 = Coarse clamp off at GREEN channel (default)

1 = Coarse clamp on at GREEN channel

0 = Coarse clamp off at RED channel (default)

1 = Coarse clamp on at RED channel

SOG Clamp

Subaddress

2Eh

(Default 00h)

0

7

6

5

4

3

2

1

SOG_CE

Reserved

SOG_CE:

0 = SOG Clamp disabled (default)

1 = SOG Clamp enabled. Set to 1 for SOG operation.

ALC Placement

Subaddress

31h

(Default 00h)

0

7

6

5

4

3

2

1

ALC placement [7:0]

ALC placement [7:0]:

0 = Default

18h = PC graphics and SDTV with

bi-level syncs

5Ah = HDTV with tri-level syncs

Positions the ALC signal an integer number of clock periods after the HSYNC signal. ALC must be applied after the clamp end.

31

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

32

TVP7000

www.ti.com

SLES143–SEPTEMBER 2005

APPLICATION INFORMATION

1.5 kΩ

0.1 µF

4.7 nF

10 nF

SOG1

GIN1

0.1 µF

G/Y

B/Pb

R/Pr

75 Ω

GOUT[9:0]

BOUT[9:0]

0.1 µF

BIN1

RIN1

ROUT[9:0]

DATACLK

SOGOUT

VSOUT

HSOUT

HSYNC

VSYNC

HSYNC_A

VSYNC_A

RESETB

+3.3 V

2.2 kΩ x 2

2.2 kΩ x 3

Figure 8. TVP7000 Application Example

Schematic

33

PACKAGE OPTION ADDENDUM

www.ti.com

18-Oct-2005

PACKAGING INFORMATION

Orderable Device

TVP7000PZP

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

HTQFP

PZP

100

90 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TVP7000PZPR

HTQFP

PZP

100

1000

TBD

CU NIPDAU Level-4-220C-72 HR

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

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Resale of TI products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products

Applications

Audio

Amplifiers

amplifier.ti.com

www.ti.com/audio

Data Converters

dataconverter.ti.com

Automotive

www.ti.com/automotive

DSP

dsp.ti.com

Broadband

Digital Control

Military

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/military

Interface

Logic

interface.ti.com

logic.ti.com

Power Mgmt

Microcontrollers

power.ti.com

Optical Networking

Security

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

microcontroller.ti.com

Telephony

Video & Imaging

Wireless

www.ti.com/wireless

Mailing Address:

Texas Instruments

Post Office Box 655303 Dallas, Texas 75265


型号：	TVP7000
厂家：	TEXAS INSTRUMENTS
描述：	TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO AND GRAPHICS DIGITIZER WITH ANALOG PLL 888 /10- BIT，一百十分之一百五十零MSPS ，视频和图形数字化仪，模拟PLL
文件：	总37页 (文件大小：310K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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