TVP5200PFP [TI]
COLOR SIGNAL DECODER, PQFP144, POWER, PLASTIC, TQFP-144;
| 型号： | TVP5200PFP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | COLOR SIGNAL DECODER, PQFP144, POWER, PLASTIC, TQFP-144 商用集成电路 |
| 文件： | 总10页 (文件大小：136K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVP5200
ALL FORMAT ANALOG VIDEO DECODER
Product Preview Data Manual
SLES037
PRODUCT PREVIEW 03/06/02
Product Preview documents contain information on products
in the formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Insruments reserves
the right to change or discontinue the products without prior notice.
PRELIMINARY
TEXAS
TVP5200
INSTRUMENTS
All Format Analog Video Decoder
SLES037
PRODUCT PREVIEW 03/06/02
Product Preview documents contain information on products
in the formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Insruments reserves
the right to change or discontinue the products without prior notice.
Page i
PRELIMINARY
TEXAS
TVP5200
INSTRUMENTS
All Format Analog Video Decoder
1 Introduction
TVP5200 is the first, high quality, all format, single-chip digital video decoder that digitizes and decodes base-band analog video
into digital component video. TVP5200 supports the A/D conversion of Standard and High Definition (SD/HD) component RGB
and YPbPr signals from PC and video sources, as well as the decoding of composite NTSC, PAL and SECAM video standards. This
chip uses three high-speed 9-bit 165-MSPS ADCs and a single high-resolution 10-bit 80-MSPS ADC. Prior to the ADC, each
channel contains an analog circuit, which clamps the input to a reference voltage and applies a programmable gain and offset to
amplify the signal to the desired level.
Composite signals are oversampled at either 2x or 4x the square-pixel or ITU-R BT.601 (27- or 54-MHz) clock frequency, line-
locked for correct pixel alignment, and are afterwards decimated. The following output formats can be selected: 20/16- or 10/8-bit
4:2:2 YCbCr, 10/8-bit ITU-R BT.656 with embedded syncs, 12, 30/24 or 48-bit 4:4:4 RGB. The TVP5200 uses Texas Instruments’
patented technology for locking to weak, noisy, or unstable signals, and a genlock chroma frequency control output is generated for
synchronizing downstream video encoders.
Complementary 3-line or 4-line adaptive comb filtering is available for both the luma and chroma data paths to reduce both cross-
luma and cross-chroma artifacts; a chroma trap filter is also available. Video characteristics including hue, contrast, brightness and
saturation may be programmed using one of four supported host port interfaces; I2C and three parallel host interface (PHI) modes.
TVP5200 generates synchronization, blanking, field, lock and clock signals in addition to digital video outputs.
TVP5200 includes methods for advanced vertical blanking interval (VBI) data retrieval. The VBI Data Processor (VDP) slices,
parses, and performs error checking on teletext, closed caption, and other data in several formats. A built-in FIFO stores up to 11
lines of teletext data, and with proper host port synchronization, full-screen teletext retrieval is possible. TVP5200 can pass through
the output formatter 2x sampled raw composite data for host-based VBI processing.
TVP5200 also supports PC RGB graphics (VESA) signals. The device handles pixel rates up to 165 MSPS. Therefore, it can be
used for PC graphics digitizing up to the VESA standard of UXGA (1600x1200) resolution at 60-Hz screen refresh rate
(162-MSPS). The TVP5200 includes auto-phase and auto-frequency detection hardware to allow the development of an algorithm
for automatic sampling phase and frequency detection for any supported PC graphics RGB signal (auto-lock function).
TVP5200 includes:
•
•
•
•
•
•
•
•
•
•
•
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Three High-Speed 9-Bit, 165-MSPS A/D Converters with Analog Pre-Processors
One High-Resolution 10-Bit, 80-MSPS A/D Converter with an Analog Pre-Processor
Y/C Separation by 2D Adaptive Comb and Chroma-Trap Filter
Chrominance Processor
Luminance Processor
Component Processor
Clock/Timing Processor and Power-Down Control
Output Formatter Including Color Space Conversion
Host Port Interface
VBI Data Processor
MacrovisionTM Copy Protection Detection Circuit
JTAG Test Interface
Macrovision is a trademark of Macrovision Corporation. Other trademarks are the property of their respective owners.
SLES037
PRODUCT PREVIEW 03/06/02
Product Preview documents contain information on products
in the formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Insruments reserves
the right to change or discontinue the products without prior notice.
1
Page
PRELIMINARY
TEXAS
TVP5200
INSTRUMENTS
All Format Analog Video Decoder
1.1 Features
•
Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N) and SECAM (B, D, G, K, K1, L) Composite Video Base-Band Signal
(CVBS), S-Video
•
•
•
•
•
Supports Analog Component YPbPr /RGB Video
Supports HDTV/SDTV Formats
Supports PC Graphics RGB Formats up to UXGA (1600x1200) @ 60Hz
16 Analog Video Input Terminals for Multi-Source Connection
User-Programmable Video Output Formats:
•
•
•
12/24/30/48-Bit 4:4:4 RGB
20/16-Bit or 10/8-Bit 4:2:2 YCbCr
10/8-Bit ITU-R BT.656 4:2:2 YCbCr with Embedded Syncs
•
HD/SD/RGB Processing
High-Speed Triple 165-MSPS, 9-Bit A/D Channels for RGB PC Formats (>80MSPS) and Pb/B, Pr/R Video Components
(<80MSPS)
•
•
•
High-Resolution 80-MSPS, 10-Bit A/D Channel for Y Luma or G Component Video
Automatic Frequency, Phase and Mode Detection for RGB
Can Be Bypassed with External Sync/Phase Programming
•
•
•
Four Differential CMOS Analog Preprocessing Channels with Clamping and
AGC for Best S/N Performance
Video Processing
•
•
•
•
Automatic Video Standard Detection (NTSC/PAL/SECAM)
Adaptive 2D 3-Line and 4-Line Comb Filter
High-Resolution Oversampling 10-Bit A/D Converter for Composite, S-Video Luma
Programmable Output Data Rates
•
•
•
12.2727-MHz Square-Pixel (NTSC)
13.5-MHz ITU-R BT.601 (NTSC/ PAL/SECAM)
14.7500-MHz Square-Pixel (PAL)
•
•
Color Space Conversion
Patented Architecture for Locking to Weak, Noisy, or Unstable Signals.
•
•
Single 14.31818- or 27-MHz Reference Crystal for All Standards
Line-Locked Internal Pixel Sampling Clock Generation
SLES037
PRODUCT PREVIEW 03/06/02
Product Preview documents contain information on products
in the formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Insruments reserves
the right to change or discontinue the products without prior notice.
2
Page
PRELIMINARY
TEXAS
TVP5200
INSTRUMENTS
All Format Analog Video Decoder
•
Vertical Blank Interval Data Processor
•
•
•
•
•
•
Teletext (NABTS, WST)
Closed Caption (CC) and Extended Data Service (XDS)
Wide Screen Signaling (WSS)
Video Program System (VPS)
Vertical Interval Time Code (VITC)
Custom Mode
•
Certified Macrovision Copy Protection Detection
2
•
•
•
•
•
Programmable Host Port Options: I C or PHI (3 modes)
Reduced Power Consumption : 1.8-V Digital Core, 3.3-V and 1.8-V Analog Core
Embedded RAM to Allow User-Downloadable Configuration Microcode (Feature Upgrade)
5-V Tolerant Digital I/O Ports
144-Pin TQFP PowerPAD™ Package
1.2 Applications
•
•
•
•
•
•
•
•
•
•
•
Digital TV
LCD Projector/Monitor
DLP Projector
Digital Image Processing
Video Conferencing
Multimedia
Digital Video
Desktop Video
Video Capture
Video Editing
Security Applications
1.3 Related Products
•
•
•
•
TVP6000 NTSC/PAL Digital Video Encoder, Literature Number SLAS184
TVP5145 NTSC/PAL/SECAM 2x10-bit Digital Video Decoder with MacrovisionTM, Literature Number SLES029
TVP5040 NTSC/PAL 2x10 bit Digital Video Decoder with MacrovisionTM, Literature Number SLAS257D
TVP5031 NTSC/PAL 9 bit Digital Video Decoder with MacrovisionTM, Literature Number SLAS267C
PowerPAD is a trademark of Texas Instruments.
SLES037
PRODUCT PREVIEW 03/06/02
Product Preview documents contain information on products
in the formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Insruments reserves
the right to change or discontinue the products without prior notice.
3
Page
PRELIMINARY
TEXAS
TVP5200
INSTRUMENTS
All Format Analog Video Decoder
1.4 Functional Block Diagram
Analog Front End
4A
VBI Data Processor
CPU reg
4B
Clamp/PGA
4C
4D
Composite Processor
CH4 A/D
10 bit ADC
80 MSPS
CVBS/Y
Chroma
Y
luma
processing
1A
1B
1C
1D
UV
chroma
processing
Clamp/PGA
CPU reg
Fast switch
CH1 A/D
9 bit ADC
165 MSPS
2A
2B
2C
2D
Y/G
Y/G
Pb/B
Pr/R
Component
Processor
Output
Formatter
G/YCbCr
Clamp/PGA
B/YCbCr
R/YCbCr
color space
conversion
gain/offset
adjustment
U/B
V/R
9 bit ADC
165 MSPS
CH2 A/D
CPU reg
CPU reg
3A
3B
3C
3D
Clamp/PGA
JTAG Interface
CPU
CH3 A/D
9 bit ADC
165 MSPS
sampling
clock
Host Interface
CPU reg
HSYN
VSYN
FID
HS
VS
Timing Processor
AVID
CPU reg
PALI
DATACLK
SLES037
PRODUCT PREVIEW 03/06/02
Product Preview documents contain information on products
in the formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Insruments reserves
the right to change or discontinue the products without prior notice.
4
Page
PRELIMINARY
TEXAS
TVP5200
INSTRUMENTS
All Format Analog Video Decoder
1.5 Terminal Assignments
144 PIN TQFP PACKAGE
(TOP VIEW)
1
108
107
106
105
104
103
102
101
100
99
V38
CH1_A18VDD
CH1_A18GND
VI_1A
2
V37
3
V36
VI_1B
4
V35
VI_1C
5
V34
VI_1D
6
V33
7
DGND
IOGND
V32
CH1_A33GND
CH1_A33VDD
CH2_A33VDD
CH2_A33GND
VI_2A
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
IOVDD
DVDD
V31
98
VI_2B
97
VI_2C
96
V30
VI_2D
95
V29
94
V28
CH2_A18GND
CH2_A18VDD
A18VDD_REF
A18GND_REF
93
V27
92
V26
91
V25
90
V24
TVP5200PFP
CH3_A18VDD
CH3_A18GND
VI_3A
89
V23
88
V22
87
V21
VI_3B
86
V20
VI_3C
85
V19
VI_3D
84
V18
CH3_A33GND
CH3_A33VDD
83
DGND
IOGND
V17
82
CH4_A18VDD
CH4_A18GND
VI_4A
81
80
IOVDD
DVDD
VI_4B
79
VI_4C
78
V16
V15
VI_4D
77
76
IOGND
V14
CH4_A33GND
CH4_A33VDD
XTAL1
75
74
V13
XTAL2
73
V12
1.6 Ordering Information
PACKAGED DEVICES
144-pin Plastic Flatpack PowerPAD™
TA
0°C to 70°C
TVP5200PFP
SLES037
PRODUCT PREVIEW 03/06/02
Product Preview documents contain information on products
in the formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Insruments reserves
the right to change or discontinue the products without prior notice.
5
Page
PRELIMINARY
TEXAS
TVP5200
INSTRUMENTS
All Format Analog Video Decoder
1.7 Terminal Functions
Terminal
I/O
Description
Name
Analog video
VI_1A
NO.
3
4
5
I
VI_xA: Analog video input
VI_xB: Analog video input
VI_xC: Analog video input
VI_xD: Analog video input
VI_1B
VI_1C
VI_1D
6
VI_2A
VI_2B
VI_2C
VI_2D
VI_3A
VI_3B
VI_3C
VI_3D
VI_4A
VI_4B
VI_4C
VI_4D
11
12
13
14
21
22
23
24
29
30
31
32
For composite video, the luma input is fed to one of the input terminals routed to
channel 4 (10-bit channel); the chroma input can be fed to any other channel (9-bit
channel).
For component video formats up to 80MSPS pixel clock (i.e. all SDTV and HDTV
formats), the Green or Luma input is fed to one of the input terminals routed to
channel 4 (10-bit), while the other video components are fed to the 9-bit channels.
For video/PC graphics formats higher than 80MSPS, all video components should be
fed to the 9-bit channels.
The inputs must be AC coupled. The recommended coupling is 0.1 µF.
Up to sixteen composite, four component or eight S-video inputs (or a combination
thereof) can be supported.
Clock Signals
XTAL1
XTAL2
HS
35
36
44
45
55
I
O
I
I
O
External clock reference input.
External clock reference output. (see Section 2.2.9)
Input horizontal sync (for modes with dedicated Hsync)
Input vertical sync (for modes with dedicated Vsync)
Line locked data output clock (0.5x, 1x, or 2x sample frequency)
VS
DATACLK
Digital Video
V[47:45]
V[44:0]
O / I
O
Digital video output (inputs at power-up)
V[47:45] is used for host port selection at power-up. (see Table 2-3)
JTAG Signals (JTAG interface for manufacturing test purposes only)
TRST
TMS
TCLK
TDI
39
40
41
42
43
I
I
I
I
O
JTAG test port reset
JTAG test port mode select
JTAG test port clock
JTAG test port data in
JTAG test port data out
TDO
Miscellaneous signals
RSTINB
OEB
FAST SWITCH
46
47
48
I
I
I
Reset in, active low
Output enable, active low
Fast Switch. Switching between synchronous YPbPr/ RGB and composite input
video
GLCO
49
O
Genlock Control Output
GPCL/VBLK
139
I/O
Programmable General purpose I/O or vertical blank output
SLES037
PRODUCT PREVIEW 03/06/02
Product Preview documents contain information on products
6
Page
in the formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Insruments reserves
the right to change or discontinue the products without prior notice.
PRELIMINARY
TEXAS
TVP5200
INSTRUMENTS
All Format Analog Video Decoder
Power Supplies
NSUB
144
7
I
I
Substrate ground. Connect to analog ground.
Analog 3.3V return
CH1_A33GND
CH2_A33GND
CH3_A33GND
CH4_A33GND
CH1_A33VDD
CH2_A33VDD
CH3_A33VDD
CH4_A33VDD
CH1_A18GND
CH2_A18GND
CH3_A18GND
CH4_A18GND
CH1_ A18VDD
CH2_ A18VDD
CH3_ A18VDD
CH4_ A18VDD
A18VDD_REF
A18VSS_REF
DGND
10
25
33
8
I
I
I
Analog power. Connect to 3.3V
Analog 1.8V return
9
26
34
2
15
20
28
1
16
19
27
17
18
63,83
Analog power. Connect to 1.8V
I
I
I
Analog power for reference 1.8V
Analog 1.8V return
Digital return
102,117,133
59, 79
DVDD
I
Digital power. Connect to 1.8V
98,113,130
PLL_A18GND
PLL_A18VDD
IO_GND
37
38
62,76,82
101,116
I
I
I
Analog power return
Analog power. Connect to 1.8V.
Digital power return
IO_VDD
60, 69,80
99,114
I
Digital power. Connect to 3.3V or less for reduced noise
HOST PORT
A[1:0]
D[7:0] 129,128,127,126
125,124,123,122
131,132
I
PHI address port
PHI data port
I/O
INTREQ
VC[3:0]
138
137,136
135,134
I/O
I/O
Interrupt request
PHI port control / I2C port (see Section 2.2.11)
Sync Signals
PALI/HLK
50
O
PAL line indicator or horizontal lock indicator
FID/VLK
VSYN/CSYN
HSYN
51
52
53
54
O
O
O
O
Odd/even Field indicator or vertical lock indicator
Vertical sync or composite sync
Horizontal sync
AVID
Active video indicator
Reserved
140,141,142,143
I
Reserved Pins
SLES037
PRODUCT PREVIEW 03/06/02
Product Preview documents contain information on products
in the formative or design phase of development. Characteristic data
and other specifications are design goals. Texas Insruments reserves
the right to change or discontinue the products without prior notice.
7
Page
PRELIMINARY
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