TVP5160PNPG4 [TI]
COLOR SIGNAL DECODER, PQFP128, PLASTIC, HTQFP-128;
| 型号： | TVP5160PNPG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | COLOR SIGNAL DECODER, PQFP128, PLASTIC, HTQFP-128 商用集成电路 |
| 文件： | 总111页 (文件大小：1382K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVP5160
NTSC/PAL/SECAM/Component 2x10-Bit Digital Video
Decoder
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES135E
February 2005–Revised April 2011
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
www.ti.com
Contents
1
Introduction ........................................................................................................................ 9
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
Features ...................................................................................................................... 9
Applications .................................................................................................................. 9
Description ................................................................................................................... 9
Related Products .......................................................................................................... 12
Trademarks ................................................................................................................. 12
Document Conventions ................................................................................................... 12
Ordering Information ...................................................................................................... 12
Functional Block Diagram ................................................................................................ 13
Terminal Assignments .................................................................................................... 14
2
Functional Description ....................................................................................................... 17
Analog Processing and A/D Converters ................................................................................ 17
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
Video Input Switch Control .................................................................................... 18
480p and 576p Component YPbPr ........................................................................... 18
Analog Input Clamping ......................................................................................... 18
Automatic Gain Control ........................................................................................ 18
Analog Video Output ........................................................................................... 18
A/D Converters .................................................................................................. 19
2.2
Digital Video Processing .................................................................................................. 19
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
2x Decimation Filter ............................................................................................ 19
Composite Processor .......................................................................................... 19
Color Low-Pass Filter .......................................................................................... 19
Y/C Separation .................................................................................................. 20
3D Frame Recursive Noise Reduction ....................................................................... 20
Time Base Corrector ........................................................................................... 20
IF Compensation ............................................................................................... 20
Luminance Processing ......................................................................................... 21
Color Transient Improvement ................................................................................. 21
2.3
2.4
2.5
2.6
2.7
Clock Circuits .............................................................................................................. 22
Real-Time Control (RTC) ................................................................................................. 22
Output Formatter .......................................................................................................... 23
Fast Switches for SCART and Digital Overlay ........................................................................ 24
Discrete Syncs ............................................................................................................. 26
2.8
2.9
Embedded Syncs .......................................................................................................... 31
I2C Host Interface .......................................................................................................... 32
2.9.1
Reset and I2C Bus Address Selection ....................................................................... 32
I2C Operation .................................................................................................... 33
VBUS Access ................................................................................................... 33
2.9.2
2.9.3
2.9.3.1 VBUS Write ......................................................................................... 34
2.9.3.2 VBUS Read ......................................................................................... 34
2.10 VBI Data Processor ....................................................................................................... 34
2.10.1 VBI FIFO and Ancillary Data in Video Stream .............................................................. 35
2.10.2 VBI Raw Data Out .............................................................................................. 36
2.11 Powerup, Reset, and Initialization ....................................................................................... 36
2.12 Adjusting External Syncs ................................................................................................. 37
2
Contents
Copyright © 2005–2011, Texas Instruments Incorporated
TVP5160
www.ti.com
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
3
4
Internal Control Registers ................................................................................................... 38
3.1
Register Definitions ........................................................................................................ 43
VBUS Register Definitions ............................................................................................... 88
3.2
Typical Application Circuit .................................................................................................. 95
Typical Application Circuit ................................................................................................ 95
4.1
5
6
Typical Register Programming Sequence ............................................................................. 96
Electrical Specifications ..................................................................................................... 97
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Absolute Maximum Ratings .............................................................................................. 97
Recommended Operating Conditions .................................................................................. 97
Crystal Specifications ..................................................................................................... 98
DC Electrical Characteristics ............................................................................................. 98
Analog Processing and A/D Converters ................................................................................ 99
Data Clock, Video Data, Sync Timing .................................................................................. 99
I2C Host Port Timing ..................................................................................................... 100
SDRAM Timing ........................................................................................................... 101
Example SDRAM Timing Alignment ................................................................................... 102
6.10 Memories Tested ......................................................................................................... 103
6.11 Thermal Specification ................................................................................................... 103
7
8
Designing With PowerPAD™ ............................................................................................. 104
Revision History .............................................................................................................. 106
Copyright © 2005–2011, Texas Instruments Incorporated
Contents
3
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
www.ti.com
List of Figures
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
3-1
4-1
6-1
6-2
6-3
6-4
7-1
TVP5160 PNP-Package Terminal Diagram .................................................................................. 15
Analog Processors and A/D Converters ...................................................................................... 18
Luminance Edge-Enhancer Peaking Block ................................................................................... 21
Peaking Filter Frequency Response NTSC/PAL ITU_R BT.601 Sampling............................................... 21
Reference Clock Configuration ................................................................................................. 22
RTC Timing ....................................................................................................................... 23
Fast-Switches for SCART and Digital Overlay ............................................................................... 25
Vertical Synchronization Signals for 525-Line System ...................................................................... 28
Vertical Synchronization Signals for 625-Line System ...................................................................... 28
Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode.................................................................. 29
Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode.................................................................. 30
VS Position With Respect to HS for Interlaced Signals ..................................................................... 31
VS Position With Respect to HS for Progressive Signals................................................................... 31
VBUS Access ..................................................................................................................... 33
Reset Timing...................................................................................................................... 37
Teletext Filter Function .......................................................................................................... 80
Application Example ............................................................................................................. 95
Clocks, Video Data, and Sync Timing ....................................................................................... 100
I2C Host Port Timing............................................................................................................ 100
SDRAM Interface Timing ...................................................................................................... 101
TVP5160 Timing Relationship with K4S161622E-80 SDRAM............................................................ 102
128-Pin PowerPAD Package.................................................................................................. 105
4
List of Figures
Copyright © 2005–2011, Texas Instruments Incorporated
TVP5160
www.ti.com
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
List of Tables
1-1
Terminal Functions .............................................................................................................. 15
Y/C Separation Support by Video Standard .................................................................................. 20
Output Format .................................................................................................................... 23
Summary of Line Frequency, Data Rate, and Pixel/Line Counts .......................................................... 24
Fast-Switch Modes............................................................................................................... 25
Look-Up Table for Converting from Digital RGB to 10-Bit YCbCr Data................................................... 26
EAV and SAV Sequence........................................................................................................ 32
I2C Host Interface Terminal Description....................................................................................... 32
I2C Host Interface Device Addresses.......................................................................................... 32
Supported VBI System .......................................................................................................... 34
Ancillary Data Format and Sequence ......................................................................................... 35
Reset Sequence.................................................................................................................. 36
I2C Registers Summary.......................................................................................................... 38
VBUS Registers Summary...................................................................................................... 42
Input/Output Select .............................................................................................................. 43
Analog Channel and Video Mode Selection .................................................................................. 43
AFE Gain Control ................................................................................................................ 44
Video Standard Select .......................................................................................................... 44
Operation Mode .................................................................................................................. 44
Autoswitch Mask ................................................................................................................. 45
Color Killer ........................................................................................................................ 45
Luminance Processing Control 1 .............................................................................................. 46
Luminance Processing Control 2 .............................................................................................. 46
Luminance Processing Control 3 .............................................................................................. 47
Luminance Brightness .......................................................................................................... 47
Luminance Contrast ............................................................................................................. 47
Chrominance Saturation ........................................................................................................ 48
Chroma Hue ...................................................................................................................... 48
Chrominance Processing Control 1 ........................................................................................... 49
Chrominance Processing Control 2 ........................................................................................... 50
R/Pr Saturation .................................................................................................................. 50
G/Y Saturation ................................................................................................................... 50
B/Pb Saturation .................................................................................................................. 51
G/Y Brightness ................................................................................................................... 51
AVID Start Pixel .................................................................................................................. 51
AVID Stop Pixel .................................................................................................................. 52
HS Start Pixel .................................................................................................................... 52
HS Stop Pixel .................................................................................................................... 52
VS Start Line ..................................................................................................................... 52
VS Stop Line ..................................................................................................................... 53
VBLK Start Line .................................................................................................................. 53
VBLK Stop Line .................................................................................................................. 53
Embedded Sync Offset Control 1 ............................................................................................. 53
Embedded Sync Offset Control 2 ............................................................................................. 54
Fast-Switch Control ............................................................................................................. 54
Fast-Switch Overlay Delay ..................................................................................................... 55
Fast-Switch SCART Delay ..................................................................................................... 55
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
3-24
3-25
3-26
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-34
3-35
Copyright © 2005–2011, Texas Instruments Incorporated
List of Tables
5
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
www.ti.com
3-36
3-37
3-38
3-39
3-40
3-41
3-42
3-43
3-44
3-45
3-46
3-47
3-48
3-49
3-50
3-51
3-52
3-53
3-54
3-55
3-56
3-57
3-58
3-59
3-60
3-61
3-62
3-63
3-64
3-65
3-66
3-67
3-68
3-69
3-70
3-71
3-72
3-73
3-74
3-75
3-76
3-77
3-78
3-79
3-80
3-81
3-82
3-83
Overlay Delay .................................................................................................................... 55
SCART Delay .................................................................................................................... 56
CTI Control ....................................................................................................................... 56
Brightness and Contrast Range Extender .................................................................................... 56
Component Autoswitch Mask .................................................................................................. 57
Sync Control ..................................................................................................................... 57
Output Formatter Control 1 ..................................................................................................... 58
Output Formatter Control 2 ..................................................................................................... 58
Output Formatter Control 3 ..................................................................................................... 59
Output Formatter Control 4 ..................................................................................................... 59
Output Formatter Control 5 ..................................................................................................... 60
Output Formatter Control 6 ..................................................................................................... 60
Clear Lost Lock Detect .......................................................................................................... 61
Status 1 ........................................................................................................................... 61
Status 2 ........................................................................................................................... 62
AGC Gain Status ................................................................................................................ 62
Video Standard Status .......................................................................................................... 63
GPIO Input 1 ..................................................................................................................... 63
GPIO Input 2 ..................................................................................................................... 64
Back End AGC Status 1 ........................................................................................................ 64
AFE Coarse Gain for CH 1 ..................................................................................................... 64
AFE Coarse Gain for CH 2 ..................................................................................................... 65
AFE Coarse Gain for CH 3 ..................................................................................................... 65
AFE Coarse Gain for CH 4 ..................................................................................................... 65
AFE Fine Gain for B/Pb ......................................................................................................... 66
AFE Fine Gain for G/Y/Chroma ............................................................................................... 66
AFE Fine Gain for R/Pr ......................................................................................................... 66
AFE Fine Gain for CVBS/Luma ................................................................................................ 67
656 Version ....................................................................................................................... 67
SDRAM Control .................................................................................................................. 67
3DNR Y Noise Sensitivity ...................................................................................................... 68
3DNR UV Noise Sensitivity .................................................................................................... 68
3DNR Y Coring Threshold Limit ............................................................................................... 68
3DNR UV Coring Threshold Limit ............................................................................................. 68
3DNR Low Noise Limit .......................................................................................................... 68
"Blue" Screen Y Control ........................................................................................................ 68
"Blue" Screen Cb Control ....................................................................................................... 68
"Blue" Screen Cr Control ....................................................................................................... 69
"Blue" Screen LSB Control ..................................................................................................... 69
Noise Measurement ............................................................................................................. 69
3DNR Y Core0 ................................................................................................................... 69
3DNR UV Core0 ................................................................................................................. 69
F- and V-Bit Decode Control ................................................................................................... 70
Back-End AGC Control ......................................................................................................... 71
AGC Decrement Speed ......................................................................................................... 71
ROM Version ..................................................................................................................... 71
RAM Version MSB .............................................................................................................. 71
AGC White Peak Processing .................................................................................................. 72
6
List of Tables
Copyright © 2005–2011, Texas Instruments Incorporated
TVP5160
www.ti.com
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
3-84
3-85
3-86
3-87
3-88
3-89
3-90
3-91
3-92
3-93
3-94
3-95
3-96
3-97
3-98
3-99
F-Bit and V-Bit Control .......................................................................................................... 72
AGC Increment Speed .......................................................................................................... 73
AGC Increment Delay ........................................................................................................... 73
Analog Output Control 1 ........................................................................................................ 73
Chip ID MSB ..................................................................................................................... 73
Chip ID LSB ...................................................................................................................... 73
RAM Version LSB ............................................................................................................... 74
Color PLL Speed Control ....................................................................................................... 74
3DYC Luma Coring LSB ........................................................................................................ 74
3DYC Chroma Coring LSB ..................................................................................................... 74
3DYC Luma/Chroma Coring MSB ............................................................................................ 74
3DYC Luma Gain ................................................................................................................ 75
3DYC Chroma Gain ............................................................................................................. 75
3DYC Signal Quality Gain ...................................................................................................... 75
3DYC Signal Quality Coring .................................................................................................... 75
IF Compensation Control ....................................................................................................... 76
3-100 IF Differential Gain Control ..................................................................................................... 76
3-101 IF Low Frequency Gain Control ............................................................................................... 76
3-102 IF High Frequency Gain Control ............................................................................................... 76
3-103 Weak Signal High Threshold ................................................................................................... 76
3-104 Weak Signal High Threshold ................................................................................................... 77
3-105 Status Request .................................................................................................................. 77
3-106 3DYC NTSC VCR Threshold .................................................................................................. 77
3-107 3DYC PAL VCR Threshold ..................................................................................................... 77
3-108 Vertical Line Count .............................................................................................................. 77
3-109 AGC Decrement Delay ......................................................................................................... 78
3-110 VDP TTX Filter and Mask ...................................................................................................... 78
3-111 VDP TTX Filter Control ......................................................................................................... 79
3-112 VDP FIFO Word Count ......................................................................................................... 80
3-113 VDP FIFO Interrupt Threshold ................................................................................................. 81
3-114 VDP FIFO Reset ................................................................................................................. 81
3-115 VDP FIFO Output Control ...................................................................................................... 81
3-116 VDP Line Number Interrupt .................................................................................................... 81
3-117 VDP Pixel Alignment ............................................................................................................ 82
3-118 VDP Line Start ................................................................................................................... 82
3-119 VDP Line Stop ................................................................................................................... 82
3-120 VDP Global Line Mode ......................................................................................................... 82
3-121 VDP Full Field Enable .......................................................................................................... 82
3-122 VDP Full Field Mode ............................................................................................................ 83
3-123 Interlaced/Progressive Status .................................................................................................. 83
3-124 VBUS Data Access with No VBUS Address Increment .................................................................... 83
3-125 VBUS Data Access with VBUS Address Increment ........................................................................ 83
3-126 VDP FIFO Read Data ........................................................................................................... 83
3-127 VBUS Address ................................................................................................................... 84
3-128 Interrupt Raw Status 0 .......................................................................................................... 84
3-129 Interrupt Raw Status 1 .......................................................................................................... 85
3-130 Interrupt Status 0 ................................................................................................................ 85
3-131 Interrupt Status 1 ................................................................................................................ 86
Copyright © 2005–2011, Texas Instruments Incorporated
List of Tables
7
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
www.ti.com
3-132 Interrupt Mask 0 ................................................................................................................. 86
3-133 Interrupt Mask 1 ................................................................................................................. 86
3-134 Interrupt Clear 0 ................................................................................................................. 87
3-135 Interrupt Clear 1 ................................................................................................................. 87
3-136 VDP Closed Caption Data ...................................................................................................... 88
3-137 VDP WSS/CGMS Data ......................................................................................................... 88
3-138 VDP VITC Data .................................................................................................................. 89
3-139 VDP V-Chip TV Rating Block 1 ................................................................................................ 89
3-140 VDP V-Chip TV Rating Block 2 ................................................................................................ 89
3-141 VDP V-Chip TV Rating Block 3 ................................................................................................ 90
3-142 VDP V-Chip MPAA Rating Data ............................................................................................... 90
3-143 VDP General Line Mode and Line Address .................................................................................. 91
3-144 VDP VPS, Gemstar EPG Data ................................................................................................ 92
3-145 Analog Output Control 2 ........................................................................................................ 93
3-146 Interrupt Configuration .......................................................................................................... 93
3-147 Interrupt Raw Status 1 .......................................................................................................... 93
3-148 Interrupt Status 1 ................................................................................................................ 94
3-149 Interrupt Mask 1 ................................................................................................................. 94
3-150 Interrupt Clear 1 ................................................................................................................. 94
6-1
Memories Tested ............................................................................................................... 103
Revision History................................................................................................................. 106
8-1
8
List of Tables
Copyright © 2005–2011, Texas Instruments Incorporated
TVP5160
www.ti.com
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
NTSC/PAL/SECAM/Component 2x10-Bit Digital Video Decoder
Check for Samples: TVP5160
1
Introduction
1.1 Features
1
• Two 11-Bit 60-MSPS Analog-to-Digital (A/D)
Converters With Analog Preprocessors
(Clamp/AGC)
• Fast Switch 4x Oversampled Input for Digital
RGB Overlay Switching Between Any CVBS,
S-Video, or Component Video Input
• Fixed RGB-to-YUV Color Space Conversion
• Robust Sync Detection for Weak and Noisy
• SCART 4x Oversampled Fast Switching
Between Component RGB Input and CBVS
Input
Signals as Well as VCR
• Analog Video Output
• Chrominance Processor
• Luminance Processor
• Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I,
M, N, Nc, 60) and SECAM (B, D, G, K, K1, L)
CVBS, S-Video
• Supports Component Standards 480i, 576i,
• Clock/Timing Processor and Power-Down
480p, and 576p
Control
• Supports ITU-R BT.601 Pixel Sampling
• Output Formatter Supports Both ITU-R BT.656
(Embedded Syncs) and ITU-R BT.601 (4:2:2
With Discrete Syncs)
Frequencies
• Supports 3D Y/C Separation, or 2D 5-Line (5H)
Adaptive Comb and Chroma Trap Filter for
Both PAL and NTSC Signals
• Concurrent Temporal, Frame Recursive, Noise
Reduction (3DNR)
• IF Compensation
• I2C Host Port Interface
• VBI Data Processor
• "Blue" Screen (Programmable Color) Output
• Macrovision™ Copy Protection Detection
Circuit (Types 1, 2, and 3) on Both Interlaced
and Progressive Signals
• Line-Based Time Base Correction (TBC)
1.2 Applications
•
•
•
•
•
•
•
Digital TV
LCD TV/Monitors
DVD-R
PVR
PC Video Cards
Video Capture/Video Editing
Video Conferencing
1.3 Description
The TVP5160 device is a high quality, digital video decoder that digitizes and decodes all popular
baseband analog video formats into digital component video. The TVP5160 decoder supports the A/D
conversion of component YPbPr and RGB (SCART) signals, as well as the A/D conversion and decoding
of NTSC, PAL, and SECAM composite and S-Video into component YCbCr. Additionally, component
progressive signals can be digitized. The chip includes two 11-bit, 60-MSPS, A/D converters (ADCs). Prior
to each ADC, each analog channel contains an analog circuit, which clamps the input to a reference
voltage and applies a programmable gain and offset. A total of 12 video input terminals can be configured
to a combination of YPbPr, RGB, CVBS, and S-Video video inputs.
Progressive component signals are sampled at 2× clock frequency (54 MHz) and are then decimated to
the 1× rate. In SCART mode the component inputs and the CVBS inputs are sampled at 54 MHz
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2011, Texas Instruments Incorporated
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
www.ti.com
alternately, then decimated to the 1× rate. Composite or S-Video signals are sampled at 4× the ITU-R
BT.601 clock frequency (54 MHz), line-locked for correct pixel alignment, and are then decimated to the
1× rate. CVBS decoding uses advanced 3D Y/C filtering and 2-dimensional complementary 5-line adaptive
comb filtering for both the luma and chroma data paths to reduce both cross-luma and cross-chroma
artifacts. 3D Y/C color separation may be used on both PAL and NTSC video signals. A chroma trap filter
is also available. On CVBS and Y/C inputs, the user can control video characteristics such as hue,
contrast, brightness, and saturation via an I2C host port interface. Furthermore, luma peaking with
programmable gain is included, as well as a patented color transient improvement (CTI) circuit.
Attenuation at higher frequencies or asymmetrical color subcarrier sidebands are compensated using the
IF compensation block. Frame adaptive noise reduction may be applied to reduce temporal noise on
CVBS, S-Video, or component inputs.
3D noise reduction and 3D Y/C separation may be used at the same time or independently.
The TVP5160 decoder uses Texas Instruments' patented technology for locking to weak, noisy, or
unstable signals and can auto-detect between broadcast quality and VCR-style (nonstandard) video
sources.
The TVP5160 decoder generates synchronization, blanking, field, active video window, horizontal and
vertical syncs, clock, genlock (for downstream video encoder synchronization), host CPU interrupt and
programmable logic I/O signals, in addition to digital video outputs.
The TVP5160 decoder includes methods for advanced vertical blanking interval (VBI) data retrieval. The
VBI data processor (VDP) slices and performs error checking on teletext, closed caption, and other VBI
data. A built-in FIFO stores up to 11 lines of teletext data, and, with proper host port synchronization,
full-screen teletext retrieval is possible. The TVP5160 decoder can pass through the output formatter 2×
sampled raw Luma data for host-based VBI processing.
Digital RGB overlay can be synchronously switched with any video input, with all signals being
oversampled at 4× the pixel rate.
The TVP5160 detailed functionality includes:
•
Two high-speed, 60-MSPS, 11-bit, A/D channels with programmable clamp and gain control
The two ADCs can sample CVBS or S-Video at 54 MHz. YPbPr/RGB is multiplexed between the two
ADCs which sample at 54 MHz giving a channel sampling frequency of 27 MHz.
•
Supports ITU-R BT.601 pixel sampling frequencies.
Supports ITU-R BT.601 sampling for both interlaced and progressive signals.
RGB-to-YUV color space conversion for SCART signals
3D Y/C separation or 2D 5-line (5H) adaptive comb and chroma trap filter
3-frame NTSC and PAL color separation
•
•
•
Temporal frame recursive noise reduction (3DNR)
Frame recursive noise reduction can be applied to interlaced CVBS, S-Video, or component inputs for
interlaced signals. Noise reduction can be used at the same time as 3D Y/C separation. Noise
reduction cannot be applied to progressive video signals.
•
Line-based time base correction (TBC)
Line-based time correction corrects for horizontal phase errors encountered during video decoding up
to ±80 pixels of error. This improves the output video quality from jittery sources such as VCRs. It also
reduces line tearing during video trick modes such as fast forward and rewind.
•
•
IF compensation
Attenuation at higher frequencies or asymmetrical color subcarrier sidebands are compensated using
the IF compensation block
Fast switch 4× oversampling for digital RGB overlay signals for switching between any CVBS, S-Video,
or component video inputs
The fast switch overlay signals (FSO, DR, DG, DB) are oversampled at 4× the pixel clock frequency.
The phase of these signals is used to mix the selected video input format and a digital RGB input to
10
Introduction
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generate an output video stream. This improves the overlay picture quality when the external FSO and
digital RGB signals are generated by an asynchronous source.
•
SCART 4x oversampled fast switching between component RGB input and CBVS input
The SCART overlay control signal (FSS) is oversampled at 4x the pixel clock frequency. The phase of
this signal is used to mix between the CVBS input and the analog RGB inputs. This improves the
analog overlay picture quality when the external FSS and analog video signals are generated by an
asynchronous source.
•
•
Analog video output
Buffered analog output with automatic PGA
Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc, 60), SECAM (B, D, G, K, K1, L), CVBS, and
S-Video
•
•
Twelve analog video input terminals for multi-source connection
User-programmable video output formats
–
–
–
–
–
10-bit ITU-R BT.656 4:2:2 YCbCr with embedded syncs
20-bit 4:2:2 YCbCr with discrete syncs
10-bit 4:2:2 YCbCr with discrete syncs
2× sampled raw VBI data in active video during a vertical blanking period
Sliced VBI data during a horizontal blanking period
•
•
HS/VS outputs with programmable position, polarity, and width and FID (Field ID) output
Composite and S-Video processing
–
Adaptive 3D/2D Y/C separation using 5-line adaptive comb filter for composite video inputs;
chroma-trap available
–
–
–
–
–
Automatic video standard detection and switching (NTSC/PAL/SECAM/progressive)
Luma-peaking with programmable gain
Output data rates either 1× or 2× pixel rate
Patented architecture for locking to weak, noisy, or unstable signals
Single 14.31818-MHz reference crystal for all standards (ITU-R.BT601 sampling, interlaced or
progressive)
–
–
–
Line-locked internal pixel sampling clock generation with horizontal and vertical lock signal outputs
Certified Macrovision copy protection detection on composite and S-Video inputs (NTSC, PAL)
Genlock output (RTC) for downstream video encoder synchronization
•
Vertical blank interval data processor
–
–
–
–
–
–
–
–
–
–
Teletext (NABTS, WST)
Closed caption (CC) and extended data service (XDS)
Wide screen signaling (WSS)
Copy generation management system (CGMS)
Video program system (VPS/PDC)
Vertical interval time code (VITC)
EPG video guide 1×/2× (Gemstar)
V-Chip decoding
Custom mode
Register readback of CC, CGMS, WSS, VPS, VITC, V-Chip, EPG 1× and 2× sliced data, CGMS-A
and RC for progressive signals.
•
•
•
I2C host port interface
"Blue" screen output
Macrovision copy protection detection circuit (types 1, 2, and 3) on both interlaced and progressive
signals
Macrovision detection on standard definition signals of types 1, 2, and 3, and to Revision 1.2 for
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progressive signals
•
•
Reduced power consumption: 1.8-V digital core, 3.3-V and 1.8-V analog core with power-save and
power-down modes
128-TQFP PowerPAD™ package
1.4 Related Products
•
•
•
•
•
•
TVP5146M2
TVP5147M1
TVP5150AM1
TVP5151
TVP5154A
TVP5158
1.5 Trademarks
•
•
•
•
TI and PowerPAD are trademarks of Texas Instruments.
Macrovision is a trademark of Macrovision Corporation.
Gemstar is a trademark of Gemstar-TV Guide International.
Other trademarks are the property of their respective owners
1.6 Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are
listed below:
1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit
binary field.
2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a
12-bit hexadecimal field.
3. All other numbers that appear in this document that do not have either a b or h following the number
are assumed to be decimal format.
4. If the signal or terminal name has a bar above the name (for example, RESETB), then this indicates
the logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
5. RSVD indicates that the referenced item is reserved.
1.7 Ordering Information(1)
PACKAGED DEVICES(2)
TA
PACKAGE OPTION
128-PIN TQFP PowerPAD™
0°C to 70°C
TVP5160PNP
Tray
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
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1.8 Functional Block Diagram
INTREQ
SDA
SCL
Control
Address
Data
GLCO
HS/CS
VS/VBLK
FID
AVID
SCLK
RESETB
PWDN
XOUT
XIN
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1.9 Terminal Assignments
The TVP5160 video decoder is packaged in a 128-terminal PNP PowerPAD package. Figure 1-1 is the
PNP-package terminal diagram. Table 1-1 gives a description of the terminals.
PNP PACKAGE
(TOP VIEW)
PNP PACKAGE
(TOP VIEW)
Y_2
A33GND
A33VDD
VI_1
1
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
Y_3
2
Y_4
3
IOGND
IOVDD
Y_5
VI_2
4
VI_3
5
NC
6
Y_6
VI_4
7
Y_7
VI_5
8
Y_8
VI_6
9
Y_9
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DGND
DVDD
SCLK
GLCO/GPIO/I2CA0
GPIO/I2CA1
A3
A18VDD
A18GND
A18VDD
A18GND
A18GND
A18VDD
VI_7
A2
A1
VI_8
A0
VI_9
A10
NC
BA1
VI_10
VI_11
IOGND
IOVDD
BA0
VI_12
NC
RAS
A33VDD
A33GND
A33GND
A33GND
DGND
SCL
CAS
WE
A4
A5
A6
DGND
DVDD
SDA
INTREQ
Figure 1-1. TVP5160 PNP-Package Terminal Diagram
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Table 1-1. Terminal Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Analog Video
VI_1
VI_2
VI_3
VI_4
VI_5
VI_6
VI_7
VI_8
VI_9
VI_10
VI_11
VI_12
3
4
5
7
8
I
VI_x: analog video inputs
Up to 12 composite, 6 S-Video, or 3 component video inputs (or combinations thereof) can
be
supported. Also, 4-channel SCART is supported.
The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 µF.
The possible input configurations are listed in the input select register 00h.
Unused inputs must be connected to ground through 0.1-µF capacitors.
9
17
18
19
21
22
23
Analog_out
Clock Signals
XIN
127
O
Unbuffered analog video output
121
122
84
I
External clock reference input. It may connected to external oscillator with 1.8-V compatible
clock signal or 14.31818-MHz crystal oscillator.
XOUT
O
O
External clock reference output. Not connected if XTAL1 is driven by an external
single-ended oscillator.
SCLK
Line-locked data output clock
Digital Video
Y[9:0]
87–91,
94–98
O
Digital video output of Y/YCbCr, Y_9 is MSB and Y_0 is LSB. For 8-bit operation, the upper
8 bits must be connected.
C[9:0] / GPIO
101–104,
107–110,
113, 114
I/O
Digital video output of CbCr, C_9 is MSB and C_0 is LSB. These terminals can be
programmable general purpose I/O, or as digital overlay controls. For 8-bit operation, the
upper 8 bits must be connected.
FSO
DB
DG
DR
101
102
103
104
I
I
I
I
Fast-switch overlay between digital RGB and any video input
Digital BLUE input from overlay device
Digital GREEN input from overlay device
Digital RED input from overlay device
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
Miscellaneous Signals
RESETB
PWDN
36
35
I
I
Reset input, active low
Power down input
1 = Power down
0 = Normal mode
GLCO /
GPIO / I2CA0
83
82
I/O
Genlock control output (GLCO). Supports the real-time control (RTC) format. This pin can
also be configured as a general-purpose I/O (GPIO).
During power on reset this pin is sampled along with pin 82 (I2CA1) as an input to determine
the I2C address the device will be configured to. A 10-kΩ resistor pulls this either high (to
IOVDD) or low to select between addresses.
GPIO / I2CA1
I/O
Programmable general purpose I/O
During power on reset this pin is sampled along with pin 83 (I2CA0) as an input to determine
the I2C address the device will be configured to. A 10-kΩ resistor pulls this either high (to
IOVDD) or low to select between addresses.
INTREQ
FSS
32
119
O
I
Interrupt request output (open drain when programmed to be active low)
SCART fast switch input
NC
6, 10, 20, 24
N/A
No internal connection. Connect to AGND through 0.1-µF capacitors for future compatibility.
Host Interface
SDA
31
30
I/O
I/O
I2C data bus
I2C clock input
SCL
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Table 1-1. Terminal Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
Power Supplies
A33GND
1, 26, 27,
P
Analog 3.3-V return. Connect to analog ground.
28, 126, 128
A33VDD
2, 25, 125
12, 14, 15
11, 13, 16
124
P
P
P
P
P
P
Analog power. Connect to analog 3.3-V supply.
Analog 1.8-V return. Connect to analog ground.
Analog power. Connect to analog 1.8-V supply.
Analog power return. Connect to analog ground.
Analog power. Connect to analog 1.8-V supply.
Digital return. Connect to digital ground.
A18GND
A18VDD
PLL18GND
PLL18VDD
123
DGND
29, 34, 48,66,
86, 100,112,
120
DVDD
33, 47, 65,85,
99, 111
P
P
P
Digital core power. Connect to 1.8-V supply.
Digital power return. Connect to digital ground.
Digital I/O power. Connect to digital 3.3-V supply.
IOGND
38, 58, 75,93,
106
IOVDD
37, 57, 74,92,
105
Sync Signals
HS / CS /
GPIO
117
118
116
I/O
I/O
I/O
Horizontal sync output or digital composite sync output
Programmable general purpose I/O
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
VS / VBLK /
GPIO
Vertical sync output. (for modes with dedicated VS) or vertical blanking output
Programmable general purpose I/O
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
FID / GPIO
Odd/even field indicator
Programmable general purpose I/O This pin must be pulled low through a 10-kΩ resistor for
correct device operation.
AVID / GPIO
115
I/O
O
Active video indicator
Programmable general purpose I/O
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
SDRAM Interface
Address[11:0]
61, 77,
SDRAM address bus
62–64,
67–69, 81–78
D[15:0]
WE
49–56, 46–39
I/O
O
SDRAM data bus
70
71
SDRAM write enable
SDRAM CAS enable
CAS
O
RAS
72
O
SDRAM RAS enable
DQM
59
O
SDRAM input/output mask for data
SDRAM bank address
SDRAM 108-MHz clock
BA[1:0]
SDRAM_CLK
76, 73
60
O
O
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2
Functional Description
2.1 Analog Processing and A/D Converters
Figure 2-1 shows a functional diagram of the analog processors and A/D converters (ADCs). This block
provides the analog interface to all video inputs. It accepts up to 12 inputs and performs source selection,
video clamping, video amplification, A/D conversion, and gain and offset adjustments to center the
digitized video signal. The TVP5160 decoder supports one analog video output.
M
U
X
Analog_out
PGA
Clamp
VI_1
M
U
X
Buffer
VI_2
VI_3
ADC
PGA
ADC1 Out
VI_4
M
U
X
Buffer
VI_5
VI_6
Clamp
Clamp
VI_7
M
U
X
Buffer
VI_8
VI_9
ADC
PGA
ADC2 Out
VI_10
M
U
X
Buffer
VI_11
VI_12
Line-Locked
Sampling Clock
Clamp
Figure 2-1. Analog Processors and A/D Converters
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2.1.1 Video Input Switch Control
The TVP5160 decoder has two analog channels that accept up to 12 video inputs. The user can configure
the internal analog video switches via I2C. The 12 analog video inputs can be used for different input
configurations, some of which are:
•
•
•
•
12 CVBS video inputs
4 S-Video inputs and 2 CVBS inputs
3 YPbPr video inputs and 3 CVBS input
2 YPbPr video inputs, 2 S-Video inputs, and 2 CVBS inputs
The input selection is performed by the input select register at I2C subaddress 00h.
2.1.2 480p and 576p Component YPbPr
The TVP5160 decoder supports progressive component video inputs. The YPbPr inputs of the TVP5160
decoder may accept 480p or 576p progressive inputs. The Y channel is fed into one ADC while PbPr are
sampled alternatively by the other ADC.
2.1.3 Analog Input Clamping
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit
provides line-by-line restoration of the video sync level to a fixed dc reference voltage. The selection
between bottom and mid clamp is performed automatically by the TVP5160 decoder.
2.1.4 Automatic Gain Control
The TVP5160 decoder uses two programmable gain amplifiers (PGAs); one per channel. The PGA can
scale a signal with a voltage input compliance of 0.5 VPP to 2.0 VPP to a full-scale, 11-bit, A/D output code
range. A 4-bit code sets the coarse gain with individual adjustment per channel. Minimum gain
corresponds to a code 0x0 (2.0-VPP full-scale input, –6 dB gain) while maximum gain corresponds to code
0xF (0.5-VPP full scale, +6 dB gain). The TVP5160 decoder also has 12-bit fine gain controls for each
channel and applies independently to coarse gain controls. For composite video, the input video signal
amplitude may vary significantly from the nominal level of 1 VPP. The TVP5160 decoder can adjust its
PGA setting automatically: an automatic gain control (AGC) can be enabled and can adjust the signal
amplitude such that the maximum input range of the ADC is reached without clipping. Some nonstandard
video signals contain peak white levels that saturate the ADC. In these cases, the AGC automatically cuts
back gain to avoid clipping. If the AGC is on, then the TVP5160 decoder can read the gain currently being
used.
The TVP5160 AGC comprises the front-end AGC before Y/C separation and the back-end AGC after Y/C
separation. The back-end AGC restores the optimum system gain whenever an amplitude reference, such
as the composite peak (which is only relevant before Y/C separation), forces the front-end AGC to set the
gain too low. The front-end and back-end AGC algorithms can use up to four amplitude references: sync
height, color burst amplitude, composite peak, and luma peak.
The specific amplitude references being used by the front-end and back-end AGC algorithms can be
independently controlled using the AGC white peak processing register located at subaddress 74h. The
TVP5160 gain increment speed and gain increment delay can be controlled using the AGC increment
speed register located at subaddress 78h and the AGC increment delay register located at subaddress
79h, respectively.
2.1.5 Analog Video Output
Any one of the analog input signals is available at the analog video output pin. The signal at this pin must
be buffered by a source follower if it drives a 75-Ω resister. The nominal output voltage is 2 VPP, and the
signal can drive a 75-Ω line when buffered. The magnitude is maintained with a PGA in 16 steps
controlled by the TVP5160 decoder.
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2.1.6 A/D Converters
All ADCs have a resolution of 11 bits and can operate up to 60 MSPS. All A/D channels receive an
identical clock from the on-chip, phase-locked loop (PLL) at a frequency between 24 MHz and 60 MHz. All
ADC reference voltages are generated internally.
2.2 Digital Video Processing
This block receives digitized video signals from the ADCs and performs composite processing for CVBS
and S-Video inputs, YCbCr signal enhancements for CVBS and S-Video inputs. It also generates
horizontal and vertical syncs, and other output control signals such as RTC for CVBS and S-Video inputs.
Additionally, it can provide field identification, horizontal and vertical lock, vertical blanking, and active
video window indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2
with external syncs or 10-bit 4:2:2 with embedded/discrete syncs. The circuit detects pseudo sync pulses,
AGC pulses and color striping in Macrovision-encoded copy protected material. Information present in the
VBI interval can be retrieved and either inserted in the ITU-R.BT656 output as ancillary data or stored in
an internal FIFO for retrieval via the I2C interface.
2.2.1 2x Decimation Filter
All input signals are typically oversampled by a factor of 4 (54 MHz). The A/D outputs first pass through
decimation filters that reduce the data rate to 1× pixel rate. The decimation filter is a half-band filter.
Oversampling and decimation filtering can effectively increase the overall signal-to-noise ratio by 3 dB.
2.2.2 Composite Processor
The TVP5160 digital composite video processing circuit receives a digitized composite or S-Video signal
from the ADCs and performs 2D or 3D Y/C separation (bypassed for S-Video input), chroma demodulation
for PAL/NTSC and SECAM, and YUV signal enhancements.
2.2.3 Color Low-Pass Filter
High filter bandwidth preserves sharp color transitions and produces crisp color boundaries. However, for
nonstandard video sources that have asymmetrical U and V side bands, it is desirable to limit the filter
bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the
three notch filters.
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2.2.4 Y/C Separation
Y/C separation may be done using 3D or 2D adaptive 5-line (5-H delay) comb filters or chroma trap filter
for both NTSC and PAL video standards as shown in Table 2-1. The comb filter can be selectively
bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma notch
filters are used. TI's patented adaptive comb filter algorithm reduces artifacts such as hanging dots at
color boundaries. It detects and properly handles false colors in high-frequency luminance images such as
a multiburst pattern or circle pattern.
Table 2-1. Y/C Separation Support by Video Standard
Video Standard
NTSC-M
2D Y/C
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
3D Y/C
Yes
Yes
Yes
Yes
No
NTSC-J
PAL-B, D, G, H, I
PAL-N
PAL-M
PAL-Nc
No
NTSC-4.43, PAL-60
SECAM
No
No
2.2.5 3D Frame Recursive Noise Reduction
The TI proprietary frame recursive noise reduction or 3DNR reduces the level of noise in CVBS, S-Video,
or component inputs by comparing multiple frames of data and canceling out the resulting noise. The
3DNR uses the same frame buffer memory used by the 3DYC. The 3DNR may function concurrently with
3DYC.
There are various modes of operation for the 3DNR and 3DYC:
MODES
Mode 0
Mode 1
Mode 2
Mode 3
OPERATION
3DYC + 3DNR
3DYC only
MEMORY REQUIRED
4 MBytes
2 MBytes
2D 5-line CF + 3DNR
2D only (default
2 MBytes
None
2.2.6 Time Base Corrector
The time base corrector monitors and corrects for horizontal PLL phase offsets up to ±80 pixels. This
improves video decoder output quality by removing artifacts due to jittery horizontal syncs from broadcast
stations. It also reduces line tearing during VCR trick modes such as fast forward and rewind. 3DYC,
frame recursive noise reduction (3DNR), and time base correction (TBC) can be used simultaneously or
independently. Because TBC does not require any external memory, it can be used in all configurations.
2.2.7 IF Compensation
Attenuation of higher frequencies from the tuners input characteristics or due to channels that are not
correctly tuned can be corrected in the IF compensation block. This block can correct for uneven
sidebands resulting in incorrect and uneven UV demodulation.
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2.2.8 Luminance Processing
The luma component is derived from the composite signal by subtracting the remodulated chroma
information. The luminance signal is then fed to the input of a peaking circuit. Figure 2-2 illustrates the
basic functions of the luminance data path. In the case of S-Video, the luminance signal bypasses the
comb filter or chroma trap filter and is fed to the circuit directly. A peaking filter (edge-enhancer) amplifies
high frequency components of the luminance signal. Figure 2-3 shows the characteristics of the peaking
filter at four different gain settings that are user-programmable by the I2C.
Gain
Peak
Detector
Bandpass
Filter
Peaking
Filter
x
IN
Delay
+
OUT
Figure 2-2. Luminance Edge-Enhancer Peaking Block
Figure 2-3. Peaking Filter Frequency Response NTSC/PAL ITU_R BT.601 Sampling
2.2.9 Color Transient Improvement
Color transient improvement (CTI) enhances horizontal color transients. The color difference signal
transition points are maintained, but the edges are enhanced for signals which have bandwidth limited
color components.
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2.3 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to
drive the PLL. This may be input to the TVP5160 decoder at 1.8-V level on terminal 121 (XIN), or a crystal
of 14.31818-MHz fundamental resonant frequency may be connected across terminals 121 (XIN) and 122
(XOUT). If a parallel resonant circuit is used as shown in Figure 2-4, then the external capacitors must
have following relationship:
CL1 = CL2 = 2CL – CSTRAY
Where,
CSTRAY is the pin capacitance with respect to ground
CL is the crystal load capacitance specified by the crystal manufacturer
Figure 2-4 shows the reference clock configurations. The TVP5160 decoder generates the SCLK signal
used for clocking data.
NOTE
See crystal data sheet for correct loading specifications.
TVP5160
TVP5160
121
122
121
122
14.31818-MHz
1.8-V Clock
XIN
XIN
CL1
14.31818-MHz
Crystal
R
CL2
XOUT
NC
XOUT
Note: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-kΩ resistor
may be used for most crystal types.
Figure 2-4. Reference Clock Configuration
2.4 Real-Time Control (RTC)
Although the TVP5160 decoder is a line-locked system, the color burst information is used to accurately
determine the color subcarrier frequency and phase. This ensures proper operation with nonstandard
video signals that do not follow exactly the required frequency multiple between color subcarrier frequency
and video line frequency. The frequency control word of the internal color subcarrier PLL and the
subcarrier reset bit are transmitted via the terminal 83 (GLCO) for optional use in an end system (for
example, by a video encoder). The frequency control word is a 23-bit binary number. The instantaneous
frequency of the color subcarrier can be calculated from the following equation:
F
CTRL
FPLL
=
× FSCLK
233
where FPLL is the frequency of the subcarrier PLL, FCTRL is the 23-bit PLL frequency control word and
FSCLK is the 2× pixel frequency.
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Valid
Sample
Valid
Sample
Reserved
M
S
B
L
S
B
RTC
Mode
S
R
22
0
18 CLK
1 CLK
45 CLK
23-Bit Fsc PLL Increment
3 CLK
128 CLK
Start
Bit
Figure 2-5. RTC Timing
RTC:
Reset bit (R) is active low
Sequence bit (S) PAL:
1 = (R-Y) line normal
0 = (R-Y) line inverted
NTSC: 1 = no change
2.5 Output Formatter
The output formatter sets how the data is formatted for output on the TVP5160 output buses. Table 2-2
shows the available output modes.
Table 2-2. Output Format
TERMINAL
NAME
TERMINAL
NUMBER
ITU-R BT.656
10-Bit 4:2:2 YCbCr
20-BIT 4:2:2
YCbCr
Y_9
Y_8
Y_7
Y_6
Y_5
Y_4
Y_3
Y_2
Y_1
Y_0
C_9
C_8
C_7
C_6
C_5
C_4
C_3
C_2
C_1
C_0
87
88
Cb9, Y9, Cr9
Cb8, Y8, Cr8
Cb7, Y7, Cr7
Cb6, Y6, Cr6
Cb5, Y5, Cr5
Cb4, Y4, Cr4
Cb3, Y3, Cr3
Cb2, Y2, Cr2
Cb1, Y1, Cr1
Cb0, Y0, Cr0
Y9
Y8
89
Y7
90
Y6
91
Y5
94
Y4
95
Y3
96
Y2
97
Y1
98
Y0
101
102
103
104
107
108
109
110
113
114
Cb9, Cr9
Cb8, Cr8
Cb7, Cr7
Cb6, Cr6
Cb5, Cr5
Cb4, Cr4
Cb3, Cr3
Cb2, Cr2
Cb1, Cr1
Cb0, Cr0
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Table 2-3. Summary of Line Frequency, Data Rate, and Pixel/Line Counts
ACTIVE
PIXELS
PER LINE
COLOR
SUBCARRIER
FREQUENCY (MHz)
PIXELS
STANDARDS
LINES PER PIXEL FREQ
HORIZONTAL
LINE RATE (kHz)
PER LINE
FRAME
(MHz)
ITU-R BT.601 sampling
NTSC-J, M
NTSC-4.43
PAL-M
858
858
858
858
864
864
864
720
720
720
720
720
720
720
525
525
525
525
625
625
625
13.5
13.5
13.5
13.5
13.5
13.5
13.5
3.579545
4.43361875
3.57561149
4.43361875
4.43361875
4.43361875
3.58205625
15.73426
15.73426
15.73426
15.73426
15.625
PAL-60
PAL-B, D, G, H, I
PAL-N
15.625
PAL-Nc
15.625
Dr = 4.406250
Db = 4.250000
SECAM
864
720
625
13.5
15.625
The TVP5160 input-to-output processing delay depends on the operating mode and the video standard.
When 3DYC is enabled, the processing delay is approximately 1 frame and 2-1/3 lines. When 3DYC is
disabled, the processing delay is approximately 2-1/3 lines.
2.6 Fast Switches for SCART and Digital Overlay
The TVP5160 decoder supports the SCART interface used mainly in European audio/video end
equipment to carry mono/stereo audio, composite video, S-Video, and RGB video on the same cable. In
the event that composite video and RGB video are present simultaneously on the video pins assigned to a
SCART interface, the TVP5160 decoder assumes they are pixel synchronous to each other. The timing for
both composite video and RGB video is obtained from the composite source and its derived clock is used
to sample RGB video as well. The fast-switch input pin allows switching between these two input video
sources on a pixel-by-pixel basis. This feature can be used to, for example, overlay RGB graphics for
on-screen display onto decoded CVBS video. The SCART overlay control signals (FSS) are oversampled
at 4× the pixel clock frequency. The phase of this signal is used to mix between the CVBS input and the
analog RGB inputs. This improves the analog overlay picture quality when the external FSS and analog
video signals are generated by an asynchronous source. The TVP5160 decoder has two programmable
delays for component video to compensate for composite comb filter delays and two programmable delays
for digital RGB to compensate AFE and decimation filter delays.
If the overlay output is digital supporting 8 colors of data, the TVP5160 decoder can take digital overlay
inputs using terminals C6, C7, and C8. For this mode, output must be the 10-bit ITU-R BT.656 mode.
Figure 2-6 shows the block diagram of two fast-switches. Table 2-4 shows the fast-switch 1 and 2
controls.
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Y
Y’
Gain/Offset
R
G
B
R’
G’
B’
R”
G”
B”
R’’’
G’’’
B’’’
Color Space
Conversion
D
U
V
UV
UV’
4×
Oversample
Gain
2
Y’’
FSS’
FSO’
FSS
FSO
FSS”
FSO”
D
D
Prog
Delay
Output
Formatter
UV’’
Soft Mix
FSS’’’
FSO’’’
D
SCART/COMP_Y
SCART/COMP_Y’
SCART/COMP_UV’
CVBS_SEP_Y
SCART/COMP_UV
CVBS_SEP_UV
D
= User Prgrammable Delay
Figure 2-6. Fast-Switches for SCART and Digital Overlay
Table 2-4. Fast-Switch Modes
MODES
000
DESCRIPTION
CVBS ↔ SCART
001
CVBS, S_Video ↔ Digital overlay
Component ↔ Digital overlay
(CVBS ↔ SCART) ↔ Digital overlay
(CVBS ↔ Digital overlay) ↔ SCART
CVBS ↔ (SCART ↔ Digital overlay
Composite
010
011
100
101
110
111
No switching
Fast switching of digital RGB input: closed caption decoder output is digital RGB with blanking signal. The
TVP5160 decoder supports this digital RGB input and can do overlay with composite, S-Video, or
component video.
See TI application note SLEA016, TVP5146 SCART and OSD, for more information on SCART overlay
and digital overlay programming.
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Table 2-5. Look-Up Table for Converting from Digital RGB to 10-Bit YCbCr Data
INPUT
OUTPUT
Cb
COLOR
DR
DG
0
DB
0
Y
Cr
BLACK
BLUE
0
0
0
0
1
1
1
1
64
512
960
216
664
360
808
64
512
440
136
64
0
1
164
580
680
324
424
840
940
GREEN
CYAN
1
0
1
1
RED
0
0
960
888
584
512
MAGENTA
YELLOW
WHITE
0
1
1
0
1
1
512
2.7 Discrete Syncs
VS, HS, and VBLK are independently software programmable to a 1× pixel count. This allows any
possible alignment to the internal pixel count and line count. The default settings for a 525-line and
625-line video output are given as an example below. FID changes at the same transient time when the
trailing edge of vertical sync occurs. The polarity of FID is programmable by an I2C interface.
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525-Line
525
1
2
3
4
5
6
7
8
9
10
11
20
21
First Field Video
HS
VS
VS Start
VS Stop
CS
FID
VBLK
VBLK Start
VBLK Stop
283 284
262 263 264 265 266 267 268 269 270 271 272 273
Second Field Video
HS
VS
VS Start
VS Stop
CS
FID
VBLK
VBLK Start
NOTE: Line numbering conforms to ITU-R BT.470.
VBLK Stop
Figure 2-7. Vertical Synchronization Signals for 525-Line System
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625-Line
622 623 624 625
1
2
3
4
5
6
7
8
23
24
25
First Field Video
HS
VS
VS Start
VS Stop
CS
FID
VBLK
VBLK Start
VBLK Stop
310 311 312 313 314 315 316 317 318 319 320 321
336 337 338
Second Field Video
HS
VS
VS Start
VS Stop
CS
FID
VBLK
VBLK Start
A. NOTE: Line numbering conforms to ITU-R BT.470.
VBLK Stop
Figure 2-8. Vertical Synchronization Signals for 625-Line System
ITU-R BT.656 10-bit 4:2:2 Timing with 2× pixel clock reference
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0
SCLK
EAV EAV EAV EAV
SAV SAV SAV SAV
Y[9:0]
Cb
Y
Cr
Y
Horizontal Blanking
Cb0
Y0
Cr0
Y1
1
2
3
4
1
2
3
4
HS Start
HS Stop
HS
A
C
B
D
AVID
AVID Stop
AVID Start
Figure 2-9. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode
SCLK = 2× PIXEL CLOCK(1)
MODE
A
B
C
D
NTSC 601
PAL 601
480p
106
112
106
112
128
128
128
128
42
48
42
48
276
288
276
288
576p
(1) ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference 601 = ITU-R BT.601 timing
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0
SCLK
Y[9:0]
Y
Y
Y
Y
Horizontal Blanking
Horizontal Blanking
Y0
Y1
Y2
Y3
CbCr[9:0]
Cb
Cr
Cb
Cr
Cb0 Cr0 Cb1 Cr1
HS Start
HS Stop
HS
A
C
B
D
AVID
AVID Stop
AVID Start
NOTE: AVID rising edge occurs 4 clock cycles early.
NOTE: AVID rising edge occurs 4 clock cycles early.
Figure 2-10. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode
SCLK = 1X PIXEL CLOCK(1)
MODE
NTSC 601
A
B
C
D
53
56
53
56
64
64
64
64
19
22
19
22
138
144
138
144
PAL 601
480p
576p
(1) 20-bit 4:2:2 timing with 1× pixel clock reference 601 = ITU-R BT.601 timing
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HS
First Field
B/2
B/2
VS
HS
H/2 + B/2
H/2 + B/2
Second Field
VS
Figure 2-11. VS Position With Respect to HS for Interlaced Signals
HS
B/2
B/2
VS
Figure 2-12. VS Position With Respect to HS for Progressive Signals
10-BIT (SCLK = 2× PIXEL CLOCK) 20-BIT (SCLK = 1× PIXEL CLOCK)
MODE(1)
B/2
64
H/2
858
864
858
864
B/2
32
32
32
32
H/2
429
432
NTSC 601 interlaced
PAL 601 interlaced
NTSC 601 progressive
PAL 601 progressive
64
(1) 601 = ITU-R BT.601 timing
2.8 Embedded Syncs
Standard with embedded syncs insert SAV and EAV codes into the data stream on the rising and falling
edges of AVID. These codes contain the V and F bits which also define vertical timing. Table 2-6 shows
the format of the SAV and EAV codes.
H equals 1b always indicates EAV. H equals 0b always indicates SAV. The alignment of V and F to the
line and field counter varies depending on the standard.
The P bits are protection bits:
•
•
•
•
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
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Table 2-6. EAV and SAV Sequence
Y9 (MSB)
Y8
1
Y7
1
Y6
1
Y5
1
Y4
1
Y3
1
Y2
1
Y1
1
Y0
1
Preamble
Preamble
Preamble
Status
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
V
H
P3
P2
P1
P0
0
0
2.9 I2C Host Interface
Communication with the TVP5160 decoder is via an I2C host interface. The I2C standard consists of two
signals, the serial input/output data (SDA) line and input/output clock line (SCL), which carry information
between the devices connected to the bus. A 2-bit control signal (I2CA0/ I2CA1) selects the slave
address. Although an I2C system can be multi-mastered, the TVP5160 decoder can function as a slave
device only. Because SDA and SCL are kept open-drain at logic high output level or when the bus is not
driven, the user must connect SDA and SCL to IOVDD via a pullup resistor on the board. The slave
address select, terminals 83 and 82 (I2CA0 and I2CA1), enables the use of four TVP5160 devices tied to
the same I2C bus, because it controls the two least significant bits of the I2C device address.
Table 2-7. I2C Host Interface Terminal Description
SIGNAL
I2CA0
I2CA1
SCL
TYPE
DESCRIPTION
Slave address selection
Slave address selection
Input clock line
I
I
I/O
I/O
SDA
Input/output data line
2.9.1 Reset and I2C Bus Address Selection
The TVP5160 decoder can respond to four possible chip addresses. The address selection is made at
reset by an externally supplied level on the I2CA0/I2CA1 pins. The TVP5160 decoder samples the level of
terminals 83 and 82 at power up or at the trailing edge of RESETB and configures the I2C bus address bit
A0/A1.
Table 2-8. I2C Host Interface Device Addresses
A6
1
A5
0
A4
1
A3
1
A2
1
A1(I2CA1)(1)
A0 (I2CA0)(1)
R/W
1/0
1/0
1/0
1/0
HEX
0 (default)
0 (default)
B9/B8
BB/BA
BD/BC
BF/BE
1
0
1
1
1
0
1
1
1
0
1
1
0
1
1
1
1
0
1
1
1
(1) To pull up the I2C terminals high, tie to IOVDD via a 2.2-kΩ resistor.
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2.9.2 I2C Operation
Data transfers occur utilizing the following formats.
Read from I2C control registers
receive
data
S
10111000
ACK
subaddress
ACK
S
10111001
ACK
NAK
P
Write to I2C control registers
S
10111000
ACK
subaddress
ACK
send data
ACK
P
S = I2C bus start condition
P = I2C bus stop condition
ACK = Acknowledge generated by the slave
NAK = Acknowledge generated by the master, for multiple byte read master will ACK each
byte except the last byte
Subaddress = Subaddress byte
Data = Data byte
I2C bus address = In the example shown, I2CA0/I2CA1 are in default mode. Write (B8h), Read (B9h)
2.9.3 VBUS Access
The TVP5160 decoder has additional internal registers accessible through an indirect access to an
internal 24-bit address wide VBUS. Figure 2-13 shows the VBUS registers access.
2
I C Registers
VBUS Registers
00h
00 0000h
Host
2
80 051Ch
80 0520h
80 052Ch
80 0600h
I C
CC
WSS/CGMS
VITC
Processor
E0h
VBUS
Data
Line Mode
E1h
E8h
VBUS[23:0]
80 0700h
90 1904h
VPS/Gemstar
FIFO
VBUS
Address
EAh
FFh
FF FFFFh
Figure 2-13. VBUS Access
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2.9.3.1 VBUS Write
Single byte
S
B8
ACK
E8
ACK
ACK
VA0
VA0
ACK
ACK
VA1
VA1
ACK
send data
VA2
ACK
ACK
P
P
S
B8
ACK
E0
Multiple bytes
S
S
B8
ACK
E8
E1
ACK
ACK
VA2
ACK
ACK
P
P
B8
ACK
ACK
send data
ACK
. . .
send data
2.9.3.2 VBUS Read
Single byte
S
S
B8
ACK
ACK
E8
E0
ACK
ACK
VA0
VA0
ACK
ACK
VA1
VA1
ACK
ACK
VA2
ACK
NAK
P
P
B8
S
B9
ACK
read data
Multiple bytes
S
B8
ACK
E8
ACK
S
VA2
ACK
P
P
S
B8
ACK
E1
ACK
B9
ACK
read data MACK
…
read data
NAK
NOTE:
Examples use default I2C address
ACK = Acknowledge generated by the slave
MACK = Acknowledge generated by the master
NAK = No Acknowledge generated by the master
2.10 VBI Data Processor
The TVP5160 VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closed
caption (CC), wide screen signaling (WSS), program delivery control (PDC), vertical interval time code
(VITC), video program system (VPS), copy generation management system (CGMS) data, and electronic
program guide (EPG or Gemstar) 1x/2x. Table 2-9 shows the supported VBI system.
These services are acquired by programming the VDP to enable the reception of one or more VBI data
standard(s) in the vertical blanking interval. The VDP can be programmed on a line-per-line basis to
enable simultaneous reception of different VBI formats, one per line. The results are stored in a FIFO
and/or registers. Because of its high data bandwidth, the teletext results are stored in the FIFO only. The
TVP5160 decoder provides fully decoded V-Chip data to the dedicated registers at subaddresses
800540h through 800543h.
Table 2-9. Supported VBI System
VBI SYSTEM
Teletext WST A
Teletext WST B
Teletext NABTS C
Teletext NABTS D
Closed Caption
Closed Caption
WSS-CGMS
WSS-CGMS
VITC
STANDARD
SECAM
PAL
LINE NUMBER
6–23 (Field 1, 2)
6–22 (Field 1, 2)
10–21 (Field 1, 2)
10–21 (Field 1, 2)
22 (Field 1, 2)
21 (Field 1, 2)
23 (Field 1, 2)
20 (Field 1, 2)
6–22
NUMBER OF BYTES
38
43
NTSC
NTSC-J
PAL
34
35
2
NTSC
PAL
2
14 bits
NTSC
PAL
20 bits
9
9
VITC
NTSC
PAL
10–20
VPS
16
13
2
V-Chip (Decoded)
NTSC
21 (Field 2)
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Table 2-9. Supported VBI System (continued)
VBI SYSTEM
STANDARD
NTSC
NTSC
Any
LINE NUMBER
NUMBER OF BYTES
2
Gemstar EPG 1×
Gemstar EPG 2×
User
5 with frame byte
Programmable
20 bits
Programmable
CGMS-A packet A
CGMS-A packet B
480p
41
40
480p
16 bytes
2.10.1 VBI FIFO and Ancillary Data in Video Stream
Sliced VBI data can be output as ancillary data in the video stream in ITU-R BT.656 mode. VBI data is
output on the Y[9:2] terminals during the horizontal blanking period following the line from which the data
was retrieved. Table 2-10 shows the header format and sequence of the ancillary data inserted into the
video stream. This format also stores any VBI data into the FIFO. The size of the FIFO is 512 bytes.
Therefore, the FIFO can store up to 9 lines of teletext data according to the WSTB standard.
Table 2-10. Ancillary Data Format and Sequence
BYTE NO. Y7(MSB)
Y6
0
Y5
0
Y4
0
Y3
0
Y2
0
Y1
0
Y0 (LSB)
DESCRIPTION
0
1
0
1
0
1
Ancillary data preamble
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
3
NEP
NEP
NEP
EP
EP
EP
0
1
0
DID2
F2
N2
DID1
F1
N1
DID0
F0
N0
Data ID (DID)
4
F5
N5
F4
N4
F3
N3
Secondary data ID (SDID)
Number of 32 bit data (NN)
Internal Data ID0 (IDID0)
Internal Data ID1 (IDID1)
5
6
Video line # [7:0]
7
0
0
0
Data error Match #1 Match #2
Video line # [9:8]
8
Sample 1
Sample 2
Sample 3
Sample 4
Data byte
Data byte
Data byte
Data byte
1st word
9
10
11
.
.
.
.
.
.
Sample m-1
Sample m
CS[7:0]
Data byte
Data byte
Checksum
Fill byte
Nth word
4N+5
4N+6
4N+7
0
0
0
0
0
0
0
0
EP:
Even parity for Y5–Y0
NEP:
DID:
Negated even parity
91h: Sliced data of VBI lines of first field
53h: Sliced data of line 24 to end of first field
55h: Sliced data of VBI lines of second field
97h: Sliced data of line 24 to end of second field
SDID:
NN:
This field holds the data format taken from the line mode register bits [5:0] of the
corresponding line.
Number of Dwords beginning with byte 8 through 4N+7. Note this value is the number of
Dwords where each Dword is 4 bytes.
IDID0:
Transaction video line number [7:0]
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IDID1:
Bit 0/1 – Transaction video line number [9:8]
Bit 2 – Match 2 flag
Bit 3 – Match 1 flag
Bit 4 – 1b if at least one error was detected in the EDC block. 0b if no error was detected.
CS:
Sum of Y7–Y0 of byte 8 through byte 4N+5. For teletext modes, byte 8 is the sync pattern
byte. Byte 9 is Sample 1.
Fill byte:
Fill byte makes a multiple of 4 bytes from byte zero to last fill byte
2.10.2 VBI Raw Data Out
The TVP5160 decoder can output raw A/D video data at twice the sampling rate for external VBI slicing.
This is transmitted as an ancillary data block, although a bit differently from the way the sliced VBI data is
transmitted in the FIFO format as described in Section 3.10.1. The samples are transmitted during the
active portion of the line. VBI raw data uses ITU-R BT 656 format having only luma data. The chroma
samples are replaced by luma samples. The TVP5160 decoder inserts a 4-byte preamble 000h 3FFh
3FFh 180h before data start. There is no checksum byte or fill bytes in this mode.
DATA
NO.
Y9
(MSB)
Y0
(LSB)
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
DESCRIPTION
0
1
2
3
4
0
1
1
0
0
1
1
1
0
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VBI raw data preamble
Sample 1
2× pixel rate
Luma data
(i.e., NTSC 601: n = 1707)
5
⋮
Sample 2
⋮
n–1
N
Sample n–5
Sample n–4
2.11 Powerup, Reset, and Initialization
No specific power-up sequence is required, but all power supplies must be active and stable within 500
ms of each other. Reset may be low during power-up, but must remain low for at least 1 µs after the
power supplies become stable and the crystal begins to oscillate. Alternately, reset may be asserted any
time after power up and a stable crystal oscillation, and must remain asserted for at least 1 µs. Table 2-11
describes the status of the TVP5160 terminals during and immediately after reset.
200 µs must be allowed after reset before commencing I2C operations if the SCL pin is not monitored
during I2C operations
Table 2-11. Reset Sequence
SIGNAL NAME
Y[9:0], SCLK
C[9:0]/GPIO
DURING RESET
RESET COMPLETED
High-impedance
Input
Input
Input
Input
RESETB, PWDN, SDA, SCL, FSS/GPIO,
AVID/GPIO, GLCO/GPIO/I2CA0, HS/CS/GPIO,
VS/VBLK/GPIO, FID/GPIO
Input
INTREQ
Input
Output (open drain)
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200 µs
1 µs
Power
Crystal
RESET
2
I C SDA
Figure 2-14. Reset Timing
After reset has completed, the following sequence of operations must be completed:
1. Write 01h to VBus register 0xB00060
2. Write 01h to VBus register 0xB00063
3. Write 00h to VBus register 0xB00060
2.12 Adjusting External Syncs
The TVP5160 decoder stores values for the positions of the external syncs for two different modes:
•
•
525-line with ITU-R BT.601 sampling
625-line with ITU-R BT.601 sampling
Once the values are stored, they are retained and restored when the signal switches back into one of
these two modes.
The proper sequence to change the external sync positions is:
•
To set NTSC, PAL-M, NTSC 443, PAL 60 (525-line modes):
–
–
Make sure the standard is one of the above 525-line mode formats by forcing the video standard
Set HS, VS, VBLK, and AVID external syncs (register 16h through 24h)
•
To set PAL, PAL-N, SECAM (625-line modes):
–
–
Make sure the standard is one of the above 625-line mode formats by forcing the video standard
Set HS, VS, VBLK, and AVID external syncs (register 16h through 24h)
Once programmed, the values for each mode are retained when the signal switches back into that or other
compatible video standards.
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3
Internal Control Registers
The TVP5160 decoder is initialized and controlled by a set of internal registers that define the operating
parameters of the entire device. Communication between the external controller and the TVP5160
decoder is through a standard I2C host port interface, as described earlier.
Table 3-1 shows the summary of these registers. Detailed programming information for each register is
described in the following sections. Additional registers are accessible through an indirect procedure
involving access to an internal 24-bit address wide VBUS. Table 3-2 shows the summary of VBUS
registers.
Table 3-1. I2C Registers Summary
REGISTER NAME
I2C SUBADDRESS
00h
DEFAULT
00h
R/W(1)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Input/Output Select
AFE Gain Control
Video Standard Select
Operation Mode
Autoswitch Mask
Color Killer
01h
0Fh
00h
02h
03h
00h
04h
23h
05h
10h
Luminance Processing Control 1
Luminance Processing Control 2
Luminance Processing Control 3
Luminance Brightness
Luminance Contrast
Chrominance Saturation
Chroma Hue
06h
00h
07h
00h
08h
00h
09h
80h
0Ah
80h
0Bh
80h
0Ch
00h
Chrominance Processing Control 1
Chrominance Processing Control 2
Reserved(2)
0Dh
00h
0Eh
0Ch
0Fh
Pr Contrast
10h
80h
80h
80h
R/W
R/W
R/W
Y Contrast
11h
Pb Contrast
12h
Reserved(2)
13h
G/Y Brightness
14h
80h
R/W
Reserved(2)
15h
AVID Start Pixel
16h–17h
18h–19h
1Ah–1Bh
1Ch–1Dh
1Eh–1Fh
20h–21h
22h–23h
24h–25h
26h
55h/5Fh
325h/32Fh
00h/07h
40h/47h
004h/001h
007h/004h
001h/26Fh
015h/018h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AVID Stop Pixel
HS Start Pixel
HS Stop Pixel
VS Start Line
VS Stop Line
VBLK Start Line
VBLK Stop Line
Embedded Sync Offset Control 1
Embedded Sync Offset Control 2
Fast Switch Control
Fast Switch Overlay Delay
Fast Switch SCART Delay
Overlay Delay
27h
00h
28h
C0h
29h
17h
2Ah
1Ch
2Bh
12h
(1) R = Read only, W = Write only, R/W = Read and write
(2) Reserved I2C register addresses must not be written to.
38
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Table 3-1. I2C Registers Summary (continued)
REGISTER NAME
I2C SUBADDRESS
DEFAULT
R/W(1)
SCART Delay
Reserved(2)
CTI Control
2Ch
56h
R/W
2Dh
2Eh
00h
00h
00h
R/W
R/W
R/W
Brightness and Contrast Range Extender
Component Autoswitch Mask
Reserved(2)
2Fh
30h
31h
Sync Control
32h
00h
40h
00h
FFh
FFh
FFh
FFh
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Output Formatter 1
Output Formatter 2
Output Formatter 3
Output Formatter 4
Output Formatter 5
Output Formatter 6
Clear Lost Lock Detect
Status 1
33h
34h
35h
36h
37h
38h
39h
3Ah
Status 2
3Bh
R
AGC Gain Status
Reserved(2)
3Ch–3Dh
3Eh
R
Video Standard Status
GPIO Input 1
3Fh
R
R
R
40h
GPIO Input 2
41h
Reserved(2)
42h-43h
44h
Back End AGC Status
Reserved(2)
R
45h
AFE Coarse Gain for CH1
AFE Coarse Gain for CH2
AFE Coarse Gain for CH3
AFE Coarse Gain for CH4
AFE Fine Gain for Pb
AFE Fine Gain for Chroma
AFE Fine Gain for Pr
AFE Fine Gain for CVBS_Luma
Reserved(2)
46h
20h
20h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
47h
48h
20h
49h
20h
4Ah–4Bh
4Ch–4Dh
4Eh–4Fh
50h–51h
52h-56h
57h
900h
900h
900h
900h
656 Version
00h
R/W
Reserved(2)
58h
SDRAM Control
59h
00h
80h
80h
80h
40h
40h
00h
80h
80h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Y Noise Sensitivity
UV Noise Sensitivity
Y coring threshold
UV coring threshold
Low Noise Limit
5Ah
5Bh
5Ch
5Dh
5Eh
"Blue" Screen Y
5Fh
"Blue" Screen Cb
60h
"Blue" Screen Cr
61h
"Blue" Screen LSB
3DNR Noise Measurement LSB
3DNR Noise Measurement MSB
62h
64h
65h
R
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Table 3-1. I2C Registers Summary (continued)
REGISTER NAME
I2C SUBADDRESS
DEFAULT
R/W(1)
Y Core0 (3DNR)
UV Core0 (3DNR)
Reserved(2)
66h
R
R
67h
68h
F and V Bit Decode Control
Reserved(2)
69h
00h
08h
04h
R/W
R/W
6Ah-6Bh
6Ch
Back End AGC Control
Reserved(2)
6Eh
AGC Decrement Speed
ROM Version
6Fh
R/W
R
70h
RAM Version MSB
Reserved(2)
71h
R
72h-73h
74h
AGC White Peak Processing
F and V Bit Control
00h
16h
R/W
R/W
75h
Reserved(2)
76h-77h
78h
AGC Increment Speed
AGC Increment Delay
Analog Output Control 1
CHIP ID MSB
06h
1Eh
00h
51h
60h
R/W
R/W
R/W
R
79h
7Fh
80h
CHIP ID LSB
81h
R
RAM Version MSB
82h
R
Color PLL Speed Control
3DYC Luma Coring LSB
3DYC Chroma Coring LSB
3DYC Chroma/Luma MSBs
3DYC Luma Gain
83h
09h
20h/20h
20h/2Ah
00h/00h
08h/08h
08h/08h
02h/02h
328h/380h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
84h
85h
86h
87h
3DYC Chroma Gain
88h
3DYC Signal Quality Gain
3DYC Signal Quality Coring
IF Compensation Control
IF Differential Gain Control
IF Low Frequency Gain Control
IF High Frequency Gain Control
Reserved(2)
89h
8Ah–8Bh
8Dh
8Eh
22h
8Fh
44h
90h
00h
91h-94h
95h
Weak Signal High Threshold
Weak Signal Low Threshold
Status Request
60h
50h
00h
10h
20h
00h
R/W
R/W
R/W
R/W
R/W
R
96h
97h
3DYC NTSC VCR Threshold
3DYC PAL VCR Threshold
Vertical Line Count
98h
99h
9Ah–9Bh
9Ch-9Dh
9Eh
Reserved(2)
AGC Decrement Delay
Reserved(2)
R/W
9Fh-B0h
B1h
VDP TTX Filter 1 Mask 1
VDP TTX Filter 1 Mask 2
VDP TTX Filter 1 Mask 3
VDP TTX Filter 1 Mask 4
VDP TTX Filter 1 Mask 5
00h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
R/W
B2h
B3h
B4h
B5h
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Table 3-1. I2C Registers Summary (continued)
REGISTER NAME
I2C SUBADDRESS
DEFAULT
00h
R/W(1)
R/W
R/W
R/W
R/W W
R/W
R/W
R
VDP TTX Filter 2 Mask 1
VDP TTX Filter 2 Mask 2
VDP TTX Filter 2 Mask 3
VDP TTX Filter 2 Mask 4
VDP TTX Filter 2 Mask 5
VDP TTX Filter Control
VDP FIFO Word Count
B6h
B7h
00h
B8h
00h
B9h
00h
BAh
00h
BBh
00h
BCh
VDP FIFO Interrupt Threshold
Reserved
BDh
80h
R/W
BEh
VDP FIFO Reset
BFh
00h
00h
R/W
R/W
R/W
R/W
VDP FIFO Output Control
VDP Line Number Interrupt
VDP Pixel Alignment
Reserved
C0h
C1h
00h
C2h–C3h
C4h–D5h
D6h
01Eh
VDP Line Start
06h
1Bh
FFh
00h
FFh
R/W
R/W
R/W
R/W
R/W
R
VDP Line Stop
D7h
VDP Global Line Mode
VDP Full Field Enable
VDP Full Field Mode
Interlaced/Progressive Status
Reserved(2)
D8h
D9h
DAh
DBh
DCh-DFh
E0h
VBUS Data Access with No VBUS Address Increment
VBUS Data Access with VBUS Address Increment
VDP FIFO Read Data
Reserved(2)
R/W
R/W
R
E1h
E2h
E3h-E7h
E8h–EAh
EBh-EFh
F0h
VBUS Address Access
Reserved(2)
00 0000h
R/W
Interrupt Raw Status 0
Interrupt Raw Status 1
Interrupt Status 0
R
R
F1h
F2h
R
Interrupt Status 1
F3h
R
Interrupt Mask 0
F4h
00h
00h
00h
00h
R/W
R/W
R/W
R/W
Interrupt Mask 1
F5h
Interrupt Clear 0
F6h
Interrupt Clear 1
F7h
Reserved(2)
F8h-FFh
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Table 3-2. VBUS Registers Summary
VBUS
SUBADDRESS
REGISTER NAME
DEFAULT
R/W(1)
(2)(3)
Reserved
00 0000h – 80 051Bh
80 051Ch – 80 051Fh
80 0520h – 80 0526h
80 0527h – 80 052Bh
80 052Ch – 80 0534h
80 0535h – 80 053Fh
80 0540h – 80 0543h
80 0544h – 80 05FFh
80 0600h – 80 0611h
80 0612h – 80 06FFh
80 0700h – 80 070Ch
80 070Dh – A0 005Dh
A0 005Eh
VDP Closed Caption Data
VDP WSS/CGMS data
R
R
(2)(3)
Reserved
VDP VITC Data
R
R
(2)(3)
Reserved
VDP V-Chip Data
(2)(3)
Reserved
VDP General Line Mode and Address
FFh, 00h
R/W
R
(2)(3)
Reserved
VDP VPS/Gemstar EPG Data
(2)(3)
Reserved
Analog Output Control 2
B2h
00h
R/W
R/W
(2)(3)
Reserved
A0 005Fh – B0 005Fh
B0 0060h
Interrupt Configuration Register
(2)(3)
Reserved
B0 0062h – B0 0064h
B0 0065h
Interrupt Mask 1
Interrupt Raw Status 1
Interrupt Status 1
Interrupt Clear 1
Reserved(2)(3)
R
R
R
R
B0 0069h
B0 006Dh
B0 0071h
B0 0073h – FF FFFFh
(1) R = Read only, W = Write only, R/W = Read and write
(2) Register addresses not shown in the register map summary are reserved and must not be written to.
(3) Writing to or reading from any value labeled "Reserved" register may cause erroneous operation of the TVP5160 decoder. For registers
with reserved bits, a 0b must be written to reserved bit locations unless otherwise stated.
42
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3.1 Register Definitions
Table 3-3. Input/Output Select
Subaddress 00h
Default
00h
7
6
5
4
3
2
1
0
Input select [7:0]
Twelve input terminals can be configured to support composite, S-Video, and component YPbPr. Only values in Table 3-4 are valid.
NOTE: The video output can be either CVBS, Y, or G.
Table 3-4. Analog Channel and Video Mode Selection
INPUT SELECT [7:0]
MODE
CVBS
INPUT(S) SELECTED
OUTPUT
VI_1
7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
6
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
3
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
0
HEX
00
01
02
04
05
06
08
09
0A
0C
0D
0E
40
41
42
50
51
52
44
45
46
54
55
56
90
91
92
94
95
96
C0
C1
C2
VI_1 (default)
VI_2
VI_2
VI_3
VI_3
VI_4
VI_4
VI_5
VI_5
VI_6
VI_6
VI_7
VI_7
VI_8
VI_8
VI_9
VI_9
VI_10
VI_11
VI_12
VI_10
VI_11
VI_12
S-Video
VI_1(Y), VI_7(C)
VI_1(Y)
VI_2(Y)
VI_3(Y)
VI_1(Y)
VI_2(Y)
VI_3(Y)
VI_4(Y)
VI_5(Y)
VI_6(Y)
VI_4(Y)
VI_5(Y)
VI_6(Y)
VI_1(Y)
VI_2(Y)
VI_3(Y)
VI_4(Y)
VI_5(Y)
VI_6(Y)
VI_1(CVBS)
VI_2(CVBS)
VI_3(CVBS)
VI_2(Y), VI_8(C)
VI_3(Y), VI_9(C)
VI_1(Y), VI_10(C)
VI_2(Y), VI_11(C)
VI_3(Y), VI_12(C)
VI_4(Y), VI_7(C)
VI_5(Y), VI_8(C)
VI_6(Y), VI_9(C)
VI_4(Y), VI_10(C)
VI_5(Y), VI_11(C)
VI_6(Y), VI_12(C)
YPbPr
VI_10(Pb), VI_1(Y), VI_7(Pr)
VI_11(Pb), VI_2(Y), VI_8(Pr)
VI_12(Pb), VI_3(Y), VI_9(Pr)
VI_10(Pb), VI_4(Y), VI_7(Pr)
VI_11(Pb), VI_5(Y), VI_8(Pr)
VI_12(Pb), VI_6(Y), VI_9(Pr)
VI_10(B), VI_4(G), VI_7(R), VI_1(CVBS)
VI_11(B), VI_5(G), VI_8(R), VI_2(CVBS)
VI_12(B), VI_6(G), VI_9(R), VI_3(CVBS)
SCART
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Table 3-5. AFE Gain Control
Subaddress 01h
Default
0Fh
7
6
5
4
3
1
2
1
1
1
0
Reserved
AGC
Bit 3:
Bit 2:
Bit 1:
AGC:
1b must be written to this bit
1b must be written to this bit
1b must be written to this bit
Controls automatic gain
0 = Manual
1 = Enable auto gain (default)
This setting only affects the analog front-end (AFE). The brightness and contrast controls are not affected by these settings.
Table 3-6. Video Standard Select
Subaddress 02h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Video standard [3:0]
Video standard [3:0]:
CVBS and S-Video
Component video
Autoswitch mode (default)
Interlaced 525 (480i)
Interlaced 625 (576i)
Reserved
0000 = Autoswitch mode (default)
0001 = (M, J) NTSC
0010 = (B, D, G, H, I, N) PAL
0011 = (M) PAL
0100 = (Combination-N) PAL
0101 = NTSC 4.43
Reserved
Reserved
0110 = SECAM
Reserved
0111 = PAL 60
Reserved
1000 = Reserved
Reserved
1001 = Reserved
NTSC Progressive 525 (480p)
PAL Progressive 625 (576p)
1010 = Reserved
The user can force the device to operate in a particular video standard mode by writing the appropriate value into this register. Changing
these bits will cause some register settings to be reset to their defaults.
Table 3-7. Operation Mode
Subaddress 03h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Power save
Power save
0 = Normal operation (default)
1 = Power save mode. Reduces the clock speed of the internal processor and switches off the ADCs. I2C interface is active and all
current operating settings are preserved.
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Table 3-8. Autoswitch Mask
Subaddress 04h
Default
23h
7
6
5
4
3
2
1
0
Reserved
PAL 60
SECAM
NTSC 4.43
(Nc) PAL
(M) PAL
PAL
(M, J) NTSC
Autoswitch mode mask: Limits the video formats between which autoswitch is possible. See register 30h for masking the progressive
modes.
PAL 60
0 = Autoswitch does not include PAL 60 (default)
1 = Autoswitch includes PAL 60
SECAM
0 = Autoswitch does not include SECAM
1 = Autoswitch includes SECAM (default)
NTSC 4.43
0 = Autoswitch does not include NTSC 4.43 (default)
1 = Autoswitch includes NTSC 4.43
(Nc) PAL
0 = Autoswitch does not include (Nc) PAL (default)
1 = Autoswitch includes (Nc) PAL
(M) PAL
0 = Autoswitch does not include (M) PAL (default)
1 = Autoswitch includes (M) PAL
PAL
0 = Reserved
1 = Autoswitch includes (B, D, G, H, I, N) PAL (default)
(M, J) NTSC
0 = Reserved
1 = Autoswitch includes (M, J) NTSC (default)
Note: Bits 1 and 0 must always be 11b.
Table 3-9. Color Killer
Subaddress 05h
Default
10h
7
6
5
4
3
2
1
0
Reserved
Automatic color killer
Color killer threshold [4:0]
Automatic color killer:
00 = Automatic mode (default)
01 = Reserved
10 = Color killer enabled, the UV terminals are forced to a zero color state
11 = Color killer disabled
Color killer threshold [4:0]:
11111 = 31 (maximum)
10000 = 16 (default)
00000 = 0 (minimum)
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Table 3-10. Luminance Processing Control 1
Subaddress 06h
Default 00h
7
6
5
4
3
2
1
0
Reserved
Pedestal
Reserved
VBI raw
Reserved
Luminance signal delay [2:0]
Pedestal:
0 = 7.5 IRE pedestal is present on the analog video input signal (default)
1 = Pedestal is not present on the analog video input signal
VBI raw:
0 = Disable (default)
1 = Enable
During the duration of the vertical blanking as defined by VBLK start and stop registers 22h through 25h, the chroma samples are replaced
by luma samples. This feature may be used to support VBI processing performed by an external device during the vertical blanking interval.
To use this bit, the output format must be the 10-bit, ITU-R BT.656 mode.
Luminance signal delay [2:0]: Luminance signal delays respect to chroma signal in 1× pixel clock increments.
011 = 3 pixel clocks delay
010 = 2 pixel clocks delay
001 = 1 pixel clock delay
000 = 0 pixel clock delay (default)
111 = –1 pixel clock delay
110 = –2 pixel clocks delay
101 = –3 pixel clocks delay
100 = 0 pixel clock delay
Table 3-11. Luminance Processing Control 2
Subaddress 07h
Default
00h
7
6
5
4
3
2
1
0
Luma filter select [1:0]
Reserved
Peaking gain [1:0]
Reserved
Luma filter selected [1:0]:
00 = Luminance adaptive comb enable (default on CVBS and SECAM)
01 = Luminance adaptive comb disable (trap filter selected)
10 = Luma comb/trap filter bypassed (default on S-Video, component mode)
11 = Reserved
Peaking gain [1:0]:
00 = 0 (default)
01 = 0.5
10 = 1
11 = 2
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Table 3-12. Luminance Processing Control 3
Subaddress 08h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Trap filter select [1:0]
Trap filter select[1:0] selects one of the four trap filters to produce the luminance signal by removing the chrominance signal from the
composite video signal. The stop band of the chroma trap filter is centered at the chroma subcarrier frequency with stopband bandwidth
controlled by the two control bits. Changing this register will trade luma resolution for dot crawl.
Trap filter stop band bandwidth (MHz):
Filter select [1:0]
NTSC ITU-R 601
1.2129
PAL ITU-R 601
1.2129
00 (default)
01
10
11
0.8701
0.8701
0.7183
0.7383
0.5010
0.5010
Table 3-13. Luminance Brightness
Subaddress 09h
Default
80h
7
6
5
4
3
2
1
0
Brightness [7:0]
Brightness [7:0]: This register works for CVBS and S-Video luminance. See subaddress 2Fh.
0000 0000 = 0 (dark)
1000 0000 = 128 (default)
1111 1111 = 255 (bright)
For composite and S-Video outputs, the output black level relative to the nominal black level (64 out of 1024) as a function of the
Brightness[7:0] setting is as follows.
Black Level = nominal_black_level + (MB + 1) × (Brightness[7:0] - 128)
Where MB is the brightness multiplier setting in the Brightness and Contrast Range Extender register at I2C subaddress 2Fh.
Table 3-14. Luminance Contrast
Subaddress 0Ah
Default
80h
7
6
5
4
3
2
1
0
Contrast [7:0]
Contrast [7:0]: This register works for CVBS and S-Video luminance. See subaddress 2Fh.
0000 0000 = 0 (minimum contrast)
1000 0000 = 128 (default)
1111 1111 = 255 (maximum contrast)
For composite and S-Video outputs, the total luminance gain relative to the nominal luminance gain as a function of the Contrast [7:0]
setting is as follows.
Luminance Gain = (nominal_luminance_gain) × [Contrast[7:0] / 64 / (2^MC) + MC - 1]
Where MC is the contrast multiplier setting in the Brightness and Contrast Range Extender register at I2C subaddress 2Fh.
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Table 3-15. Chrominance Saturation
Subaddress 0Bh
Default
80h
7
6
5
4
3
2
1
0
Saturation [7:0]
Saturation [7:0]: This register works for CVBS and S-Video chrominance.
0000 0000 = 0 (no color)
1000 0000 = 128 (default)
1111 1111 = 255 (maximum)
For composite and S-Video outputs, the total chrominance gain relative to the nominal chrominance gain as a function of the Saturation
[7:0] setting is as follows.
Chrominance Gain = (nominal_chrominance_gain) × (Saturation[7:0] / 128)
Table 3-16. Chroma Hue
Subaddress 0Ch
Default
00h
7
6
5
4
3
2
1
0
Hue [7:0]
Hue [7:0] (does not apply to a component or SECAM video):
0111 1111 = 180 degrees
0000 0000 = 0 degrees (default)
1000 0000 = –180 degrees
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Table 3-17. Chrominance Processing Control 1
Subaddress 0Dh
Default
00h
7
6
5
4
3
2
1
0
3DYC
TBC
Reserved
Chroma adaptive comb enable
3DNR
Automatic color gain control
[1:0]
3DYC, frame recursive noise reduction (3DNR), and time base correction (TBC) can be used simultaneously or independently.
Memory requirements:
External Memory
3DYC
3DNR
Function
Required
0
1
0
1
0
0
1
1
None
None
3DYC only
3DNR only
3DYC + 3DNR
16 Mbits
16 Mbits
32 Mbits
Note: The SDRAM configuration register must be programmed before enabling features that require the SDRAM. Failure to do so will
result in incorrect operation of the memory controller
3DYC:
0 = Disable; the 2D adaptive 5-line comb filter is enabled (default)
1 = Enable
3DYC enhances 2D Y/C separation by utilizing temporal-based, or frame-based information. 3DYC requires the use of the frame buffer
memory and can be used simultaneously with 3DNR and TBC.
TBC:
00 = Disable (default)
01 = On
10 = Automatic selection
11 = Automatic selection
Line-based time correction corrects for horizontal phase errors encountered during video decoding up to ±80 pixels of error. TBC can
be used simultaneously with 3DYC and 3DNR. TBC does not require external memory.
Chrominance adaptive comb enable:
0 = Enable (default)
1 = Disable
This bit is effective on composite video only.
3DNR:
0 = Disable (default)
1 = Enable
Frame recursive noise reduction minimizes the amount of noise in interlaced CVBS, S-Video, or component inputs. 3DNR requires the
use of the frame buffer memory and can be used simultaneously with 3DYC and TBC.
Note: Noise reduction can not be used on progressive inputs.
Automatic color gain control (ACGC) [1:0]:
00 = ACGC enabled (default)
01 = Reserved
10 = ACGC disabled, ACGC set to the nominal value
11 = ACGC frozen to the previously set value
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Table 3-18. Chrominance Processing Control 2
Subaddress 0Eh
Default 0Ch
7
6
5
4
3
2
1
0
Reserved
PAL
WCF
Chrominance filter select [1:0]
compensation
This register trades chroma bandwidth for less false color.
PAL compensation: This bit has no effect in NTSC and SECAM modes.
0 = Disabled
1 = Enabled (default)
Wideband chroma LPF filter (WCF):
0 = Disabled
1 = Enabled (default)
Chrominance filter select [1:0]:
00 = Disabled (default)
01 = Notch 1
10 = Notch 2
11 = Notch 3
Table 3-19. R/Pr Saturation
Subaddress 10h
Default 80h
7
6
5
4
3
2
1
0
R/Pr saturation [7:0]
R/Pr saturation [7:0]: This register works only with YPbPr component video. For RGB video, use the AFE gain registers.
0000 0000 = minimum
1000 0000 = default
1111 1111 = maximum
For component video, the total R/Pr gain relative to the nominal R/Pr gain as a function of the R/Pr saturation[7:0] setting is as follows.
R/Pr Gain = (nominal_chrominance_gain) × (R/Pr saturation[7:0] / 128)
Table 3-20. G/Y Saturation
Subaddress 11h
Default
80h
7
6
5
4
3
2
1
0
G/Y contrast [7:0]
G/Y contrast [7:0]: This register works only with YPbPr component video. For RGB video, use the AFE gain registers.
0000 0000 = minimum
1000 0000 = default
1111 1111 = maximum
For component video outputs, the total luminance gain relative to the nominal luminance gain as a function of the G/Y contrast[7:0] is
as follows.
G/Y Gain = (nominal_luminance_gain) × (G/Y contrast[7:0] / 128)
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Table 3-21. B/Pb Saturation
Subaddress 12h
Default
80h
7
6
5
4
3
2
1
0
B/Pb saturation[7:0]
B/Pb saturation [7:0]: This register works only with YPbPr component video. For RGB video, use the AFE gain registers.
0000 0000 = minimum
1000 0000 = default
1111 1111 = maximum
For component video, the total Pb gain relative to the nominal Pb gain as a function of the B/Pb saturation[7:0] setting is as follows.
B/Pb Gain = (nominal_chrominance_gain) × (B/Pb saturation[7:0] / 128)
Table 3-22. G/Y Brightness
Subaddress 14h
Default
80h
7
6
5
4
3
2
1
0
G/Y brightness[7:0]
G/Y brightness [7:0]: This register works only with YPbPr component video. For RGB video, use the AFE gain registers.
0000 0000 = minimum
1000 0000 = default
1111 1111 = maximum
For component video, the output black level relative to the nominal black level (64 out of 1024) as a function of G/Y brightness[7:0] is
as follows.
Black Level = nominal_black_level + (G/Y brightness[7:0] - 128)
Table 3-23. AVID Start Pixel
Subaddress 16h–17h
Default
55h/5Fh
Subaddress
16h
7
6
5
4
3
2
1
0
AVID start [7:0]
AVID active
17h
Reserved
Reserved
AVID start [9:8]
AVID active
0 = AVID out active in VBLK (default)
1 = AVID out inactive in VBLK
AVID start [9:0]: AVID start pixel number, this is a absolute pixel location from HS start pixel 0.
The TVP5160 decoder updates the AVID start only when the AVID start MSB byte is written to. The AVID start pixel register also
controls the position of the SAV code. If these registers are modified, then the TVP5160 decoder retains the values for each video
standard until the device is reset. The values for a particular video standard must be set by forcing the decoder to the desired video
standard first using register 02h then setting this register. This must be repeated for each video standard where the default values need
to be changed.
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Table 3-24. AVID Stop Pixel
Subaddress 18h–19h
Default
325h/32Fh
7
Subaddress
18h
6
5
4
3
2
1
0
AVID stop [7:0]
19h
Reserved
AVID stop [9:8]
AVID stop [9:0]: AVID stop pixel number. The number of pixels of active video must be an
even number. This is a absolute pixel location from HS start pixel 0.
The TVP5160 decoder updates the AVID stop only when the AVID stop MSB byte is written
to. The AVID stop pixel register also controls the position of the EAV code. If these registers
are modified, then the TVP5160 decoder retains the values for each video standard until the
device is reset. The values for a particular video standard must be set by forcing the decoder
to the desired video standard first using register 02h then setting this register. This must be
repeated for each video standard where the default values need to be changed.
Table 3-25. HS Start Pixel
Subaddress 1Ah–1Bh
Default
000h
Subaddress
1Ah
7
6
5
4
3
2
1
0
HS start [7:0]
1Bh
Reserved
HS start [9:8]
HS start pixel [9:0]: This is an absolute pixel location from HS start pixel 0.
The TVP5160 decoder updates the HS start only when the HS start MSB byte is written to. If these registers are modified, then the
TVP5160 decoder retains the values for each video standard until the device is reset. The values for a particular video standard must be
set by forcing the decoder to the desired video standard first using register 02h then setting this register. This must be repeated for each
video standard where the default values need to be changed.
Table 3-26. HS Stop Pixel
Subaddress 1Ch–1Dh
Default
040h
Subaddress
1Ch
7
6
5
4
3
2
1
0
HS stop [7:0]
1Dh
Reserved
HS stop [9:8]
HS stop [9:0]: This is a absolute pixel location from HS start pixel 0.
The TVP5160 decoder updates the HS stop only when the HS stop MSB byte is written to. If these registers are modified, then the
TVP5160 decoder retains the values for each video standard until the device is reset. The values for a particular video standard must be
set by forcing the decoder to the desired video standard first using register 02h then setting this register. This must be repeated for each
video standard where the default values need to be changed.
Table 3-27. VS Start Line
Subaddress 1Eh–1Fh
Default
004h/001h
Subaddress
1Eh
7
6
5
4
3
2
1
0
VS start [7:0]
1Fh
Reserved
VS start [9:8]
VS start [9:0]: This is a absolute line number.
The TVP5160 decoder updates the VS start only when the VS start MSB byte is written to. If these registers are modified, then the
TVP5160 decoder retains the values for each video standard until the device is reset. The values for a particular video standard must be
set by forcing the decoder to the desired video standard first using register 02h then setting this register. This must be repeated for each
video standard where the default values need to be changed.
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Table 3-28. VS Stop Line
Subaddress 20h–21h
Default
004h/001h
Subaddress
20h
7
6
5
4
3
2
1
0
VS stop [7:0]
21h
Reserved
VS stop [9:8]
VS stop [9:0]: This is an absolute line number.
The TVP5160 decoder updates the VS stop only when the VS stop MSB byte is written to. If these registers are modified, then the
TVP5160 decoder retains the values for each video standard until the device is reset. The values for a particular video standard must be
set by forcing the decoder to the desired video standard first using register 02h then setting this register. This must be repeated for each
video standard where the default values need to be changed.
Table 3-29. VBLK Start Line
Subaddress 22h–23h
Default
001h/26Fh
Subaddress
22h
7
6
5
4
3
2
1
0
VBLK start [7:0]
23h
Reserved
VBLK start [9:8]
VBLK start [9:0]: This is an absolute line number.
The TVP5160 decoder updates the VBLK start line only when the VBLK start MSB byte is written to. If these registers are modified, then
the TVP5160 decoder retains the values for each video standard until the device is reset. The values for a particular video standard must
be set by forcing the decoder to the desired video standard first using register 02h then setting this register. This must be repeated for each
video standard where the default values need to be changed.
Table 3-30. VBLK Stop Line
Subaddress 24h–25h
Default
001h/26Fh
Subaddress
24h
7
6
5
4
3
2
1
0
VBLK stop [7:0]
25h
Reserved
VBLK stop [9:8]
VBLK stop [9:0]: This is an absolute line number.
The TVP5160 decoder updates the VBLK stop only when the VBLK stop MSB byte is written to. If these registers are modified, then the
TVP5160 decoder retains the values for each video standard until the device is reset. The values for a particular video standard must be
set by forcing the decoder to the desired video standard first using register 02h then setting this register. This must be repeated for each
video standard where the default values need to be changed.
Table 3-31. Embedded Sync Offset Control 1
Subaddress 26h
Default
00h
7
6
5
4
3
2
1
0
Offset [7:0]
This register allows the line position of the embedded F bit and V bit signals to be offset from the 656 standard positions. This register is
only applicable to input video signals with standard number of lines.
0111 1111 = 127 lines
⋮
0000 0001 = 1 line
0000 0000 = 0 line
1111 1111 = –1 line
⋮
1000 0000 = –128 lines
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Table 3-32. Embedded Sync Offset Control 2
Subaddress 27h
Default 00h
7
6
5
4
3
2
1
0
Offset [7:0]
This register allows the line relationship between the embedded F bit and V bit signals to be offset from the 656 standard positions, and
moves F relative to V. This register is only applicable to input video signals with standard number of lines.
0111 1111 = 127 lines
⋮
0000 0001 = 1 line
0000 0000 = 0 line
1111 1111 = –1 line
⋮
1000 0000 = –128 lines
Table 3-33. Fast-Switch Control
Subaddress 28h
Default
C0h
7
6
5
4
3
2
1
0
Mode [2:0]
Reserved
Polarity FSO
Polarity FSS
Mode [2:0]:
000 = CVBS ↔ SCART
001 = CVBS, S_VIDEO ↔ Digital overlay
010 = Component ↔ Digital overlay
011 = (CVBS ↔ SCART) ↔ Digital overlay
100 = (CVBS ↔ Digital overlay) ↔ SCART
101 = CVBS ↔ (SCART ↔ Digital overlay)
110 = Composite (default)
111 = Component
Polarity FSO:
0 = If FSO = 0, then output = YPbPr
If FSO = 1, then output = Digital RGB (default)
1 = If FSO = 0, then output = Digital RGB
If FSO = 1, then output = YPbPr
Polarity FSS:
0 = If FSO = 0, then output = RGB
If FSO = 1, then output = CVBS (4A) (default)
1 = If FSO = 0, then output = CVBS (4A)
If FSO = 1, then output = RGB
See TI application note SLEA016, TVP5146 SCART and OSD, for more information on SCART overlay and digital overlay programming.
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Table 3-34. Fast-Switch Overlay Delay
Subaddress 29h
Default
17h
7
6
5
4
3
2
1
0
Reserved
FSO delay [4:0]
Overlay delay [4:0]: Adjusts delay between digital RGB and FSO
11111 = 8 pixel delay
⋮
11000 = 1 pixel delay
10111 = 0 delay (default)
10110 = –1 pixel delay
⋮
00000 = –23 pixel delay
When SCART mode is active (RGB component) the recommended setting for this register is 1Bh; otherwise, 17h is recommended.
Table 3-35. Fast-Switch SCART Delay
Subaddress 2Ah
Default
1Ch
7
6
5
4
3
2
1
0
Reserved
FSS delay [4:0]
FSS delay [4:0]: Adjusts delay between FSS and component RGB
11111 = 3 pixel delay
⋮
11101 = 1 pixel delay
11100 = 0 delay (default)
11011 = –1 pixel delay
⋮
00000 = –23 pixel delay
Table 3-36. Overlay Delay
Subaddress 2Bh
Default 12h
7
6
5
4
3
2
1
0
Reserved
Overlay delay [4:0]
Overlay delay[4:0]: Adjusts delay between digital RGB and component video
11111 = 13 pixel delay
⋮
10011 = 1 pixel delay
10010 = 0 delay (default)
10001 = –1 pixel delay
⋮
00000 = –18 pixel delay
When SCART mode is active (RGB component) the recommended setting for this register is 16h; otherwise, 12h is recommended.
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Table 3-37. SCART Delay
Subaddress 2Ch
Default
56h
7
6
5
4
3
2
1
0
Reserved
SCART delay [6:0]
This register must be changed in multiples of 2 to maintain the CbCr relationship. SCART delay[6:0]: Adjusts delay between CVBS and
component video.
101 1111 = 9 pixel delay
⋮
101 0111 = 1 pixel delay
101 0110 = 0 delay (default)
101 0101 = –1 pixel delay
⋮
000 0000 = –86 pixel delay
Table 3-38. CTI Control
Subaddress 2Eh
Default
00h
7
6
5
4
3
2
1
0
CTI coring [3:0]
CTI gain [3:0]
CTI coring [3:0]: 4-bit CTI coring limit control values, unsigned, linear control range from 0 to ±60, step size = 4
1111 = ±60
⋮
0001 = ±4
0000 = 0 (default)
CTI gain [3:0]: 4-bit CTI gain control values, unsigned, linear control range from 0 to 15/16, step size = 1/16
1111 = 15/16
⋮
0001 = 1/16
0000 = 0 (default)
Table 3-39. Brightness and Contrast Range Extender
Subaddress 2Fh
Default
00h
7
6
5
4
3
2
1
0
Reserved
Contrast
multiplier
Brightness multiplier [3:0]
Contrast multiplier [4]: (MC) Increases the contrast control range for composite and S-Video modes.
0 = 2x contrast control range (default), Gain = n/64 – 1 where n is the contrast control and 64 ≤ n ≤ 255
1 = Normal contrast control range, Gain = n/128 where n is the contrast control and 0 ≤ n ≤ 255
Brightness multiplier [3:0]: (MB) Increases the brightness control range for composite and S-Video modes from 1x to 16x.
0h = 1x(default)
1h = 2x
3h = 4x
7h = 8x
Fh = 16x
Note: In general, the brightness multiplier should be set to 0h for 10-bit outputs and 3h for 8-bit outputs
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Table 3-40. Component Autoswitch Mask
Subaddress 30h
Default
00h
7
6
5
4
3
2
1
0
Reserved
576i
480i
576p
480p
Masks the component progressive/interlaced modes from being processed in the autoswitch routines.
480p
0 = Autoswitch does not include 480p progressive modes (default)
1 = Autoswitch includes 480p progressive mode
576p
0 = Autoswitch does not include 576p progressive mode (default)
1 = Autoswitch includes 576p progressive mode
480i
0 = Autoswitch does not include 480i interlaced modes (default)
1 = Autoswitch includes 480i interlaced mode
576i
0 = Autoswitch does not include 576i interlaced mode (default)
1 = Autoswitch includes 576i interlaced mode
Table 3-41. Sync Control
Subaddress 32h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Polarity FID
Polarity VS
Polarity HS
VS/VBLK
HS/CS
Polarity FID: determines polarity of FID pin
0 = First field high, second field low (default)
1 = First field low, second field high
Polarity VS: determines polarity of VS pin
0 = Active low (default)
1 = Active high
Polarity HS: determines polarity of HS pin
0 = Active low (default)
1 = Active high
VS/VBLK:
0 = VS pin outputs vertical sync (default)
1 = VS pin outputs vertical blank
HS/CS:
0 = HS pin outputs horizontal sync (default)
1 = HS pin outputs composite sync
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Table 3-42. Output Formatter Control 1
Subaddress 33h
Default
40h
7
6
5
4
3
2
1
0
Reserved
YCbCr code range
CbCr code
Reserved
Output format [2:0]
YCbCr output code range:
0 = ITU-R BT.601 coding range (Y ranges from 64 to 940, Cb and Cr range from 64 to 960)
1 = Extended coding range (Y, Cb, and Cr range from 4 to 1016) (default)
CbCr code format:
0 = Offset binary code (2s complement + 512) (default)
1 = Straight binary code (2s complement)
Output format [2:0]:
000 = 10-bit 4:2:2 (pixel × 2 rate) with embedded syncs (ITU-R BT.656)
001 = 20-bit 4:2:2 (pixel rate) with discrete syncs
010 = Reserved
011 = 10-bit 4:2:2 with discrete syncs
100 = 20-bit 4:2:2 (pixel rate) with embedded syncs
101–111 = Reserved
Note: 10-bit mode is also used for raw VBI output mode when bit 4 (VBI raw) in the luminance processing control 1 register at subaddress
06h is set.
Table 3-43. Output Formatter Control 2
Subaddress 34h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Data enable
"Blue" Screen Output [1:0]
Clock polarity
SCLK enable
Data enable: Y[9:0] and C[9:0] output enable
0 = Y[9:0] and C[9:0] high-impedance (default)
1 = Y [9:0] and C[9:0] active
"Blue" Screen Output [1:0]:
00 = Normal operation (default)
01 = "Blue" screen out when the TVP5160 decoder detects lost lock (with tuner input but not with VCR)
10 = Force "Blue" screen out
11 = Reserved
Fully programmable color of "blue screen" to support clean input/channel switching. When enabled, in case of lost lock, or when forced, the
decoder waits until the end of the current frame, then switches the output data to a programmable color. Once displaying the "blue screen",
the inputs and or RF channel can be switched without causing snow or noise to be displayed on the digital output data. Once the inputs
have settled, the "blue screen" can be disabled, and the decoder then waits until the end of the current video frame before re-enabling the
video stream data to the output ports.
Clock polarity:
0 = Data clocked out on the falling edge of SCLK (default)
1 = Data clocked out on the rising edge of SCLK
SCLK enable:
0 = SCLK outputs are high-impedance (default)
1 = SCLK outputs are enabled
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Table 3-44. Output Formatter Control 3
Subaddress 35h
Default
FFh
7
6
5
4
3
2
1
0
GPIO [1:0]
AVID [1:0]
GLCO [1:0]
FID [1:0]
GPIO [1:0]: GPIO pin (pin 82) function select
00 = GPIO is 0b output
01 = GPIO is 1b output
10 = Reserved
11 = GPIO in logic input (default)
AVID [1:0]: AVID pin function select
00 = AVID is 0b output
01 = AVID is 1b output
10 = AVID is active video indicator output
11 = AVID is logic input (default). In this mode the pin is used as GPIO.
GLCO [1:0]: GLCO pin function select
00 = GLCO is 0b output
01 = GLCO is 1b output
10 = GLCO is genlock output
11 = GLCO is logic input (default). In this mode the pin is used as GPIO.
FID [1:0]: FID pin function select
00 = FID is 0b output
01 = FID is 1b output
10 = FID is FID output
11 = FID is logic input (default). In this mode the pin is used as GPIO.
Table 3-45. Output Formatter Control 4
Subaddress 36h
Default
FFh
7
6
5
4
3
2
1
0
VS/VBLK [1:0]
HS/CS [1:0]
C_1 [1:0]
C_0 [1:0]
VS/VBLK [1:0]: VS pin function select
00 = VS is 0b output
01 = VS is 1b output
10 = VS/VBLK is vertical sync or vertical blank output corresponding to bit 1 (VS/VBLK) in the sync control register at subaddress 32h
(see Section 4.1.37)
11 = VS is logic input (default). In this mode the pin is used as GPIO.
HS/CS [1:0]: HS pin function select
00 = HS is 0b output
01 = HS is 1b output
10 = HS/CS is horizontal sync or composite sync output corresponding to bit 0 (HS/CS) in the sync control register at subaddress 32h
(see Section 4.1.37)
11 = HS is logic input (default). In this mode the pin is used as GPIO.
C_1 [1:0]: C_1 pin function select
00 = C_1 is 0b output
01 = C_1 is 1b output
10 = Reserved
11 = C_1 is logic input (default)
C_0 [1:0]: C_0 pin function select
00 = C_0 is 0b output
01 = C_0 is 1b output
10 = Reserved
11 = C_0 is logic input (default)
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Table 3-46. Output Formatter Control 5
Subaddress 37h
Default
FFh
7
6
5
4
3
2
1
0
C_5 [1:0]
C_4 [1:0]
C_3 [1:0]
C_2 [1:0]
C_5 [1:0]: C_5 pin function select
00 = C_5 is 0b output
01 = C_5 is 1b output
10 = Reserved
11 = C_5 is logic input (default). In this mode the pin is used as GPIO.
C_4 [1:0]: C_4 pin function select
00 = C_4 is 0b output
01 = C_4 is 1b output
10 = Reserved
11 = C_4 is logic input (default). In this mode the pin is used as GPIO.
C_3 [1:0]: C_3 pin function select
00 = C_3 is 0b output
01 = C_3 is 1b output
10 = Reserved
11 = C_3 is logic input (default). In this mode the pin is used as GPIO.
C_2 [1:0]: C_2 pin function select
00 = C_2 is 0b output
01 = C_2 is 1b output
10 = Reserved
11 = C_2 is logic input (default). In this mode the pin is used as GPIO.
Table 3-47. Output Formatter Control 6
Subaddress 38h
Default
FFh
7
6
5
4
3
2
1
0
C_9 [1:0]
C_8 [1:0]
C_7 [1:0]
C_6 [1:0]
C_9 [1:0]: C_9 pin function select
00 = C_9 is 0b output
01 = C_9 is 1b output
10 = Reserved
11 = C_9 is logic input (default). In this mode the pin is used as GPIO.
Note: If overlay is enabled, then C[9] functions as FSO regardless of the setting of register 38h.
C_8 [1:0]: C_8 pin function select
00 = C_8 is 0b output
01 = C_8 is 1b output
10 = Reserved
11 = C_8 is logic input (default). In this mode the pin is used as GPIO.
C_7 [1:0]: C_7 pin function select
00 = C_7 is 0b output
01 = C_7 is 1b output
10 = Reserved
11 = C_7 is logic input (default). In this mode the pin is used as GPIO.
C_6 [1:0]: C_6 pin function select
00 = C_6 is 0b output
01 = C_6 is 1b output
10 = Reserved
11 = C_6 is logic input (default). In this mode the pin is used as GPIO.
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Table 3-48. Clear Lost Lock Detect
Subaddress 39h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Clear lost lock detect
Clear lost lock detect: Clear bit 4 (lost lock detect) in the status 1 register at subaddress 3Ah
0 = No effect (default)
1 = Clears bit 4 in the status 1 register
Table 3-49. Status 1
Subaddress 3Ah
Read only
7
6
5
4
3
2
1
0
Peak white
detect status
Line-alternating
status
Field rate
status
Lost lock detect
Color
subcarrier lock
status
Vertical sync
lock status
Horizontal sync TV/VCR status
lock status
Peak white detect status:
0 = Peak white is not detected
1 = Peak white is detected
Line-alternating status:
0 = Non line-alternating
1 = Line-alternating
Field rate status:
0 = 60 Hz
1 = 50 Hz
Lost lock detect:
0 = No lost lock since this bit was last cleared
1 = Lost lock since this bit was last cleared
Color subcarrier lock status:
0 = Color subcarrier is not locked
1 = Color subcarrier is locked
Vertical sync lock status:
0 = Vertical sync is not locked
1 = Vertical sync is locked
Horizontal sync lock status:
0 = Horizontal sync is not locked
1 = Horizontal sync is locked TV/VCR status: 0 = TV 1 = VCR
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Table 3-50. Status 2
Subaddress 3Bh
Read only
7
6
5
4
3
2
1
0
Signal present
Weak signal
detection
PAL switch
polarity
Field sequence
status
Color killed
Macrovision detection [2:0]
Signal present detection:
0 = Signal not present
1 = Signal present
Weak signal detection:
0 = No weak signal
1 = Weak signal mode
PAL switch polarity of first line of odd field:
0 = PAL switch is 0b
1 = PAL switch is 1b
Field sequence status:
0 = Even field
1 = Odd field
Color killed:
0 = Color killer not active
1 = Color killer activated
Macrovision detection [2:0]:
000 = No copy protection
001 = AGC pulses/pseudo syncs present (Type 1)
010 = 2-line colorstripe only present
011 = AGC pulses/pseudo syncs and 2-line colorstripe present (Type 2)
100 = Reserved
101 = Reserved
110 = 4-line colorstripe only present
111 = AGC pulses/pseudo syncs and 4-line colorstripe present (Type 3)
Table 3-51. AGC Gain Status
Subaddress 3Ch–3Dh
Read only
Subaddress
3Ch
7
6
5
4
3
2
1
0
Fine Gain [7:0]
3Dh
Coarse Gain [3:0]
Fine Gain[11:8]
Fine gain [11:0]: This register provides the fine gain value of sync channel.
1111 1111 1111 = 1.9995
1000 0000 0000 = 1
0100 0000 0000 = 0.5
Coarse gain [3:0]: This register provides the coarse gain value of sync channel.
1111 = 2
0101 = 1
0000 = 0.5
These AGC gain status registers are updated automatically by the TVP5160 decoder with AGC on, in manual gain control mode these
register values are not updated by the TVP5160 decoder.
Because this register is a multi-byte register, it is necessary to capture the setting into the register to ensure that the value is not updated
between reading the lower and upper bytes. To cause this register to capture the current settings, bit 0 of I2C register 97h (status request)
must be set to 1b. Once the internal processor has updated this register, bit 0 of register 97h is cleared, indicating that both bytes of the
AGC gain status register have been updated and can be read. Either byte may be read first, because no further update occurs until bit 0 of
97h is set to 1b again.
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Table 3-52. Video Standard Status
Subaddress 3Fh
Read only
7
6
5
4
3
2
1
0
Autoswitch
Reserved
Video standard [3:0]
Autoswitch mode
0 = Single standard set
1 = Autoswitch mode enabled
Video standard [3:0]:
CVBS and S-Video
0000 = Reserved
Component Video
Reserved
0001 = (M, J) NTSC
0010 = (B, D, G, H, I, N) PAL
0011 = (M) PAL
Interlaced 525 (480i)
Interlaced 625 (576i)
Reserved
0100 = (Combination-N) PAL
0101 = NTSC 4.43
0110 = SECAM
Reserved
Reserved
Reserved
0111 = PAL 60
Reserved
1000 = Reserved
Reserved
1001 = Reserved
Progressive 525 (480p)
Progressive 625 (576p)
1010 = Reserved
This register contains information about the detected video standard that the device is currently operating. When in autoswitch mode, this
register can be tested to determine which video standard as has been detected.
Table 3-53. GPIO Input 1
Subaddress 40h
Read only
7
6
5
4
3
2
1
0
C_7
C_6
C_5
C_4
C_3
C_2
C_1
C_0
C_x input status:
0 = Input is a low
1 = Input is a high
These status bits are only valid when pins are used as input and are updated at every line.
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Table 3-54. GPIO Input 2
Subaddress 41h
Read only
7
6
5
4
3
2
1
0
AVID
GPIO
GLCO
VS
HS
FID
C_9
C_8
AVID input pin status:
0 = Input is a low
1 = Input is a high
GPIO (Pin 82) input pin status:
0 = Input is a low
1 = Input is a high
GLCO input pin status:
0 = Input is a low
1 = Input is a high
VS input pin status:
0 = Input is a low
1 = Input is a high
HS input status:
0 = Input is a low
1 = Input is a high
FID input status:
0 = Input is a low
1 = Input is a high
C_x input status:
0 = Input is a low
1 = Input is a high
These status bits are only valid when pins are used as input and its states updated at every line.
Table 3-55. Back End AGC Status 1
Subaddress 44h
Read only
7
6
5
4
3
2
1
0
Gain [7:0]
Current back end AGC ratio = Gain/128
Table 3-56. AFE Coarse Gain for CH 1
Subaddress 46h
Default
20h
7
6
5
4
3
2
1
0
CGAIN 1 [3:0]
Reserved
CGAIN 1 [3:0]: Coarse Gain = 0.5 + (CGAIN 1)/10 where 0 ≤ CGAIN 1 ≤ 15
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
1111 = 2
1110 = 1.9
1101 = 1.8
...
0010 = 0.7(default)
0001 = 0.6
0000 = 0.5
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Table 3-57. AFE Coarse Gain for CH 2
Subaddress 47h
Default
20h
7
6
5
4
3
2
1
1
1
0
0
0
CGAIN 2 [3:0]
Reserved
CGAIN 2 [3:0]: Coarse Gain = 0.5 + (CGAIN 2)/10 where 0 ≤ CGAIN 2 ≤ 15.
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
1111 = 2
1110 = 1.9
1101 = 1.8
⋮
0010 = 0.7(default)
0001 = 0.6
0000 = 0.5
Table 3-58. AFE Coarse Gain for CH 3
Subaddress 48h
Default
20h
7
6
5
4
3
2
CGAIN 3 [3:0]
Reserved
CGAIN 3 [3:0]: Coarse Gain = 0.5 + (CGAIN 3)/10 where 0 ≤ CGAIN 3 ≤ 15.
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
1111 = 2
1110 = 1.9
1101 = 1.8
⋮
0010 = 0.7(default)
0001 = 0.6
0000 = 0.5
Table 3-59. AFE Coarse Gain for CH 4
Subaddress 49h
Default
20h
7
6
5
4
3
2
CGAIN 4 [3:0]
Reserved
CGAIN 4 [3:0]: Coarse Gain = 0.5 + (CGAIN 4)/10 where 0 ≤ CGAIN 4 ≤ 15.
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
1111 = 2
1110 = 1.9
1101 = 1.8
⋮
0010 = 0.7(default)
0001 = 0.6
0000 = 0.5
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Table 3-60. AFE Fine Gain for B/Pb
Subaddress 4Ah–4Bh
Default
900h
Subaddress
4Ah
7
6
5
4
3
2
1
0
FGAIN 1 [7:0]
4Bh
Reserved
FGAIN 1 [11:8]
FGAIN 1 [11:0]: This fine gain applies to component B/Pb.
Fine Gain = (1/2048) * FGAIN where 0 ≤ FGAIN 1 ≤ 4095
This register is only updated when the MSB (register 4Bh) is written to.
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
1111 1111 1111 = 1.9995
1100 0000 0000 = 1.5
1001 0000 0000 = 1.25 (default)
1000 0000 0000 = 1
0100 0000 0000 = 0.5
0011 1111 1111 to 0000 0000 0000 = Reserved
Table 3-61. AFE Fine Gain for G/Y/Chroma
Subaddress 4Ch–4Dh
Default
900h
Subaddress
4Ch
7
6
5
4
3
2
1
0
FGAIN 2 [7:0]
4Dh
Reserved
FGAIN 2 [11:8]
FGAIN 2 [11:0]: This gain applies to component G/Y channel or S-Video chroma.
This register is only updated when the MSB (register 4Dh) is written to.
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
1111 1111 1111 = 1.9995
1100 0000 0000 = 1.5
1001 0000 0000 = 1.25 (default)
1000 0000 0000 = 1
0100 0000 0000 = 0.5
0011 1111 1111 to 0000 0000 0000 = Reserved
Table 3-62. AFE Fine Gain for R/Pr
Subaddress 4Eh–4Fh
Default
900h
Subaddress
4Eh
7
6
5
4
3
2
1
0
FGAIN 3 [7:0]
4Fh
Reserved
FGAIN 3 [11:8]
FGAIN 3 [11:0]: This fine gain applies to component R/Pr.
This register is only updated when the MSB (register 4Fh) is written to.
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
1111 1111 1111 = 1.9995
1100 0000 0000 = 1.5
1001 0000 0000 = 1.25 (default)
1000 0000 0000 = 1
0100 0000 0000 = 0.5
0011 1111 1111 to 0000 0000 0000 = Reserved
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Table 3-63. AFE Fine Gain for CVBS/Luma
Subaddress 50h–51h
Default
900h
Subaddress
50h
7
6
5
4
3
2
1
0
FGAIN 4 [7:0]
51h
Reserved
FGAIN 4 [11:8]
FGAIN 4 [11:0]: This fine gain applies to CVBS or S-Video luma (see AFE fine gain for Pb register)
This register is only updated when the MSB (register 51h) is written to.
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
1111 1111 1111 = 1.9995
1100 0000 0000 = 1.5
1001 0000 0000 = 1.25 (default)
1000 0000 0000 = 1
0100 0000 0000 = 0.5
0011 1111 1111 to 0000 0000 0000 = Reserved
Table 3-64. 656 Version
Subaddress 57h
Default
00h
7
6
5
4
3
2
1
0
Reserved
656 version
Reserved
656 version
0 = Timing confirms to ITU-R BT.656-4 specifications (default)
1 = Timing confirms to ITU-R BT.656-3 specifications
Table 3-65. SDRAM Control
Subaddress 59h
Default 00h
7
6
5
4
3
2
1
0
Reserved
SDRAM_CLK delay control
Enable
Configuration[1:0]
Configuration[1:0]
Bit 1
Bit 0
Arrangement
0
0
1
1
0
1
0
1
2 banks × 2048 rows × 256 columns
4 banks × 2048 rows × 256 columns
2 banks × 4096 rows × 256 columns
4 banks × 4096 rows × 256 columns
16 Mbits
32 Mbits
32 Mbits
64 Mbits
Memories with more rows, columns, and/or banks can be used as long as the minimum requirements are met. Additional rows, columns,
and/or banks are ignored and unused by the memory controller.
The memory controller must be configured before enabling 3DYC or 3DNR; otherwise, incorrect operation of the memory controller will
result.
Enable:
0 = SDRAM controller disabled (default)
1 = SDRAM controller enabled
SDRAM_CLK delay control[3:0]
This register changes the delay from the default position of SDRAM_CLK in increments of approximately 0.58 ns.
Bit 3
Bit 2
Bit 1
Bit 0
Delay
0 (default)
0.58 ns
1.16 ns
9.3 ns
0
0
1
1
0
0
0
1
0
0
0
1
0
1
0
1
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Table 3-66. 3DNR Y Noise Sensitivity
Subaddress 5Ah
Default
80h
7
6
6
6
6
6
5
5
5
5
5
4
3
2
1
1
1
1
1
0
Y noise sensitivity[7:0]
Table 3-67. 3DNR UV Noise Sensitivity
Subaddress 5Bh
Default 80h
7
4
3
2
0
0
0
0
UV noise sensitivity[7:0]
Table 3-68. 3DNR Y Coring Threshold Limit
Subaddress 5Ch
Default 80h
7
4
3
2
Y coring threshold [7:0]
Table 3-69. 3DNR UV Coring Threshold Limit
Subaddress 5Dh
Default 40h
7
4
3
2
UV coring threshold [7:0]
Table 3-70. 3DNR Low Noise Limit
Subaddress 5Eh
Default 40h
7
4
3
2
Threshold to indicate when Low Noise Present[7:0]
This register sets a threshold for low noise present.
Table 3-71. "Blue" Screen Y Control
Subaddress 5Fh
Default
00h
7
6
5
4
3
2
1
0
Y value [9:2]
The Y value of the color screen output when enabled by bit 2 or 3 of the output formatter 2 register is programmable using a 10-bit value.
The 8 MSB, bits[9:2], are represented in this register.
The remaining two LSB are found in the "Blue" screen LSB register. The default color screen output is black.
Table 3-72. "Blue" Screen Cb Control
Subaddress 60h
Default
80h
7
6
5
4
3
2
1
0
Cb value [9:2]
The Cb value of the color screen output when enabled by bit 2 or 3 of the output formatter 2 register is programmable using a 10-bit value.
The 8 MSB, bits[9:2], are represented in this register.
The remaining two LSB are found in the "Blue" screen LSB register. The default color screen output is black.
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Table 3-73. "Blue" Screen Cr Control
Subaddress 61h
Default
80h
7
6
5
4
3
2
1
0
Cr value [9:2]
The Cr value of the color screen output when enabled by bit 2 or 3 of the output formatter 2 register is programmable using a 10-bit value.
The 8 MSB, bits[9:2], are represented in this register. The remaining two LSB are found in the "Blue" screen LSB register. The default color
screen output is black.
Table 3-74. "Blue" Screen LSB Control
Subaddress 62h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Y value LSB [1:0]
Cb value LSB [1:0]
Cr value LSB [1:0]
The two LSB for the "Blue" screen Y, Cb, and Cr values are represented in this register.
Table 3-75. Noise Measurement
Subaddress 64h–65h
Read only
Subaddress
64h
7
6
5
4
3
2
1
0
3DNR Noise Measurement [7:0]
3DNR Noise Measurement [15:8]
65h
3DNR Noise Measurement
Because this register is a double-byte register it is necessary to capture the setting into the register to ensure that the value is not updated
between reading the lower and upper bytes. To cause this register to capture the current settings, bit 0 of I2C register 97h (status request)
must be set to 1b. Once the internal processor has updated this register bit 0 of register 97h is cleared, indicating that both bytes of the
noise measurement register have been updated and can be read. Either byte may be read first, because no further update will occur until
bit 0 of 97h is set to 1b again.
Table 3-76. 3DNR Y Core0
Subaddress 66h
Read only
7
6
5
4
3
2
1
0
Y_core0[7:0]
Y Core0
Table 3-77. 3DNR UV Core0
Subaddress 67h
Read only
7
6
5
4
3
2
1
0
UV_core0[7:0]
UV Core0
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Table 3-78. F- and V-Bit Decode Control
Subaddress 69h
Default
00h
7
6
5
4
3
2
1
0
VPLL
Adaptive
Reserved
F-Mode[1:0]
This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
F-bit control mode
00 = Auto: If lines per frame is standard decode F and V bits as per 656 standard from line count else decode F bit from vsync input
and set V bit = 0b
01 = Decode F and V bits from input syncs
10 = Reserved
11 = Always decode F and V bits from line count (TVP5146 compatible)
This register is used in conjunction with register 75h as indicated below:
REGISTER 69H
REGISTER 75H
STANDARD LPF
NONSTANDARD LPF
MODE
BIT 1
BIT 0
BIT 3
BIT 2
F
V
F
V
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Reserved
TVP5160
TVP5160
Reserved
Reserved
Reserved
656
Reserved
656
Reserved
Toggle
Reserved
Switch9
0
656
656
Pulse
Reserved
Reserved
656
Reserved
Reserved
656
Reserved
Reserved
Toggle
Reserved
Reserved
Switch9
0
656
656
Pulse
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Even = 1
Odd = toggle
1
1
0
0
TVP5146
656
656
Switch
1
1
1
1
1
1
0
1
1
1
0
1
TVP5146
TVP5146
Reserved
656
656
656
656
Toggle
Pulse
Switch
Switch
Reserved
Reserved
Reserved
Reserved
656 = ITU-R BT.656 standard
Pulse = Pulses low for 1 line prior to field transition
Switch = V bit switches high before the F-bit transition and low after the F bit transition
Switch9 = V bit switches high 1 line prior to the F-bit transition, then low after 9 lines
Reserved = Not used
Adaptive
0 = Enable F- and V-bit adaptation to detected lines per frame
1 = Disable F- and V-bit adaptation to detected lines per frame
VPLL time constant control:
0 = VPLL adapts time constants to input signal
1 = VPLL time constants fixed
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Table 3-79. Back-End AGC Control
Subaddress 6Ch
Default
08h
7
6
5
4
3
1
2
1
0
Reserved
Peak
Color
Sync
This register allows disabling the back-end AGC when the front-end AGC uses specific amplitude references (sync height, color burst, or
composite peak) to decrement the front-end gain. For example, writing 0x09 to this register disables the back-end AGC whenever the
front-end AGC uses the sync height to decrement the front-end gain.
Sync: Disables back end AGC when the front end AGC uses the sync height as an amplitude reference.
0 = Enabled (default)
1 = Disabled
Color: Disables back end AGC when the front end AGC uses the color burst as an amplitude reference.
0 = Enabled (default)
1 = Disabled
Peak: Disables back end AGC when the front end AGC uses the composite peak as an amplitude reference.
0 = Enabled (default)
1 = Disabled
Table 3-80. AGC Decrement Speed
Subaddress 6Fh
Default
04h
7
6
5
4
3
2
1
0
Reserved
AGC decrement speed [2:0]
AGC decrement speed: Adjusts gain decrement speed. Only used for composite/luma peaks.
111 = 7 (slowest)
110 = 6 (default)
⋮
000 = 0 (fastest)
Table 3-81. ROM Version
Subaddress 70h
Read only
7
6
5
4
3
2
1
0
ROM version [7:0]
ROM Version [7:0]: ROM revision number
Table 3-82. RAM Version MSB
Subaddress 71h
Read only
7
6
5
4
3
2
1
0
RAM version MSB [7:0]
RAM version MSB [7:0]: This register identifies the MSB of the RAM code revision number.
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Table 3-83. AGC White Peak Processing
Subaddress 74h
Default
00h
7
6
5
4
3
2
1
0
Luma peak A
Reserved
Color burst A
Sync height A
Luma peak B
Composite
peak
Color burst B
Sync height B
Luma peak A: Use of the luma peak as a video amplitude reference for the back-end feed-forward type AGC algorithm
0 = Enabled (default)
1 = Disabled
Color burst A: Use of the color burst amplitude as a video amplitude reference for the back-end
NOTE: Not available for SECAM, component and B/W video sources.
0 = Enabled (default)
1 = Disabled
Sync height A: Use of the sync height as a video amplitude reference for the back-end feed-forward type AGC algorithm
0 = Enabled (default)
1 = Disabled
Luma peak B: Use of the luma peak as a video amplitude reference for front-end feedback type AGC algorithm
0 = Enabled (default)
1 = Disabled
Composite peak: Use of the composite peak as a video amplitude reference for front-end feedback type AGC algorithm
NOTE: Required for CVBS video sources
0 = Enabled (default)
1 = Disabled
Color burst B: Use of the color burst amplitude as a video amplitude reference for front-end feedback type AGC algorithm
NOTE: Not available for SECAM, component and B/W video sources
0 = Enabled (default)
1 = Disabled
Sync height B: Use of the sync-height as a video amplitude reference for front-end feedback type AGC algorithm
0 = Enabled (default)
1 = Disabled
NOTE: If all 4 bits of the lower nibble are set to 1111b (that is, no amplitude reference selected), then the front-end analog and digital
gains are automatically set to nominal values.
If all 4 bits of the upper nibble are set to 1111b (that is, no amplitude reference selected), then the back-end gain is set automatically to
unity. If the input sync height is greater than 100% and the AGC-adjusted output video amplitude becomes less than 100%, then the
back-end scale factor attempts to increase the contrast in the back-end to restore the video amplitude to 100%.
Table 3-84. F-Bit and V-Bit Control
Subaddress 75h
Default
16h
7
6
5
4
1
3
2
1
1
0
Reserved
F and V [1:0]
Reserved
F and V [1:0]
F AND V(1)
LINES PER FRAME
Standard
F BIT
V BIT
ITU-R BT.656
ITU-R BT 656
Forced to 1
Toggles
00 =
Nonstandard even
Nonstandard odd
Standard
Switch at field boundary
Switch at field boundary
ITU-R BT.656
ITU-R BT 656
Toggles
01 = (default)
Nonstandard
Standard
Switch at field boundary
ITU-R BT.656
ITU-R BT 656
Pulsed mode
10 =
11 =
Nonstandard
Reserved
Switch at field boundary
(1) F and V control bits are only enabled for F-bit control modes 01 and 10 (see register 69h).
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Table 3-85. AGC Increment Speed
Subaddress 78h
Default
06h
7
6
5
4
3
2
1
0
Reserved
AGC increment speed [2:0]
AGC increment speed: Adjusts gain increment speed.
111 = 7 (slowest)
110 = 6 (default)
⋮
000 = 0 (fastest)
Table 3-86. AGC Increment Delay
Subaddress 79h
Default
1Eh
7
6
5
4
3
2
1
0
AGC increment delay [7:0]
AGC increment delay: Number of frames to delay gain increments
1111 1111 = 255
⋮
0001 1110 = 30 (default)
⋮
0000 0000 = 0
Table 3-87. Analog Output Control 1
Subaddress 7Fh
Default 00h
7
6
5
4
3
2
1
0
Reserved
AGC enable
Reserved
Analog output
enable
AGC enable:
0 = Enabled (default)
1 = Disabled, manual gain mode set (see Section 4.2.10)
Analog output enable:
0 = Analog output is disabled (default)
1 = Analog output is enabled
Table 3-88. Chip ID MSB
Subaddress 80h
Read only
7
6
5
4
3
2
1
0
CHIP ID MSB[7:0]
CHIP ID MSB[7:0]: This register identifies the MSB of device ID. Value = 51h
Table 3-89. Chip ID LSB
Subaddress 81h
Read only
7
6
5
4
3
2
1
0
CHIP ID LSB [7:0]
CHIP ID LSB [7:0]: This register identifies the LSB of device ID. Value = 60h
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Table 3-90. RAM Version LSB
Subaddress 82h
Read only
7
6
5
4
3
2
1
0
RAM version LSB [7:0]
RAM version LSB [7:0]: This register identifies the LSB of the RAM code revision number.
Example:
Patch Release = v04.04.02
ROM Version = 04h
RAM Version MSB = 04h
RAM Version LSB = 02h
Table 3-91. Color PLL Speed Control
Subaddress 83h
Default 09h
7
6
5
4
3
2
1
0
Speed[3:0]
Color PLL speed control.
Table 3-92. 3DYC Luma Coring LSB
Subaddress 84h
Default
20h/20h
7
6
5
4
3
2
1
0
3DYC Luma Coring [7:0]
This register contains the lower 8 bits of the 10-bit 3DYC luma coring register. The upper 2 bits are accessed through I2C register 86h.
An inter-frame luma signal difference smaller than the programmed value is assumed to be noise, resulting in the pixel being recognized as
"no motion" hence favoring intra-frame (3D) comb filtering. The minimum value of 000h favors the 2D comb filter output, whereas the
maximum value of 3FFh favors the 3D comb filter output.
Table 3-93. 3DYC Chroma Coring LSB
Subaddress 85h
Default
20h/2Ah
7
6
5
4
3
2
1
0
3DYC Chroma Coring [7:0]
This register contains the lower 8 bits of the 10-bit 3DYC chroma coring register. The upper 2 bits are accessed through I2C register 86h.
An inter-frame chroma signal difference smaller than the programmed value is assumed to be noise, resulting in the pixel being recognized
as "no motion" hence favoring intra-frame (3D) comb filtering. The minimum value of 000h favors the 2D comb filter output whereas the
maximum value of 3FFh favors the 3D comb filter output.
Table 3-94. 3DYC Luma/Chroma Coring MSB
Subaddress 86h
Default
00h/00h
7
6
5
4
3
2
1
0
Reserved
Chroma Coring [9:8]
Luma Coring [9:8]
This register contains the upper 2 bits of the 10-bit 3DYC luma coring and 3DYC chroma coring registers. The lower 8 bits are accessed
through I2C registers 84h and 85h.
An inter-frame luma signal difference smaller than the programmed value is assumed to be noise, resulting in the pixel being recognized as
"no motion" hence favoring intra-frame (3D) comb filtering. The minimum value of 000h favors the 2D comb filter output, whereas the
maximum value of 3FFh favors the 3D comb filter output.
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Table 3-95. 3DYC Luma Gain
Subaddress 87h
Default
08h/08h
7
6
5
4
3
2
1
0
3DYC luma gain [7:0]
This register contains a 5.3 format gain value used to calculate the luma difference value for luma coring. The gain can vary from 0 to
31.875 in steps of 0.125. The minimum value of 0 favors the 3D comb filter output, whereas the maximum value of 31.875 favors the 2D
comb filter output.
Table 3-96. 3DYC Chroma Gain
Subaddress 88h
Default
08h/08h
7
6
5
4
3
2
1
0
3DYC chroma gain [7:0]
This register contains a 5.3 format gain value used to calculate the chroma difference value for chroma coring. The gain can vary from 0 to
31.875 in steps of 0.125. The minimum value of 0 favors the 3D comb filter output, whereas the maximum value of 31.875 favors the 2D
comb filter output.
Table 3-97. 3DYC Signal Quality Gain
Subaddress 89h
Default
02h/02h
7
6
5
4
3
2
1
0
3DYC Signal Quality gain [7:0]
When the input signal quality is not good, for example weak broadcast signals or poor VCR signals, 3DCY comb filtering is automatically
turned off. This register sets the gain, or sensitivity, to distinguish poor signal quality. A smaller value in this register favors application of
3DYC, whereas a larger value favors 2DYC.
Table 3-98. 3DYC Signal Quality Coring
Subaddress 8Ah–8Bh
Default
328h/380h
Subaddress
8Ah
7
6
5
4
3
2
1
0
3DYC Signal Quality Coring [7:0]
3DYC Signal Quality Coring [15:8]
8Bh
When the input signal quality is not good, for example weak broadcast signals or poor VCR signals, 3DCY comb filtering is automatically
turned off. This register sets the coring value used to distinguish poor signal quality. A larger value in this register favors application of
3DYC, whereas a smaller value favors 2DYC.
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Table 3-99. IF Compensation Control
Subaddress 8Dh
Default
00h
7
6
5
4
3
2
1
0
Reserved
U
V
Comp.
IF Enable
Comp:
0 = Crosstalk compensation only. Use if SAW IF stage used.
1 = Crosstalk and low-frequency gain compensation. Use if non-SAW IF stage used.
U: Enable high frequency U gain
0 = Enabled
1 = Disabled
V: Enable high frequency V gain
0 = Enabled
1 = Disabled
IF enable:
0 = IF compensation disabled (default)
1 = IF compensation enabled
Table 3-100. IF Differential Gain Control
Subaddress 8Eh
Default 22h
7
6
5
4
3
2
1
0
U differential gain[3:0]
V differential gain[3:0]
For low IF stage distortions, use lower settings.
Table 3-101. IF Low Frequency Gain Control
Subaddress 8Fh
Default 44h
7
6
5
4
3
2
1
0
0
0
U low frequency gain[3:0]
V low frequency gain[3:0]
Table 3-102. IF High Frequency Gain Control
Subaddress 90h
Default 00h
7
6
5
4
3
2
1
U high frequency gain[3:0]
V high frequency gain[3:0]
Table 3-103. Weak Signal High Threshold
Subaddress 95h
Default 60h
7
6
5
4
3
2
1
Level [7:0]
This register controls the upper threshold of the noise measurement that determines whether the input signal is considered a weak signal.
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Table 3-104. Weak Signal High Threshold
Subaddress 96h
Default
50h
7
6
5
4
3
2
1
0
Level [7:0]
This register controls the lower threshold of the noise measurement that determines whether the input signal is considered a weak signal.
Table 3-105. Status Request
Subaddress 97h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Capture
Capture:
Setting a 1b in this bit causes the internal processor to capture the current settings of the AGC status, 3DNR noise measurement, and
the vertical line count registers. Because this capture is not immediate, it is necessary to check for completion of the capture by reading
the Capture bit repeatedly after setting it and waiting for it to be cleared by the internal processor. Once the Capture bit is 0b, then the
AGC status, noise measurement, and vertical line counters (3Ch/3Dh, 64h/65h, and 9Ah/9Bh) will have been updated and can be
safely read in any order.
Table 3-106. 3DYC NTSC VCR Threshold
Subaddress 98h
Default
10h
7
6
5
4
3
2
1
0
Thresh [7:0]
This register controls how 3DYC is enabled/disabled for VCR modes.
Table 3-107. 3DYC PAL VCR Threshold
Subaddress 99h
Default 20h
7
6
5
4
3
2
1
0
Thresh [7:0]
This register controls how 3DYC is enabled/disabled for VCR modes.
Table 3-108. Vertical Line Count
Subaddress 9Ah–9Bh
Read only
Subaddress
9Ah
7
6
5
4
3
2
1
0
Vertical line [7:0]
9Bh
Reserved
Vertical line [9:8]
Vertical line [9:0] represent the detected a total number of lines from the previous frame. This can be used with nonstandard video signals
such as a VCR in trick mode to synchronize downstream video circuitry.
Because this register is a double-byte register it is necessary to capture the setting into the register to ensure that the value is not updated
between reading the lower and upper bytes. To cause this register to capture the current settings bit 0 of I2C register 97h (status request)
must be set to a 1b. Once the internal processor has updated this register, bit 0 of register 97h is cleared, indicating that both bytes of the
vertical line count register have been updated and can be read. Either byte may be read first, because no further update will occur until bit 0
of 97h is set to 1b again.
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Table 3-109. AGC Decrement Delay
Subaddress 9Eh
Default
1Eh
7
6
5
4
3
2
1
0
AGC decrement delay [7:0]
AGC decrement delay: Number of frames to delay gain decrements
1111 1111 = 255
0001 1110 = 30 (default)
0000 0000 = 0
Table 3-110. VDP TTX Filter and Mask
Subaddress B1h
B2h
00h
B3h
00h
B4h
00h
B5h
00h
B6h
00h
B7h
00h
B8h
00h
B9h
00h
BAh
00h
Default
00h
Subaddress
B1h
7
6
5
4
3
2
1
0
Filter 1 Mask 1
Filter 1 Mask 2
Filter 1 Mask 3
Filter 1 Mask 4
Filter 1 Mask 5
Filter 2 Mask 1
Filter 2 Mask 2
Filter 2 Mask 3
Filter 2 Mask 4
Filter 2 Mask 5
Filter 1 Pattern 1
Filter 1 Pattern 2
Filter 1 Pattern 3
Filter 1 Pattern 4
Filter 1 Pattern 5
Filter 2 Pattern 1
Filter 2 Pattern 2
Filter 2 Pattern 3
Filter 2 Pattern 4
Filter 2 Pattern 5
B2h
B3h
B4h
B5h
B6h
B7h
B8h
B9h
BAh
For an NABTS system, the packet prefix consists of five bytes. Each byte contains 4 data bits (D[3:0]) interlaced with 4 Hamming protection
bits (H[3:0]):
Bit 7
D[3]
Bit 6
H[3]
Bit 5
D[2]
Bit 4
H[2]
Bit 3
D[1]
Bit 2
H[1]
Bit 1
D[0]
Bit 0
H[0]
Only the data portion D[3:0] from each byte is applied to a teletext filter function with corresponding pattern bits P[3:0] and mask bits M[3:0].
The filter ignores hamming protection bits.
For a WST system (PAL or NTSC), the packet prefix consists of two bytes. The two bytes contain three bits of magazine number (M[2:0])
and five bits of row address (R[4:0]), interlaced with eight Hamming protection bits H[7:0]:
Bit 7
R[0]
R[4]
Bit 6
H[3]
H[7]
Bit 5
M[2]
R[3]
Bit 4
H[2]
H[6]
Bit 3
M[1]
R[2]
Bit 2
H[1]
H[5]
Bit 1
M[0]
R[1]
Bit 0
H[0]
H[4]
The mask bits enable filtering using the corresponding bit in the pattern register. For example, a 1b in the LSB of mask 1 means that the
filter module should compare the LSB of nibble 1 in the pattern register to the first data bit on the transaction. If these match, then a true
result is returned. A 0b in a mask bit means that the filter module should ignore that data bit of the transaction. If all 0s are programmed in
the mask bits, the filter matches all patterns returning a true result (default 00h).
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Table 3-111. VDP TTX Filter Control
Subaddress BBh
Default
00h
7
6
5
4
3
2
1
0
Reserved
Filter logic [1:0]
Mode
TTX filter 2
enable
TTX filter 1
enable
Filter logic [1:0]: Allow different logic to be applied when combining the decision of Filter 1 and Filter 2 as follows:
00 = NOR (default)
01 = NAND
10 = OR
11 = AND
Mode: Indicates which teletext mode is in use:
0 = Teletext filter applies to 2 header bytes (default)
1 = Teletext filter applies to 5 header bytes
TTX filter 2 enable: provides for enabling the teletext filter function within the VDP.
0 = Disable (default)
1 = Enable
TTX filter 1 enable: provides for enabling the teletext filter function within the VDP.
0 = Disable (default)
1 = Enable
If the filter matches or if the filter mask is all 0s, then a true result is returned.
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1P1[3]
D1[3]
1M1[3]
1P1[2]
D1[2]
1M1[2]
1P1[1]
D1[1]
1M1[1]
1P1[0]
D1[0]
1M1[0]
NIBBLE 1
D2[3:0]
1P2[3:0]
1M2[3:0]
NIBBLE 2
NIBBLE 3
NIBBLE 4
NIBBLE 5
PASS 1
D3[3:0]
1P3[3:0]
1M3[3:0]
Filter 1
Enable
00
01
D4[3:0]
1P4[3:0]
1M4[3:0]
PASS
10
11
D5[3:0]
1P5[3:0]
1M5[3:0]
2
FILTER 1
FILTER 2
Filter Logic
D1..D5
2P1..2P5
2M1..2M5
PASS 2
Filter 2
Enable
Figure 3-1. Teletext Filter Function
Table 3-112. VDP FIFO Word Count
Subaddress BCh
Read only
7
6
5
4
3
2
1
0
FIFO word count [7:0]
FIFO word count [7:0]: This register provides the number of words in the FIFO.
Note: 1 word equals 2 bytes.
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Table 3-113. VDP FIFO Interrupt Threshold
Subaddress BDh
Default
80h
7
6
5
4
3
2
1
0
Thresh [7:0]
Threshold [7:0]: This register is programmed to trigger an interrupt when the number of
words in the FIFO exceeds this value.
Note: 1 word equals 2 bytes.
Table 3-114. VDP FIFO Reset
Subaddress BFh
Default
00h
7
6
5
4
3
2
1
0
Reserved
FIFO reset
FIFO reset: Writing any data to this register clears the FIFO and VDP data registers. After clearing, this register bit is automatically cleared.
Table 3-115. VDP FIFO Output Control
Subaddress C0h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Host access
enable
Host access enable: This register is programmed to allow the host port access to the FIFO or allowing all VDP data to go out the video
output.
0 = Output FIFO data to the video output Y[9:2] (default)
1 = Allow host port access to the FIFO data
Table 3-116. VDP Line Number Interrupt
Subaddress C1h
Default
00h
7
6
5
4
3
2
1
0
Field 1 enable
Field 2 enable
Line number [5:0]
Field 1 interrupt enable:
0 = Disabled (default)
1 = Enabled
Field 2 interrupt enable:
0 = Disabled (default)
1 = Enabled
Line number [5:0]: Interrupt line number (default 00h)
This register is programmed to trigger an interrupt when the video line number exceeds this value in bits [5:0]. This interrupt must be
enabled at address F4h.
Note: The line number value of zero or one is invalid and will not generate an interrupt.
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Table 3-117. VDP Pixel Alignment
Subaddress C2h–C3h
Default
01Eh
Subaddress
C2h
7
6
5
4
3
2
1
0
Pixel alignment [7:0]
C3h
Reserved
Pixel alignment [9:0]
Pixel alignment [9:0]: These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync, where the VDP
controller will initiate the program from one line standard to the next line standard. For example, the previous line of teletext to the next line
of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay in the VDP, but early
enough to allow the new values to be programmed before the current settings are required.
The default value is 0x1E and has been tested with every standard supported here. A new value will only be needed if a custom standard is
in use.
Table 3-118. VDP Line Start
Subaddress D6h
Default
06h
7
6
5
4
3
2
1
0
VDP line start [7:0]
VDP line start [7:0]: Sets the VDP line starting address for the global line mode register
This register has to be set properly before enabling the line mode registers. The global line mode is only active in the region defined by the
VDP line start and stop registers.
Table 3-119. VDP Line Stop
Subaddress D7h
Default
1Bh
7
6
5
4
3
2
1
0
VDP line stop [7:0]
VDP line stop address [7:0]: Sets the VDP stop line.
Table 3-120. VDP Global Line Mode
Subaddress D8h
Default
FFh
7
6
5
4
3
2
1
0
Global line mode [7:0]
Global line mode [7:0]: VDP processing for multiple lines set by VDP start line register D6h and stop line register D7h.
Global line mode register has the same bits definitions as the line mode register's (see Table 3-143).
General line mode will have priority over the global line mode.
Table 3-121. VDP Full Field Enable
Subaddress D9h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Full field enable
Full field enable:
0 = Disabled full field mode(default)
1 = Enabled full field mode
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode register
programmed with FFh are sliced with the definition of full field mode register at subaddress DAh. Values other than FFh in the line mode
registers allow a different slice mode for that particular line.
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Table 3-122. VDP Full Field Mode
Subaddress DAh
Default
FFh
7
6
5
4
3
2
1
0
Full field mode [7:0]
Full field mode [7:0]: This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings
take priority over the full field register. This allows each VBI line to be programmed independently but have the remaining lines in full field
mode. The full field mode register has the same bits definition as line mode registers. (default FFh)
Global line mode will have priority over the full field mode.
Table 3-123. Interlaced/Progressive Status
Subaddress DBh
Read only
7
6
5
4
3
2
1
0
I/P
Interlaced/progressive detection status:
0 = SD interlaced signal detected
1 = ED/HD signal detected
Table 3-124. VBUS Data Access with No VBUS Address Increment
Subaddress E0h
Default 00h
7
6
5
4
3
2
1
0
VBUS data [7:0]
VBUS data [7:0]: VBUS data register for VBUS single byte read/write transaction.
Table 3-125. VBUS Data Access with VBUS Address Increment
Subaddress E1h
Default 00h
7
6
5
4
3
2
1
0
VBUS data [7:0]
VBUS data [7:0]: VBUS data register for VBUS multi-byte read/write transaction. VBUS address is auto-incremented after each data byte
read/write.
Table 3-126. VDP FIFO Read Data
Subaddress E2h
Read only
7
6
5
4
3
2
1
0
FIFO Read Data [7:0]
FIFO Read Data [7:0]: This register is provided to access VBI FIFO data through the I2C interface. All forms of teletext data come directly
from the FIFO, while all other forms of VBI data can be programmed to come from registers or from the FIFO. If the host port reads data
from the FIFO, then bit 0 (host access enable) in the VDP FIFO output control register at subaddress C0h must be set to 1b.
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Table 3-127. VBUS Address
Subaddress
Default
E8h
00h
E9h
00h
EAh
00h
Subaddress
E8h
7
6
5
4
3
2
1
0
VBUS address [7:0]
VBUS address [15:8]
VBUS address [23:16]
E9h
EAh
VBUS address [23:0]: VBUS is a 24-bit wide internal bus. The user must program the 24-bit
address of the internal register to be accessed via host port indirect access mode.
Table 3-128. Interrupt Raw Status 0
Subaddress F0h
Read only
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS/CGMS
VPS/Gemstar
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed, unmasked
0 = Not passed
1 = Passed
TTX: Teletext data available unmasked
0 = Not available
1 = Available
WSS/CGMS: WSS/CGMS data available unmasked
0 = Not available
1 = Available
VPS/Gemstar: VPS/Gemstar data available unmasked
0 = Not available
1 = Available
VITC: VITC data available unmasked
0 = Not available
1 = Available
CC F2: CC field 2 data available unmasked
0 = Not available
1 = Available
CC F1: CC field 1 data available unmasked
0 = Not available
1 = Available
Line: Line number interrupt unmasked
0 = Not available
1 = Available
The host interrupt raw status 0 and 1 registers represent the interrupt status without applying mask bits.
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Table 3-129. Interrupt Raw Status 1
Subaddress F1h
Read only
7
6
5
4
3
2
1
0
Reserved
FIFO full
FIFO full:
0 = FIFO not full
1 = FIFO was full during write to FIFO
The masked or unmasked status is set in the interrupt mask 1 register at subaddress F5h.
The FIFO full error flag is set when the current line of VBI data can not enter the FIFO. For example, if the FIFO has only 10 bytes left and
teletext is the current VBI line, the FIFO full error flag is set, but no data will be written because the entire teletext line will not fit. However, if
the next VBI line is closed caption requiring only 2 bytes of data plus the header, then this will go into the FIFO even if the full error flag is
set.
Table 3-130. Interrupt Status 0
Subaddress F2h
Read only
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS/CGMS
VPS/Gemstar
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed, masked
0 = Not passed
1 = Passed
TTX: Teletext data available masked
0 = Not available
1 = Available
WSS/CGMS: WSS/CGMS data available masked
0 = Not available
1 = Available
VPS/Gemstar: VPS/Gemstar data available masked
0 = Not available
1 = Available
VITC: VITC data available masked
0 = Not available
1 = Available
CC F2: CC field 2 data available masked
0 = Not available
1 = Available
CC F1: CC field 1 data available masked
0 = Not available
1 = Available
Line: Line number interrupt masked
0 = Not available
1 = Available
The interrupt status 0 and 1 registers represent the interrupt status after applying mask bits. Therefore, the status bits are the result of a
logical AND between the raw status and mask bits. The external interrupt pin is derived from this register as an OR function of all
nonmasked interrupts in this register.
Reading data from the corresponding register does not clear the status flags automatically. These flags are reset using the corresponding
bits in interrupt clear 0 and 1 registers.
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Table 3-131. Interrupt Status 1
Subaddress F3h
Read only
7
6
5
4
3
2
1
0
Reserved
FIFO full
FIFO full: Masked status of FIFO
0 = FIFO not full
1 = FIFO was full during write to FIFO, see the interrupt mask 1 register at subaddress F5h
The masked or unmasked status is set in the interrupt mask 1 register.
Table 3-132. Interrupt Mask 0
Subaddress F4h
Read only
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS/CGMS
VPS/Gemstar
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed mask
0 = Disabled (default)
1 = Enabled FIFO_THRES interrupt
TTX: Teletext data available mask
0 = Disabled (default)
1 = Enabled TTX available interrupt
WSS/CGMS: WSS/CGMS data available mask
0 = Disabled (default)
1 = Enabled WSS/CGMS available interrupt
VPS/Gemstar: VPS/Gemstar data available mask:
0 = Disabled (default)
1 = Enabled VPS/Gemstar available interrupt
VITC: VITC data available mask:
0 = Disabled (default)
1 = Enabled VITC available interrupt
CC F2: CC field 2 data available mask
0 = Disabled (default)
1 = Enabled CC field 2 available interrupt
CC F1: CC field 1 data available mask
0 = Disabled (default)
1 = Enabled CC field 1 available interrupt
LINE: Line number interrupt mask
0 = Disabled (default)
1 = Enabled Line_INT interrupt
The host interrupt mask 0 and 1 registers can be used by the external processor to mask unnecessary interrupt sources for interrupt status
0 and 1 register bits, and for the external interrupt pin. The external interrupt is generated from all nonmasked interrupt flags.
Table 3-133. Interrupt Mask 1
Subaddress F5h
Read only
7
6
5
4
3
2
1
0
Reserved
FIFO full
FIFO full: FIFO full mask
0 = Disabled (default)
1 = Enabled FIFO full interrupt
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Table 3-134. Interrupt Clear 0
Subaddress F6h
Read only
7
6
5
4
3
2
1
0
FIFO THRS
TTX
WSS/CGMS
VPS/Gemstar
VITC
CC F2
CC F1
Line
FIFO THRS: FIFO threshold passed clear
0 = No effect (default)
1 = Clear FIFO_THRES bit in status register 0 bit 7
TTX: Teletext data available clear
0 = No effect (default)
1 = Clear TTX available bit in status register 0 bit 6
WSS/CGMS: WSS/CGMS data available clear
0 = No effect (default)
1 = Clear WSS/CGMS available bit in status register 0 bit 5
VPS/Gemstar: VPS/Gemstar data available clear
0 = No effect (default)
1 = Clear VPS/Gemstar available bit in status register 0 bit 4
VITC: VITC data available clear
0 = Disabled (default)
1 = Clear VITC available bit in status register 0 bit 3
CC F2: CC field 2 data available clear
0 = Disabled (default)
1 = Clear CC field 2 available bit in status register 0 bit 2
CC F1: CC field 1 data available clear
0 = Disabled (default)
1 = Clear CC field 1 available bit in status register 0 bit 1
LINE: Line number interrupt clear
0 = Disabled (default)
1 = Clear Line interrupt available bit in status register 0 bit 0
The host interrupt clear 0 and 1 registers are used by the external processor to clear the interrupt status bits in the host interrupt status 0
and 1 registers. When no nonmasked interrupts remain set in the registers, the external interrupt pin will also become inactive.
Table 3-135. Interrupt Clear 1
Subaddress F7h
Read only
7
6
5
4
3
2
1
0
Reserved
FIFO full
FIFO full: Clear FIFO full flag
0 = No effect (default)
1 = Clear bit 0 (FIFO full flag) in the interrupt status 1 register at subaddress F3h and the interrupt raw status 1 register at subaddress
F1h
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3.2 VBUS Register Definitions
Table 3-136. VDP Closed Caption Data
Subaddress 80 051Ch – 80 051Fh
Read only
Subaddress
80 051Ch
80 051Dh
80 051Eh
80 051Fh
7
6
5
4
3
2
1
0
Closed Caption Field 1 byte 1
Closed Caption Field 1 byte 2
Closed Caption Field 2 byte 1
Closed Caption Field 2 byte 2
These registers contain the closed caption data arranged in bytes per field.
Table 3-137. VDP WSS/CGMS Data
Subaddress 80 0520h – 80 0526h
Read only
WSS/CGMS NTSC
Subaddress
80 0520h
80 0521h
80 0522h
80 0523h
80 0524h
80 0525h
80 0526h
7
–
6
–
5
4
3
2
1
0
Byte
b5
b4
b3
b2
b1
b0
b6
WSS/CGMS Field 1 Byte 1
WSS/CGMS Field 1 Byte 2
WSS/CGMS Field 1 Byte 3
b13
–
b12
–
b11
b19
b10
b18
b9
b8
b7
b17
b16
b15
b14
Reserved
–
b13
–
–
b12
–
b5
b4
b3
b9
b2
b8
b1
b7
b0
b6
WSS/CGMS Field 2 Byte 1
WSS/CGMS Field 2 Byte 2
WSS/CGMS Field 2 Byte 3
b11
b19
b10
b18
b17
b16
b15
b14
These registers contain the wide screen signaling data for NTSC.
Bits 0 – 1 represent word 0, aspect ratio
Bits 2 – 5 represent word 1, header code for word 2
Bits 6 – 13 represent word 2, copy control
Bits 14 – 19 represent word 3, CRC
WSS/CGMS PAL/SECAM
Subaddress
80 0520h
80 0521h
80 0522h
80 0523h
80 0524h
80 0525h
80 0526h
7
b7
–
6
b6
–
5
4
3
2
1
0
Byte
b5
b4
b3
b2
b1
b9
b0
b8
WSS/CGMS Field 1 Byte 1
WSS/CGMS Field 1 Byte 2
b13
b12
b11
b10
Reserved
Reserved
b7
b6
b5
b4
b12
b3
b2
b1
b9
b0
b8
WSS/CGMS Field 2 Byte 1
WSS/CGMS Field 2 Byte 2
–
–
b13
b11
b10
Reserved
These registers contain the wide screen signaling data for PAL/SECAM:
Bits 0 – 3 represent Group 1, Aspect Ratio
Bits 4 – 7 represent Group 2, Enhanced Services
Bits 8 – 10 represent Group 3, Subtitles
Bits 11 – 13 represent Group 4, Others
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Table 3-138. VDP VITC Data
Subaddress 80 052Ch – 80 0534h
Read only
Subaddress
80 052Ch
80 052Dh
80 052Eh
80 052Fh
80 0530h
80 0531h
80 0532h
80 0533h
80 0534h
7
6
5
4
3
2
1
0
VITC frame byte 1
VITC frame byte 2
VITC seconds byte 1
VITC seconds byte 2
VITC minutes byte 1
VITC minutes byte 2
VITC hours byte 1
VITC hours byte 2
VITC CRC byte
These registers contain the VITC data.
Table 3-139. VDP V-Chip TV Rating Block 1
Subaddress 80 0540h
Read only
7
6
5
4
3
2
1
0
Reserved
14-D
PG-D
Reserved
MA-L
14-L
PG-L
Reserved
TV Parental Guidelines Rating Block 3
14-D: When incoming video program is TV-14-D rated, this bit is set high.
PG-D: When incoming video program is TV-PG-D rated, this bit is set high.
MA-L: When incoming video program is TV-MA-L rated, this bit is set high.
14-L: When incoming video program is TV-14-L rated, this bit is set high.
PG-L: When incoming video program is TV-PG-L rated, this bit is set high.
Table 3-140. VDP V-Chip TV Rating Block 2
Subaddress 80 0541h
Read only
7
6
5
4
3
2
1
0
Reserved
14-S
PG-S
Reserved
MA-V
14-V
PG-V
Y7-FV
TV Parental Guidelines Rating Block 2
MA-S: When incoming video program is TV-MA-S rated, this bit is set high.
14-S: When incoming video program is TV-14-S rated, this bit is set high.
PG-S: When incoming video program is TV-PG-S rated, this bit is set high.
MA-V: When incoming video program is TV-MA-V rated, this bit is set high.
14-V: When incoming video program is TV-14-V rated, this bit is set high.
PG-V: When incoming video program is TV-PG-S rated, this bit is set high.
Y7-FV: When incoming video program is TV-Y7-FV rated, this bit is set high.
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Table 3-141. VDP V-Chip TV Rating Block 3
Subaddress 80 0542h
Read only
7
6
5
4
3
2
1
0
None
TV-MA
TV-14
TV-PG
TV-G
TV-Y7
TV-Y
None
TV Parental Guidelines Rating Block 1
None: No block intended
TV-MA: When incoming video program is "TV-MA" rated in TV Parental Guidelines Rating, this bit is set high.
TV-14: When incoming video program is "TV-14" rated in TV Parental Guidelines Rating, this bit is set high.
TV-PG: When incoming video program is "TV-PG" rated in TV Parental Guidelines Rating, this bit is set high.
TV-G: When incoming video program is "TV-G" rated in TV Parental Guidelines Rating, this bit is set high.
TV-Y7: When incoming video program is "TV-Y7" rated in TV Parental Guidelines Rating, this bit is set high.
TV-Y: When incoming video program is "TV-G" rated in TV Parental Guidelines Rating, this bit is set high.
Table 3-142. VDP V-Chip MPAA Rating Data
Subaddress 80 0543h
Read only
7
6
5
4
3
2
1
0
Not Rated
X
NC-17
R
PG-13
PG
G
NA
MPAA Rating Block (E5h)
Not Rated: When incoming video program is "Not Rated" rated in MPAA Rating, this bit is set high.
X: When incoming video program is "X" rated in MPAA Rating, this bit is set high.
NC-17: When incoming video program is "NC-17" rated in MPAA Rating, this bit is set high.
R: When incoming video program is "R" rated in MPAA Rating, this bit is set high.
PG-13: When incoming video program is "PG-13" rated in MPAA Rating, this bit is set high.
PG: When incoming video program is "PG" rated in MPAA Rating, this bit is set high.
G: When incoming video program is "G" rated in MPAA Rating, this bit is set high.
N/A: When incoming video program is "N/A" rated in MPAA Rating, this bit is set high.
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Table 3-143. VDP General Line Mode and Line Address
Subaddress 80 0600h – 80 0611h
(default line mode = FFh, line address = 00h)
Subaddress
80 0600h
80 0601h
80 0602h
80 0603h
80 0604h
80 0605h
80 0606h
80 0607h
80 0608h
80 0609h
80 060Ah
80 060Bh
80 060Ch
80 060Dh
80 060Eh
80 060Fh
80 0610h
80 0611h
7
6
5
4
3
2
1
0
Line address 1
Line mode 1
Line address 2
Line mode 2
Line address 3
Line mode 3
Line address 4
Line mode 4
Line address 5
Line mode 5
Line address 6
Line mode 6
Line address 7
Line mode 7
Line address 8
Line mode 8
Line address 9
Line mode 9
Line address [7:0]: Line number to process selected line mode register on
Line mode register x [7:0]
Bit 7
0 = Disabled filters
1 = Enabled filters for teletext and CC (Null byte filter) (default)
Bit 6
0 = Send sliced VBI data to registers only
1 = Send sliced VBI data to FIFO and registers, teletext data only goes to FIFO (default)
Bit 5
0 = Allow VBI data with errors in the FIFO
1 = Do not allow VBI data with errors in the FIFO (default)
Bit 4
0 = Disabled error detection and correction
1 = Enabled error detection and correction (teletext only) (default)
Bit 3
0 = Field 1
1 = Field 2 (default)
Bit [2:0]
000 = Teletext (WST625, Chinese Teletext, NABTS 525)
001 = CC (US, European, Japan, China)
010 = WSS/CGMS (525, 625)
011 = VITC
100 = VPS (PAL only), Gemstar EPG (NTSC only)
101 = USER 1
110 = USER 2
111 = Reserved (active video) (default)
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Table 3-144. VDP VPS, Gemstar EPG Data
Subaddress 80 0700h – 80 070Ch
Read only
VPS
Subaddress
80 0700h
80 0701h
80 0702h
80 0703h
80 0704h
80 0705h
80 0706h
80 0707h
80 0708h
80 0709h
80 070Ah
80 070Bh
80 070Ch
7
6
5
4
3
2
1
0
VPS byte 1
VPS byte 2
VPS byte 3
VPS byte 4
VPS byte 5
VPS byte 6
VPS byte 7
VPS byte 8
VPS byte 9
VPS byte 10
VPS byte 11
VPS byte 12
VPS byte 13
These registers contain the entire VPS data line except the clock run-in code and the frame code.
Gemstar EPG
Subaddress
80 0700h
80 0701h
80 0702h
80 0703h
80 0704h
80 0705h
80 0706h
80 0707h
80 0708h
80 0709h
80 070Ah
80 070Bh
80 070Ch
7
6
5
4
3
2
1
0
Gemstar EPG Frame Code
Gemstar EPG byte 1
Gemstar EPG byte 2
Gemstar EPG byte 3
Gemstar EPG byte 4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Table 3-145. Analog Output Control 2
Subaddress A0 005Eh
Default
B2h
7
6
5
4
3
2
1
0
Reserved
Gain[3:0]
Analog output PGA gain [3:0]: These bits are effective when analog output AGC is disabled.
Gain[3:0]
0000
0001
1.30
1.56
1.82
2.08
2.34
2.60
2.86
3.12
3.38
3.64
3.90
4.16
4.42
4.68
4.94
5.20
0010 (default)
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 3-146. Interrupt Configuration
Subaddress A0 0060h
Default 00h
7
6
5
4
3
2
1
0
Reserved
Polarity
Reserved
Polarity: Interrupt pin polarity
0 = Active high (default)
1 = Active low (open drain, a pullup register is required)
Table 3-147. Interrupt Raw Status 1
Subaddress B0 0069h
Read only
7
6
5
4
3
2
1
0
Reserved
H/V lock: unmasked
H/V lock
Macrovision status changed
Standard changed
Reserved
0 = H/V lock status unchanged
1 = H/V lock status changed
Macrovision status changed: unmasked
0 = Macrovision status unchanged
1 = Macrovision status changed
Standard changed: unmasked
0 = Video standard unchanged
1 = Video standard changed
The masked or unmasked status is set in the interrupt mask 1 register.
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Table 3-148. Interrupt Status 1
Subaddress B0 006Dh
Read only
7
6
5
4
3
2
1
0
Reserved
H/V lock
Macrovision status changed
Standard changed
Reserved
H/V lock: H/V lock status changed masked
0 = H/V lock status unchanged
1 = H/V lock status changed
Macrovision status changed: Macrovision status changed masked
0 = Macrovision status not changed
1 = Macrovision status changed
Standard changed: Standard changed masked
0 = Video standard not changed
1 = Video standard changed
The masked or unmasked status is set in the interrupt mask1 register.
Table 3-149. Interrupt Mask 1
Subaddress B0 0065h
Default
00h
7
6
5
4
3
2
1
0
Reserved
H/V lock: H/V lock status changed mask
H/V lock
Macrovision status changed
Standard changed
Reserved
0 = H/V lock status unchanged (default)
1 = H/V lock status changed
Macrovision status changed: Macrovision status changed mask
0 = Macrovision status unchanged (default)
1 = Macrovision status changed
Standard changed: Standard changed mask
0 = Disabled (default)
1 = Enabled video standard changed
Table 3-150. Interrupt Clear 1
Subaddress B0 0071h
Default
00h
7
6
5
4
3
2
1
0
Reserved
H/V lock
Macrovision status changed
Standard changed
Reserved
H/V lock: Clear H/V lock status changed flag
0 = H/V lock status unchanged
1 = H/V lock status changed
Macrovision status changed: Clear Macrovision status changed flag
0 = No effect (default)
1 = Clear bit 2 (Macrovision status changed) in the interrupt status 1 register at subaddress B0 006Dh and the interrupt raw status 1
register at subaddress B0 0069h
Standard changed: Clear standard changed flag
0 = No effect (default)
1 = Clear bit 1 (video standard changed) in the interrupt status 1 register at subaddress B0 006Dh and the interrupt raw status 1
register at subaddress B0 0069h
94
Typical Application Circuit
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4
Typical Application Circuit
4.1 Typical Application Circuit
Figure 4-1. Application Example
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Typical Application Circuit
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5
Typical Register Programming Sequence
Composite Input, Autoswitch, 10-bit ITU-656, 3DYC and 3DNR Enabled
// Address, Data
0xEE, 0x01 // ROM Initialization Procedure - Required
0xEA, 0xB0
0xE9, 0x00
0xE8, 0x63
0xE0, 0x01
0xEE, 0x00
0x00, 0x00 // Input/Output Select - Composite input selected (default)
0x06, 0x40 // Luminance Processing Control 1 - No pedestal present
0x33, 0x40 // Output Formatter Control 1 - 10-bit ITU-656 (default)
0x34, 0x11 // Output Formatter Control 2 - Data and SCLK enabled
0x35, 0x2A // Output Formatter Control 3 - GPIO (pin 82) = 0, GLCO, AVID, and FID enabled
0x36, 0xAF // Output Formatter Control 4 - HS and VS enabled
0x59, 0x07 // SDRAM Control - 64-Mbit SDRAM configured and enabled; must be set before enabling
3DYC
or 3DNR
0x0D, 0x84 // Chrominance Processing Control 1 - 3DYC and 3DNR enabled
480p Progressive Inputs, Autoswitch, 20-bit ITU-656, 3DYC and 3DNR Enabled
// Address, Data
0xEE, 0x01 // ROM Initialization Procedure - Required
0xEA, 0xB0
0xE9, 0x00
0xE8, 0x63
0xE0, 0x01
0xEE, 0x00
0x00, 0x95 // Input/Output Select - Y(VI_5), Pb(VI_11), Pr(VI_8)
0x06, 0x40 // Luminance Processing Control 1 - No pedestal present
0x30, 0x0F // Component Autoswitch Mask - 480i/p and 576i/p enabled in autoswitch
0x33, 0x44 // Output Formatter Control 1 - 20-bit ITU-656
0x34, 0x11 // Output Formatter Control 2 - Data and SCLK enabled
0x35, 0x2A // Output Formatter Control 3 - GPIO (pin 82) = 0, GLCO, AVID, and FID are enabled
0x36, 0xAF // Output Formatter Control 4 - HS and VS enabled
0x59, 0x07 // SDRAM Control - 64-Mbit SDRAM configured and enabled; must be set before enabling
3DYC
or 3DNR
0x0D, 0x84 // Chrominance Processing Control 1 - 3DYC and 3DNR enabled
96
Typical Register Programming Sequence
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6
Electrical Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
0.5
MAX
4.0
UNIT
IOVDD to
IOGND
V
V
V
DVDD to DGND
–0.2
–0.3
2.0
A33VDD(2) to
Supply voltage range
3.6
A33GND(3)
A18VDD(4) to
–0.2
2.0
V
A18GND(5)
VI to DGND
VO to DGND
AIN to AGND
TA
Digital input voltage range
Digital output voltage range
Analog input voltage range
Operating free-air temperature
Storage temperature
–0.5
–0.5
–0.2
0
4.5
4.5
2.0
70
V
V
V
°C
°C
Tstg
–65
150
(1) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) CH1_A33VDD, CH2_A33VDD
(3) CH1_A33GND, CH2_A33GND
(4) CH1_A18VDD, CH2_A18VDD, A18VDD, A18VDD_REF, PLL_A18VDD
(5) CH1_A18GND, CH2_A18GND, A18GND
6.2 Recommended Operating Conditions
PARAMETER
Supply voltage, digital
TEST CONDITIONS
MIN
3.0
NOM
3.3
MAX
3.6
UNIT
V
IOVDD
DVDD
AVDD33
AVDD18
VI(PP)
Supply voltage, digital
1.65
1.8
1.95
3.6
V
Supply voltage, analog
3.0
3.3
V
Supply voltage, analog
1.65
1.8
1.95
2.0
V
Input voltage, analog (ac-coupling necessary)
Input voltage high, digital(1)
0.5
1.0
V
VIH
0.7 IOVDD
V
0.3
IOVDD
VIL
Input voltage low, digital(2)
V
IOH
IOL
IOH
IOL
IOH
IOL
TA
Output current (Y/SD data/SD address/SCLK)(3)
Output current (Y/SD data/SD address/SCLK)
Output current (SDRAM_CLK)
Output current (SDRAM_CLK)
Output current (C)
Vout = 2.4 V
–8
8
mA
mA
mA
mA
mA
mA
°C
Vout = 0.4 V
Vout = 2.4 V
Vout = 0.4 V
Vout = 2.4 V
Vout = 0.4 V
–8
8
–4
4
Output current (C)
Operating free-air temperature
0
70
Analog
out
Output voltage
2.0
2.4
V
(1) Exception: 0.7 AVDD18 for XIN terminal
(2) Exception: 0.3 AVDD18 for XIN terminal
(3) Currents out of a terminal are given as a negative number
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6.3 Crystal Specifications
CYSTAL SPECIFICATION
MIN
NOM
MAX
UNIT
MHz
ppm
Frequency
Frequency tolerance(1)
14.31818
–50
50
(1) This number is the required specification for the external crystal/oscillator and is not tested.
6.4 DC Electrical Characteristics
For minimum/maximum values: IOVDD = 3.0 V to 3.6 V, DVDD = 1.65 V to 1.95 V, AVDD33 = 3.0 V to 3.6 V, AVDD18 = 1.65 V
to 1.95 V, TA = 0°C to 70°C. For typical values: IOVDD = 3.3 V, DVDD = 1.8 V, AVDD33 = 3.3 V, AVDD18 = 1.8 V, TA = 25°C
PARAMETER
TEST CONDITIONS
CVBS, 3DYC, 3DNR
MIN
TYP
28
MAX
33
UNIT
S-Video, 3DNR
SCART
23
27
IDD(IOD)
3.3-V IO digital supply current(1)
mA
33
39
480p/525p
CVBS
52
63
159
156
172
205
18
190
187
206
246
21
S-Video
IDD(D)
1.8-V digital supply current
3.3-V analog supply current
1.8-V analog supply current
mA
mA
mA
mW
SCART
480p/525p
CVBS
S-Video
31
37
IDD(33A)
IDD(18A)
PTOT
SCART
38
45
480p/525p
CVBS
35
42
80
96
S-Video
136
138
138
582
704
792
904
163
165
165
698
845
950
1085
180
3
SCART
480p/525p
CVBS, 3DYC, 3DNR
S-Video, 3DNR
SCART
Total power dissipation, normal
operation
480p/525p
PSAVE
PDOWN
Ilkg
Total power dissipation, power save
Total power dissipation, power down
Input leakage current(1)
mW
mW
µA
10
CI
Input capacitance
by design (not tested)
8
pF
Output voltage high
(Y/SD data/SD address/SCLK)
VOH
VOL
IOH = –8 mA
0.8 IOVDD
V
V
Output voltage low
(Y/SD data/SD address/SCLK)
IOL = 8 mA
0.2 IOVDD
VOH
VOL
VOH
VOL
Output voltage high (SDRAM_CLK)
Output voltage LOW (SDRAM_CLK)
Output voltage HIGH (C)
IOH = –8 mA
IOL = 8 mA
IOH = –4 mA
IOL = 4 mA
0.8 IOVDD
0.8 IOVDD
V
V
V
V
0.2 IOVDD
0.2 IOVDD
Output voltage LOW (C)
(1) GLCO and GPIO are bidirectional pins with an internal pulldown resistor during reset. These pins may sink up to 30 µA during reset.
98
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6.5 Analog Processing and A/D Converters
FS = 60 MSPS for CH1, CH2
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kΩ
pF
Zi
Input impedance, analog video inputs
Input capacitance, analog video inputs
Input voltage range
specified by design (not tested)
specified by design (not tested)
Ccoupling = 0.1 µF
200
Ci
Vi(PP)
ΔG
0.50
–6.7
–7.5%
2
1.0
V
Input gain control range
Input gain ratio, N = 0 to 15
Input offset control per step
Absolute differential nonlinearity
Absolute integral nonlinearity
Frequency response
dB
0.5 +N/10
4
0.75
1
LSB
LSB
LSB
dB
DNL
INL
AFE only
AFE only
FR
Multiburst (60 IRE)
1 MHz
–0.9
XTALK
SNR
GM
Crosstalk
dB
Signal-to-noise ratio all channels
Gain match(1)
FIN = 1 MHz, 1.0 VPP
Full scale, 1 MHz
54
dB
1.5
%
Luma ramp
(100 kHz to full, tilt null)
NS
Noise spectrum
–58
dB
DP
DG
Differential phase
Modulated ramp
Modulated ramp
0.5
°
Differential gain
±1.5
%
%
Analog output gain ratio, N = 0 to 15
–8% 1.3 + 0.26xN
8
(1) Component inputs only
6.6 Data Clock, Video Data, Sync Timing
PARAMETER
TEST CONDITIONS
MIN
TYP
50
MAX
UNIT
%
Duty cycle SCLK
45
55
t1
t1
t1
t2
t2
t2
t3
t4
t5
t6
High time, SCLK @ 13.5 MHz
High time, SCLK @ 27 MHz
High time, SCLK @ 54 MHz
Low time, SCLK @ 13.5 MHz
Low time, SCLK @ 27 MHz
Low time, SCLK @ 54 MHz
Fall time, SCLK
≥ 50%
37
ns
≥ 50%
18.5
9.25
37
≥ 50%
≤ 50%
ns
≤ 50%
18.5
9.25
≤ 50%
90% to 10%
10% to 90%
To 90%/10%
To 90%/10%
5
5
5
ns
ns
ns
ns
Rise time, SCLK
Data valid time
Data hold time
2.5
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6.7 I2C Host Port Timing
PARAMETER
TEST CONDITIONS
MIN
1.3
0
TYP
MAX
UNIT
µs
t1
Bus free time between STOP and START
Data hold time
t2
0.9
µs
t3
Data setup time
100
0.6
0.6
0.6
ns
t4
Setup time for a (repeated) START condition
Setup time for a STOP condition
Hold time (repeated) START condition
Rise time VC1(SDA) and VC0(SCL) signal
Fall time VC1(SDA) and VC0(SCL) signal
Capacitive load for each bus line
I2C clock frequency
µs
t5
µs
t6
µs
t7
specified by design(1)
specified by design(1)
specified by design(1)
250
250
400
400
ns
t8
ns
Cb
f12C
pF
kHz
(1) Assured by design. Not tested.
t
2
t
t
t
3
4
1
90%
10%
SCLK
t
5
t
6
90%
10%
Y, C, AVID,
Valid Data
Valid Data
VS, HS, FID
Figure 6-1. Clocks, Video Data, and Sync Timing
Stop Start
Stop
VC1 (SDA)
VC0 (SCL)
Data
t
t
1
6
t
3
t
6
t
2
t
5
t
4
t
t
7
8
Change
Data
Figure 6-2. I2C Host Port Timing
100
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6.8 SDRAM Timing(1)
CL = 10 pF, CAS latency = 3, Clock delay = 0 ns
PARAMETER
TEST CONDITIONS
MIN
TYP
9.2
4.6
4.6
MAX
UNIT
ns
t1
t2
t3
t4
t5
t6
t7
t8
tg
Clock period (108 MHz)
Clock high period
ns
Clock low period
ns
Clock to output valid time (address/data/control)
Output hold time
5.3
ns
1.8
1.1
0.3
ns
Data in setup time
ns
Data in hold time
ns
Clock rise time, 10% to 90%
Clock fall time, 90% to 10%
4
4
ns
ns
(1) Assured by design. Not tested.
t
t
6
t
1
4
t
t
t
t
7
2
3
5
SDRAM_CLK
Address/Control
Data_out
Data_in
Figure 6-3. SDRAM Interface Timing
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6.9 Example SDRAM Timing Alignment
Samsung K4S161622E-80, CAS latency = 3, Clock delay = 0 ns
t
= 9.2 ns
t
= 1.1 ns
= 0.3 ns
1
6
t
= 4.6 ns
t
2
7
2.5 ns
SDRAM_CLK
Address/Data_out
Data_in
9.2 ns
6 ns
2.5 ns
1 ns
2.5 ns
1 ns
4.6 ns
2 ns
SDRAM_CLK_out
Address/Data_in
Data_out
SDRAM-K4S161622E-80 (CAS LAT = 3)
t
t
(dhm)
(dsum)
Data = read margin
t
t
= 9.2 - 6 - 1.1 ns = 2.1 ns
(dsum)
= 2.5 - 0.3 ns = 2.2 ns
(dhm)
Figure 6-4. TVP5160 Timing Relationship with K4S161622E-80 SDRAM
102
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6.10 Memories Tested
Table 6-1. Memories Tested
MANUFACTURER
Samsung
Samsung
Samsung
Samsung
Etron
PART NUMBER
SIZE
MBYTES SPEED
PINS
54
54
50
54
54
54
54
54
50
54
3DYC
3DNR
3DYC+3DNR
K4S641632H-TC75
K4S641632H-TC70
K4S161622E-TC60
K4S161622H-TC60
EM638165TS-6
4 Meg x 16
4 Meg x 16
1 Meg x 16
1 Meg x 16
4 Meg x 16
4 Meg x 16
8 Meg x 16
4 Meg x 16
1 Meg x 16
4 Meg x 16
8 MB
8 MB
2 MB
2 MB
8 MB
8 MB
16 MB
8 MB
2 MB
8 MB
133 MHz
143 MHz
166 MHz
166 MHz
166 MHz
143 MHz
133 MHz
133 MHz
143 MHz
133 MHz
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
Y
Y
Y
Y
N
Y
Etron
EM638165TS-7
Micron
MT48LC8M16A2TG-75
MT48LC4M16A2TG-75
IS42S16100C1-7TL
IS42S16400B-7TL
Micron
ISSI
ISSI
6.11 Thermal Specification(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Thermal pad soldered to 4-layer
High-K PCB
θJA
Junction-to-ambient thermal resistance, still air
Junction-to-case thermal resistance, still air
Maximum junction temperature for reliable operation
17.17
°C/W
Thermal pad soldered to 4-layer
High-K PCB
θJC
0.12
°C/W
TJ(MAX)
105
°C
(1) The exposed thermal pad must be soldered to a JEDEC High-K PCB with adequate ground plane. When split ground planes are used,
attach the thermal pad to the digital ground plane.
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7
Designing With PowerPAD™
The TVP5160 device is housed in a high-performance, thermally enhanced, 128-pin PowerPAD package
(TI package designator: 128PFP). Use of the PowerPAD package does not require any special
considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the
device, is a metallic thermal and electrical conductor. Therefore, if not implementing the PowerPAD PCB
features, the use of solder masks (or other assembly techniques) may be required to prevent any
inadvertent shorting by the exposed PowerPAD of connection etches or vias under the package. The
recommended option, however, is not to run any etches or signal vias under the device, but to have only a
grounded thermal land as explained below. Although the actual size of the exposed die pad may vary, the
minimum size required for the keep out area for the 128-terminal PFP PowerPAD package is 8.8 mm ×
8.8 mm and is centered on the device package.
It is recommended that there be a thermal land, which is an area of solder-tinned-copper, underneath the
PowerPAD package. The thermal land will vary in size, depending on the PowerPAD package being used,
the PCB construction, and the amount of heat that needs to be removed. In addition, the thermal land may
or may not contain numerous thermal vias depending on PCB construction.
Other requirements for thermal lands and thermal vias are detailed in the TI application note PowerPAD
Thermally Enhanced Package Application Report, TI literature number SLMA002, available via the TI web
site at www.ti.com.
For the TVP5160 device, this thermal land must be grounded to the low impedance ground plane of the
device. This improves not only thermal performance but also the electrical grounding of the device. It is
also recommended that the device ground terminal landing pads be connected directly to the grounded
thermal land. The land size must be as large as possible without shorting device signal terminals. The
thermal land may be soldered to the exposed PowerPAD using standard reflow soldering techniques.
While the thermal land may be electrically floated and configured to remove heat to an external heat sink,
it is recommended that the thermal land be connected to the low impedance ground plane for the device.
More information may be obtained from the TI application note PHY Layout, TI literature number
SLLA020.
104
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96
65
97
64
Exposed Thermal
Pad
9,70
7,88
128
33
1
32
9,70
7,88
Top View
NOTE: All linear dimensions are in millimeters
Figure 7-1. 128-Pin PowerPAD Package
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8
Revision History
Table 8-1. Revision History
REVISION
COMMENTS
SLES135
Initial release
Unknown
SLES135A
Section 1.4, Related Products section added.
Section 1.5, Trademarks modified.
Table 1-1, I/O type modified for SCL pin.
Table 2-1, Specified Y/C separation support by video standard.
Figure 2-4, Crystal parallel resistor recommendation added.
Table 2-9, CGMS support added for PAL.
Table 2-11, Signal names modified.
Table 3-1, Brightness & Contrast Range Extender register added.
Table 3-13, Brightness control register description modified.
Table 3-14, Color saturation control register description modified.
Table 3-15, Contrast control register description modified.
Table 3-19, R/Pr saturation control register description modified.
Table 3-20, G/Y contrast control register description modified.
Table 3-21, B/Pb saturation control register description modified.
Table 3-22, G/Y brightness control register description modified.
Table 3-39, Brightness & Contrast Range Extender register added.
Table 3-128, CGMS support added.
SLES135B
Table 3-130, CGMS support added.
Table 3-132, CGMS support added.
Table 3-134, CGMS support added.
Table 3-137, CGMS support added.
Section 6.11, Thermal specification added.
Made minor editorial changes throughout.
SLES135C
SLES135D
Made minor editorial changes throughout.
Section 2.9.1, Removed statement about internal pulldown on I2CAx terminals.
Section 6.11, Updated table
Table 3-1, Added RAM version MSB and LSB registers (subaddresses: 71h, 82h)
Table 3-82, Added RAM version MSB register (subaddress: 71h)
Table 3-90, Added RAM version LSB register (subaddress: 82h)
SLES135E
106
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PACKAGE OPTION ADDENDUM
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30-Aug-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TVP5160PNP
NRND
HTQFP
PNP
128
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
0 to 70
TVP5160
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
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Addendum-Page 1
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