TPS2370D [TI]
IEEE 802.3af POWER INTERFACE SWITCH FOR POWER OVER ETHERNET(PoE) POWERED DEVICES ; IEEE 802.3af标准的电源接口开关，用于以太网供电（ PoE）的供电设备
| 型号： | TPS2370D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IEEE 802.3af POWER INTERFACE SWITCH FOR POWER OVER ETHERNET(PoE) POWERED DEVICES |
| 文件： | 总13页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢇꢈꢈ ꢈ ꢉ ꢆꢃ ꢊꢄ ꢋ ꢌ ꢁꢍ ꢎꢈ ꢏ ꢇ ꢐꢀꢈ ꢏꢑꢒꢓ ꢈ ꢂ ꢎꢇꢀ ꢓꢔ ꢑꢍ ꢏ
ꢁꢍꢎ ꢈꢏ ꢍꢕ ꢈꢏ ꢈꢀ ꢔꢈ ꢏꢐ ꢈꢀ ꢖ ꢁꢗ ꢈꢘ ꢁ ꢍꢎꢈ ꢏꢈ ꢙ ꢙ ꢈꢕꢇ ꢓ ꢈꢂ
FEATURES
DESCRIPTION
D
Integrated Power Interface Switch for IEEE
802.3af Powered Devices (PDs)
Acting as an interface between the power sourcing
equipment (PSE) and the powered device (PD), the
TPS2370 performs all detection, classification, inrush
current limiting, and switch FET control that is
necessary for compliance with the IEEE 802.3af
Standard. An internal 0.3-Ω FET provides maximum
power delivery. As an additional feature, the TPS2370
interfaces with the enable/soft-start signal of a dc-to-dc
converter, eliminating the need to have an accurate
UVLO in the dc-to-dc converter.
D
Provides PD Detection Signature
D
Provides PD Classification Signature
(Class 0−4)
D
D
D
Programmable Inrush Current Limit
Internal 0.3-Ω Low-Side FET
Interfaces to DC/DC Soft-Start for DC/DC
Enable
At low input voltages (1.8 V to 10 V), the TPS2370
draws less than 12 µA, allowing accurate sensing of the
external 24.9-kΩ discovery resistor. At input voltages
between 15 V and 20 V, an external resistor sets the
level of current to be drawn during classification mode.
TPS2370 is compatible with current as well as voltage
measurement schemes for classification. Above 20-V
input, the classification current is shut off, reducing
internal power dissipation.
D
Internal Thermal Protection – Disconnects PD
Load
D
Minimal External Parts Count
D
8-Pin SOIC, 8-Pin TSSOP Packages
APPLICATIONS
D
D
D
D
VoIP Phones
Internet Appliances
The TPS2370 drives an internal low-side FET for
control of the return side of the power path. The internal
FET is turned on when the input voltage reaches 40 V
and above. When the input voltage decreases, the FET
remains on until the input voltage drops to below 30 V.
Wireless LAN Access Points
Bluetooth Access Points
TYPICAL APPLICATION
V+
24.9 kꢀ
8
3
C
DCDCIN
0.1 ꢁf
TPS2370
44 V
TO
R
LIM
DC/DC
Converter/
Controller
1
2
4
VREG
Ethernet
Appliance
57 V
6
5
SMAJ54A
R
CLASS
C
SS
UDG−03057
V−
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. Bluetooth is a trademark of Bluetooth SIC, Inc.
ꢁꢏ ꢍ ꢙꢚ ꢓ ꢀꢇ ꢍꢐ ꢙ ꢒꢀꢒ ꢛꢜ ꢌꢗ ꢝ ꢞꢋ ꢟꢛꢗꢜ ꢛꢠ ꢡꢢ ꢝ ꢝ ꢣꢜꢟ ꢋꢠ ꢗꢌ ꢤꢢꢥ ꢦꢛꢡ ꢋꢟꢛ ꢗꢜ ꢧꢋ ꢟꢣꢊ ꢁꢝ ꢗꢧꢢ ꢡꢟꢠ
ꢡ ꢗꢜ ꢌꢗꢝ ꢞ ꢟꢗ ꢠ ꢤꢣ ꢡ ꢛ ꢌꢛ ꢡ ꢋ ꢟꢛ ꢗꢜꢠ ꢤ ꢣꢝ ꢟꢨꢣ ꢟꢣ ꢝ ꢞꢠ ꢗꢌ ꢀꢣꢩ ꢋꢠ ꢇꢜꢠ ꢟꢝ ꢢꢞ ꢣꢜꢟ ꢠ ꢠꢟ ꢋꢜꢧ ꢋꢝ ꢧ ꢪ ꢋꢝ ꢝ ꢋ ꢜꢟꢫꢊ
ꢁꢝ ꢗ ꢧꢢꢡ ꢟ ꢛꢗ ꢜ ꢤꢝ ꢗ ꢡ ꢣ ꢠ ꢠ ꢛꢜ ꢬ ꢧꢗ ꢣ ꢠ ꢜꢗꢟ ꢜꢣ ꢡꢣ ꢠꢠ ꢋꢝ ꢛꢦ ꢫ ꢛꢜꢡ ꢦꢢꢧ ꢣ ꢟꢣ ꢠꢟꢛ ꢜꢬ ꢗꢌ ꢋꢦ ꢦ ꢤꢋ ꢝ ꢋꢞ ꢣꢟꢣ ꢝ ꢠꢊ
Copyright 2002 − 2004, Texas Instruments Incorporated
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DESCRIPTION (CONTINUED)
During initial turnon of the switch (inrush mode), an external resistor is used to program the inrush current, allowing a wide
range of capacitor values to be used at the load. According to IEEE 802.3af specification, inrush current of 400 mA is
allowed only for 50 ms, limiting the load capacitor to approximately 180 µF. A programmable inrush current limit removes
this limitation, allowing a larger capacitor to be used with a lower inrush current limit.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
(1)
PACKAGE
T
PART NUMBER
TPS2370PW
TPS2370D
A
Plastic TSSOP (PW)
Plastic SOIC (D)
0°C to 70°C
(1)
The PW and D packages are also available taped and reeled. Add an R suffix to the device type (i.e., TPS2370PWR).
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted
(2)
TPS2370
UNIT
ILIM
4
CLASS
12
68
Input voltage range, wrt V
EE
V
DET, RTN, EN_DC, VDD
EN_DC (wrt RTN)
5
Operating junction temperature range, T
−55 to 150
−65 to 150
300
°C
°C
°C
J
Storage temperature, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Input voltage, V
48
57
70
V
I
Operating junction temperature, T
0
°C
J
DISSIPATION RATINGS(3)(4)
T
< 25°C
T
= 25°C
T = 70°C
A
POWER RATING
A
A
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
PACKAGE
POWER RATING
DERATING
FACTOR
8-Pin Plastic TSSOP (PW)
8-Pin Plastic SOIC (D)
258.5°C/W
176.0°C/W
464 mW
682 mW
3.9 mW/°C
5.7 mW/°C
290 mW
426 mW
(3)
(4)
Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias
Maximum power dissipation may be limited by overcurrent protection.
2
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ELECTRICAL CHARACTERISTICS
V
DD
= 48 V; T = 0°C to 70°C; all voltages and currents are with respect to VEE; (unless otherwise noted)
A
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Offset current
Sleep current
VDD = 1.8 V, DET = OPEN
1.8 V ≤ VDD < 10 V, DET = OPEN
3
12
I
I
5
73
DD
µA
R
= 24.9 kΩ, VDD = 1.8 V
= 24.9 kΩ, VDD = 9.5 V
70
380
76
DET
DET
Detection load current
DET
R
390
12.5
22.5
400
14.0
23.5
Turn on
10.0
21.5
Classification current threshold
VDD current class 0
V
Turn off
0.44 W ≤ P
15 V ≤ VDD ≤ 20 V,
≤ 12.95 W,
PoE
2.2
10.4
18.1
27.7
38.5
2.5
10.8
18.6
28.4
39.6
2.8
11.5
19.5
29.9
42.0
R
= 4.42 kΩ
= 953 Ω
= 549 Ω
= 357 Ω
CLASS
0.44 W ≤ P ≤ 3.84 W,
PoE
15 V ≤ VDD ≤ 20 V,
VDD current class 1
R
CLASS
3.84 W ≤ P
PoE
15 V ≤ VDD ≤ 20 V,
≤ 6.49 W,
VDD current class 2
mA
R
CLASS
6.49 W ≤ P
PoE
15 V ≤ VDD ≤ 20 V,
≤ 12.95 W,
VDD current class 3
R
CLASS
Reserved for future use,
VDD current class 4
15 V ≤ VDD ≤ 20 V,
30 V ≤ VDD ≤ 57 V,
Turn on
R
R
= 255 Ω
= 255 Ω
CLASS
VDD quiescent current
500
40.2
31.4
8.8
800
41.8
32.6
9.8
µA
CLASS
38.6
30.2
7.8
Input UVLO threshold
Turn off
V
UVLO hysteresis
EN_DC sink current
RTN threshold for EN_DC
40
80
200
1.8
µA
V
1.2
1.5
DMOS R
DS(on)
I
= 200 mA
0.15
405
180
0.30
455
250
144
20
0.60
505
300
Ω
RTN
Full load current limit
V
< 1.5 V
RTN
mA
ILIM current limit programming
Thermal shutdown temperature
Thermal shutdown hysteresis
R
= 125 kΩ, V
> 1.5 V during startup
LIM
RTN
°C
D OR PW PACKAGE
(TOP VIEW)
ILIM
VDD
NC
EN_DC
RTN
1
2
3
4
8
7
6
5
CLASS
DET
VEE
3
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TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
CLASS
NO.
Sets classification level with a single resistor to VEE. A precision voltage of 10 V is applied to this pin during
classification. R values listed in Table 1.
2
O
CLASS
DET
3
6
O
O
Connect the 24.9-kΩ detection resistor (R
) between this pin and VDD.
DET
Ties to dc-to-dc converter’s shutdown or soft-start pin. Sinks 80 µA until the load capacitor is fully charged.
Sets start-up current limit level with a resistor to VEE. If using C > 180 µF, I must be less than
EN_DC
DC2DCIN RUSH
ILIM
1
O
400 mA. Extra capacitance on ILIM pin can cause oscillations in the current waveform.
Return pin. Connect this pin to input return side of the dc-to-dc converter.
Connection to PD input port positive voltage.
RTN
VDD
VEE
5
8
4
O
I
I
Input side power return for the controller.
25 kW
RLIM
(1)
( )
1 A
+ 450 mA * ǒ Ǔ
IINRUSH
DETAILED PIN DESCRIPTIONS
ILIM (Pin 1)
Inrush current limiting pin. This pin is used to program the inrush current of the device. By placing a resistor to VEE
from this pin, the inrush current into the load is limited via the following equation:
25 kW
( )
1 A
+ 450 mA * ǒ Ǔ
I
INRUSH
R
LIM
(1)
CLASS (Pin 2)
Classification pin. The PD can be optionally classified by adding a resistor from this pin to ground. The resistor specific
to each class is given in Table 1: PoE Classification Resistance Values.
DET (Pin3)
Detection pin. This pin is used to set up the detection resistance during PD detection. By tying a resistor, R
this pin to VDD, the user sets the detection resistance. It should be noted that the device itself looks like approximately
, from
DET
1 MΩ of resistance in parallel with R
.
DET
VEE (Pin 4)
Negative supply to the device.
RET (Pin 5)
Negative supply to the load. This pin is the drain side of a FET between the RET pin and the VEE pin, providing hot
swap capabilities to the load. When the FET is switched on, there is approximately 300 mΩ between this pin and VEE.
EN_DC (Pin 6)
Enable pin for the load. This pin is intended to be used with a dc-to-dc coverter with a soft start capacitor. When power
is not available to the dc-to-dc converter, this pin sinks 80 µA and holds off the soft-start capacitor on the dc-to-dc
converter. Once the voltage across the load is within 1.5 V of its final value, the EN_DC pin stops drawing current
and becomes high impedance, allowing the dc-to-dc converter to soft start normally.
VDD (Pin 8)
Positive supply to the device.
4
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Table 1. PoE Classification Resistance Values
RESISTANCE
) VALUE (Ω)
POWERED DEVICES
(PDs) Power (W)
CLASSIFICATION
CURRENT (mA)
CLASS
(R
CLASS
4420
0
1
2
3
4
0.44 − 12.95
0.44 − 3.84
2.5
953
549
357
255
10.8
18.6
28.4
39.6
3.84 − 6.49
6.49 − 12.95
reserved for future use
INTERNAL BLOCK DIAGRAM
TO
DC/DC’s
Positive Input
+VE SUPPLY
VDD
R
DET
24.9 kΩ
8
UVLO, Detection,
Classification Control
CLASS
N/C
LDO
10 V
2
3
7
Precision Bandgap Reference
Precision Current Source
DET
Internal Supplies
0.1 ꢁf
5 V
15 V
EN_DC
RTN
80 µA
6
5
1.5 V
R
CLASS
20 µA
2 kΩ
ILIM
1
+
TO
DC/DC’s
INPUT
RETURN
0.1 Ω
4
R
LIM
VEE
−VE SUPPLY
UDG−02102
5
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STATE DIAGRAM
DETECTION
V
< 10 V
DD
I
= VDD/(R
Switch Resistance > 100 MΩ
) || 1 MΩ
DET
DD
CLASSIFICATION
10 V < V
DD
< 22 V
CLASS
I
≅ 10 V/(R
)
DD
Switch Resistance > 100 MΩ
INRUSH MODE
V
> 40 V (rising edge)
= 450 mA − (25 kΩ/R
Switch Resistance ≈ 100 Ω
V
> 1.5 V
DD
= I
RTN
I
) x (1 A)
LIM
RET INRUSH
LATCH OFF
> 30 V < 1 mA
Switch Resistance ꢂ 100 MΩ
V
I
DD
DD
NORMAL OPERATION
V
> 30 V
) < 450 mA
DD
(I
= I
RET LOAD
NO
Switch Resistance ≈ 0.3 Ω
YES
TSD
OVERLOAD/FAULT
Count < 7?
V
RET
> 30 V
= 450 mA
DD
I
Switch Resistance ≈ 100 Ω
THERMAL SHUTDOWN
YES
NO
V > 30 V
DD
< 1 mA
T
J
< 145 _C?
I
DD
Switch Resistance > 100 MΩ
MACHINE STATE
Detection
Normal Operation
(I = 450 mA)
UVLO ON
(Rising Edge)
UVLO OFF
(Falling Edge)
(R
LOAD
= 25 kΩ)
Classification
DD
50
57
0
2
4
6
8
10
15
20
25
31
40
44
6
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APPLICATION INFORMATION
OVERVIEW
With the addition of power via media-dependent interface (MDI) to the IEEE 802.3af Standard, all data terminal
equipment (DTE) now has the option to receive power over existing cabling that is used for data transmission.
The IEEE 802.3af Standard defines the requirements associated with providing and receiving power over the
existing cabling. The power sourcing equipment (PSE) provides the power on the cable and the powered device
(PD) receives the power. As part of the IEEE 802.3af Standard, the interface between the PSE and PD is
defined as it relates to the detection and classification protocol.
POWER SOURCING EQUIPMENT DETECTION OF A POWERED DEVICE
A powered device (PD) draws power or requests power by participating in a PD detection algorithm. This
algorithm requires the power sourcing equipment (PSE) to probe the link looking for a valid PD. The PSE probes
the link by sending out a voltage between 2.8 V and 10 V across the power lines. A valid PD detects this voltage
and places a resistance of between 23.75 kΩ and 26.25 kΩ across the power lines. Naturally, the current varies
depending on the input voltage. On detecting this current, the PSE concludes that a valid PD is connected at the
end of the ethernet cable and is requesting power.
If the powered device (PD) is in a state in which it does not accept power, the PD is required to place a
resistance above or below the values listed for a valid PD. On the lower end, a range between 12 kΩ and
23.75 kΩ signifies that the PD does not require power. On the higher end, the range is defined to be between
26.25 kΩ and 45 kΩ . Any resistance value less than 12 kΩ and greater than 45 kΩ, is interpreted by the PSE
as a nonvalid PD detection signature.
The TPS2370 participates in the detection algorithm by activating an internal FET, which connects the DET pin of
the device to VEE. As a result, any resistance connected between VDD and the DET pin of the TPS2370 is, in
effect, across the power lines. This internal FET is active only when input power to the PD is between 2.8 V and
10 V.
POWER SOURCING EQUIPMENT CLASSIFICATION OF A POWERED DEVICE
After the detection phase, the PSE can optionally initiate a classification of the PD. The classification of a PD is
used by the PSE to determine the maximum power required by the PD during normal operation. Five different
levels of classification are defined by the IEEE 802.3af Standard. These levels are shown in Table 2.
Table 2. Powered Device Classification Levels
POWER DEVICE
POWER
CLASSIFICATION
CURRENT
(mA)
CLASS
USAGE
(W)
MIN
0.44
0.44
3.84
6.49
MAX
12.95
3.84
MIN
0
MAX
4
0
1
2
3
4
Default
Optional
Optional
Optional
Not allowed
9
12
20
30
44
6.49
17
26
36
12.95
reserved for future use
Classification of the PD is optionally performed by the PSE only after a valid PD has been detected. To
determine PD classification, the PSE increases the voltage across the power lines to between 15.5 V and 20.5 V.
The amount of current drawn by the PD determines the classification (see Table 2).
When the input voltage to the TPS2370 is between 14.0 V and 20.5 V, the TPS2370 uses an internal regulator to
generate a fixed voltage on the CLASS pin. A resistor connected between the CLASS pin and VEE draws a fixed
amount of current and thereby defines the classification level of the PD.
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APPLICATION INFORMATION
POWER SOURCING EQUIPMENT POWER TO THE POWERED DEVICE
On completion of the detection and optional classification phases, the PSE ramps its output voltage above 42 V .
Once the UVLO threshold has been reached, the internal FET is turned on. At this point, the PD begins to
operate normally and it continues to operate normally as long as the input voltage remains above 30 V. For most
PDs, this input voltage is down-converted using an onboard dc-to-dc converter to generate the required voltages.
The TPS2370 is designed to apply the PSE output voltage of 36 V to 57 V across the input of the onboard
dc-to-dc converter. This is accomplished on the TPS2370 by turning on an internal pass FET located across the
power return.
PROGRAMMING THE INRUSH CURRENT
During the initial turnon of the pass FET, an inrush current is created from the charging of the capacitance at the
input of the dc-to-dc converter. According to the IEEE 802.3af specification, if the input capacitance is less than
180 µF, the PSE limits the inrush current. If the input capacitance is greater than 180 µF, the IEEE 802.3af
specification requires the PD to limit the inrush current to less than 400 mA.
In order to satisfy the IEEE 802.3af requirements, the TPS2370 has been designed for a typical current limit of
450 mA. This current limit setting satisfies the normal operation requirements as well as the inrush requirements
for a capacitive load of 180 µF or less. If a larger load capacitor is desired, the TPS2370 has been designed with
a programmable inrush current limit feature. This feature allows the designer the option of using a capacitor
larger than 180 µF. Note that the inrush current feature may also be used to lower voltage drops in the cabling
between the PSE and the PD during start-up.
The programmable inrush current limit has a range of 50 mA to 449 mA. The limit is set by connecting an
external resistor from ILIM (pin 1) to VEE (pin 4) of the TPS2370. Equation (1) shows the calculation for the
programmable inrush current limit.
25 kW
( )
1 A
+ 450 mA * ǒ Ǔ
I
INRUSH
R
LIM
(2)
where R
is a value between 63.5 kΩ and 25 MΩ.
LIM
USING EN_DC AS A SOFT-START OR A POWER-GOOD FUNCTION
The EN_DC pin is an output intended for use as a soft-start for a dc-to-dc converter. During the initial turnon of
the pass FET, an internal 80-µA current sink is enabled on the EN_DC pin. This internal current sink is removed
only after the load capacitance has been charged to within 1.5-V of the supply voltage. By connecting the
EN_DC output to the soft-start capacitor of a dc-to-dc converter, the internal current sink keeps the dc-to-dc
converter off during start-up. Once the voltage across the converter has reached within 1.5 V of full voltage, the
dc-to-dc converter is allowed to soft start.
For operation as a power-good output, the EN_DC requires an external pull-up resistor. A 1-MΩ resistor is
recommended. The EN_DC output also requires a clamp to limit the output voltage to within recommended
operating levels. A 5-V zener diode connected between EN_DC and RTN (pin 5 of the TPS2370) is
recommended. This configuration allows the EN_DC pin to act as an open-drain output with which many
designers are more familiar.
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APPLICATION INFORMATION
SURGE SUPPRESSION
As specified in the Absolute Maximum Ratings table, the absolute maximum input voltage of the TPS2370 is
68 V. The IEEE 802.3af Power-over-Ethernet Standard specifies the voltage range of PSE output as between
44 V and 57 V. This PSE output voltage range would be reduced by cable, connector, and other IR drops
between the PSE and the TPS2370 in the PD. However, the use of extended cable lengths and transformers in
some applications may induce transients in excess of 68 V during a hot plug event. To manage these transient
events and keep them from significantly exceeding the application’s maximum voltage, a transorb such as the
SMAJ54A should be placed between the positive input supply, VDD (pin 8), and the negative input supply, VEE
(pin 4). This, combined with a 0.1-µF bypass capacitor in parallel with the transorb, helps to protect the TPS2370
from damage caused by transients during hot plug events. The transorb or zener diode should be selected such
that it does not zener below the maximum required application voltage of 57 V, but before reaching the 68-V
absolute maximum rating. For layout purposes, the 0.1-µF capacitor should be placed as close as possible to the
device; the transorb or zener diode should be placed as close to the supply connector as possible. Based on the
nature of the PD application, these measures should be considered an implementation requirement.
USE OF BARREL RECTIFIERS
Many applications use barrel rectifiers after the RJ-45 connector in order to be polarity insensitive. Barrel
rectifiers in front of the TPS2370 cause the voltages at the device to be lower than the voltages at the RJ-45.
The TPS2370 allows for this and is IEEE802.3af compliant during the detection and classification phases. For
the detection phase, the device begins detection for voltages as low as 1.3 V across the supply pins. For the
optional classification phase, the device is guaranteed to start classification below 14 V across the supply pins.
Once classification has been engaged, it becomes latched-in and further voltage drops due to cable resistance
and class current does not cause it to switch out of classification. Thus, the TPS2370 allows for at least a 1.5-V
drop between the RJ-45 and the TPS2370 due to barrel rectifiers during both detection and classification phases.
However, in cases where the PSE is operating at the minimum class voltage (15.5 V) and there is a 20-Ω, 100-m
cable between the PSE and the PD, class 3 devices may not classify correctly when using barrel rectifiers. Class
3 device designs should include Schottky diodes to handle all corner cases, or switch to class 0 devices when
using barrel rectifiers.
THERMAL SHUTDOWN
In the event of a short circuit or overload condition, the TPS2370 begins to heat up until thermal shutdown is
reached. Once thermal shutdown is reached, the internal FET is switched off, removing the load from the supply.
After the device has cooled sufficiently, it retries by restarting the internal FET. If the overload or short is not
removed, the device cycles thermal shutdown seven times before latching the internal FET off. Once the internal
FET is latched off, power needs to be cycled to reset the latch.
9
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆ
www.ti.com
SLUS537C − AUGUST 2002 − REVISED MARCH 2004
APPLICATION INFORMATION
Figure 1 shows an application where 40 V < V < 57 V. In this case, the brick supply is greater then 40 V and
IN
goes through TPS2370.
PoE POWERED DEVICE FRONT END
RJ−45
3
V+
RX
R
DET
6
1
8
C
DCDCIN
3
1
2
R
LIM
TX
VREG
DC/DC
CONVERTER
ETHERNET
DEVICE
TPS2370
6
5
2
4
5
7
8
C
SS
R
S
P
A
R
E
CLASS
V−
4
DC
BRICK
SUPPLY
Figure 1. For Applications 40 V < V < 57 V.
IN
Figure 2 shows an application where V < 40 V. In this application, the brick supply is bypassing the switch.
IN
Consequently, the dc-to-dc converter can operate from any voltage. However, for V
< 23 V, a class 0
BRICK
resistor (R
= 4.42 kΩ) is recommended. This minimizes the power dissipation in TPS2370 if V
falls in
CLASS
BRICK
the classification voltage range (15 V to 20 V). The 80-µA current sink on EN_DC pin is enabled only if VDD > 40
V.
PoE POWERED DEVICE FRONT END
RJ−45
3
V+
RX
R
DET
6
1
8
C
DCDCIN
3
1
2
R
LIM
TX
VREG
DC/DC
CONVERTER
ETHERNET
DEVICE
TPS2370
6
5
2
4
R
CLASS
S
P
A
R
E
C
SS
5
7
8
V−
4
DC
BRICK
SUPPLY
Figure 2. For Applications V < 40 V.
IN
10
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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