TPS2371DRG4 [TI]

DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8;


型号：	TPS2371DRG4
厂家：	TEXAS INSTRUMENTS
描述：	DATACOM, NETWORK INTERFACE SUPPORT CIRCUIT, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8 电信光电二极管电信集成电路
文件：	总19页 (文件大小：861K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

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FEATURES

DESCRIPTION

Integrated Power Interface Switch for IEEE

802.3af Powered Devices (PDs)

Acting as an interface between the Power Source

Equipment (PSE) and the Powered Device (PD),

the TPS2371 performs all detection, class−

ification, inrush current limiting, and switch FET

control that is necessary for compatibility with

Legacy/IEEE 802.3af Standard. The TPS2371

incorporates precision UVLO thresholds and

hysteresis as well as a UVLO off-time delay to

enable Legacy IEEE802.3af PoE compatibilty. An

internal 0.3-Ω FET provides maximum power

delivery. As an additional feature, the TPS2371

interfaces with the enable/soft-start signal of a

dc-to-dc converter, eliminating the need to have

an accurate UVLO in the dc-to-dc converter.

Precision UVLO Thresholds

20-ms UVLO Off-Time Delay

Provides PD Detection Signature

Provides PD Classification Signature

(Class 0−4)

Programmable Inrush Current Limit

Internal 0.3-Ω Low-Side FET

Interfaces to DC/DC Soft-Start for DC/DC

Enable

Internal Thermal Protection – Disconnects

PD Load

At low input voltages (1.8 V to 10 V), the TPS2371

draws less than 12 µA, allowing accurate sensing

of the external 24.9-kΩ discovery resistor. At input

voltages between 15 V and 20 V, an external

resistor sets the level of current to be drawn during

classification mode. TPS2371 is compatible with

current as well as voltage measurement schemes

for classification. Above 20-V input, the

classification current is shut off, reducing internal

power dissipation.

8-Pin SOIC, 8-Pin TSSOP Packages

APPLICATIONS

VoIP Phones

Internet Appliances

Wireless LAN Access Points

Bluetooth Access Points

SIMPLIFIED APPLICATION DIAGRAM

V+

DET

DCDCIN

BYPASS

TPS2371

44 V

57 V

LIM

DEL

DC/DC

Converter/

Controller

VREG

Ethernet

Appliance

LIM

CLASS

SMAJ54A

5 V

V−

UDG−03092

Bluetooth is a trademark of the Bluetooth SIG, Inc.

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

DESCRIPTION (continued)

The TPS2371 drives an internal low-side FET for control of the return side of the power path. The internal FET

is turned on when the input voltage reaches 36 V and above. When the input voltage decreases, the FET

remains on until the input voltage drops to below 30 V.

During initial turn-on of the switch (inrush mode), an external resistor is used to program the inrush current,

allowing a wide range of capacitor values to be used at the load. According to IEEE 802.3af specification, inrush

current of 400 mA is allowed only for 50 ms, limiting the load capacitor to approximately 180 µF. A programmable

inrush current limit removes this limitation, allowing a larger capacitor to be used with a lower inrush current limit.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

Over operating free-air temperature range unless otherwise noted

(2)

TPS2371

UNIT

ILIM, DELAY

CLASS

Input voltage range, wrt V

DET, RTN, EN_DC, VDD

Operating junction temperature range, T

−55 to 150

−65 to 150

300

°C

Storage temperature, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(2)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”

is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Input voltage, V

Operating junction temperature, T

°C

(3)(4)

DISSIPATION RATINGS

< 25°C

= 25°C

T = 70°C

POWER RATING

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

PACKAGE

POWER RATING

DERATING

FACTOR

8-Pin Plastic TSSOP (PW)

8-Pin Plastic SOIC (D)

258.5°C/W

176.0°C/W

464 mW

682 mW

3.9 mW/°C

5.7 mW/°C

290 mW

426 mW

(3)

(4)

Test board conditions:

1. 3” x 3”, 4 layers, thickness: 0.062”

2. 1.5 oz. copper traces located on the top of the PCB

3. 1.5 oz. copper ground plane on the bottom of the PCB

4. 0.5 oz. copper ground planes on the 2 internal layers

5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)

Maximum power dissipation may be limited by over current protection.

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

ELECTRICAL CHARACTERISTICS

= 48 V; T = 0°C to 70°C; all voltages and currents are with respect to VEE; (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SUPPLY

Offset current

VDD = 1.8 V, DET = OPEN

1.8 V ≤ VDD < 10 V, DET = OPEN

Sleep current

µA

= 24.9 kΩ, VDD = 1.8 V

= 24.9 kΩ, VDD = 9.5 V

380

DET

Detection load current

DET

390

12.5

22.5

400

14.0

23.5

Turn on

10.0

21.5

Classification current threshold

VDD current class 0

Turn off

0.44 W ≤ P

15 V ≤ VDD ≤ 20 V,

≤ 12.95 W,

PoE

2.2

10.4

18.1

27.7

38.5

2.5

10.8

18.6

28.4

39.6

2.8

11.5

19.5

29.9

42.0

= 4.42 kΩ

= 953 Ω

= 549 Ω

= 357 Ω

CLASS

0.44 W ≤ P ≤ 3.84 W,

PoE

15 V ≤ VDD ≤ 20 V,

VDD current class 1

CLASS

3.84 W ≤ P

PoE

15 V ≤ VDD ≤ 20 V,

≤ 6.49 W,

VDD current class 2

CLASS

6.49 W ≤ P

≤ 12.95 W,

PoE

15 V ≤ VDD ≤ 20 V,

VDD current class 3

CLASS

Reserved for future use,

VDD current class 4

15 V ≤ VDD ≤ 20 V,

30 V ≤ VDD ≤ 57 V,

Turn on

= 255 Ω

CLASS

VDD quiescent current

500

35.0

30.5

4.5

800

36.1

31.5

µA

33.9

29.5

4.3

Input UVLO threshold

Turn off

UVLO hysteresis

UVLO off-time delay

EN_DC sink current

RTN threshold for EN_DC

= 180 nF

µA

DELAY

1.2

200

1.8

1.5

DMOS R

DS(on)

= 200 mA

0.15

405

180

0.30

455

250

144

0.60

505

300

Ω

RTN

Full load current limit

< 1.5 V

RTN

ILIM current limit programming

Thermal shutdown temperature

Thermal shutdown hysteresis

= 125 kΩ, V

> 1.5 V during startup

LIM

RTN

°C

D OR PW PACKAGE

(TOP VIEW)

ILIM

VDD

CLASS

DET

DELAY

EN_DC

RTN

VEE

ORDERING INFORMATION

(1)

PACKAGE

PART NUMBER

TPS2371PW

TPS2371D

Plastic TSSOP (PW)

Plastic SOIC (D)

0°C to 70°C

(1)

The PW and D packages are also available taped and reeled. Add an R suffix to the device type (i.e., TPS2371PWR).

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

Sets classification level with a single resistor to VEE. A precision voltage of 10.0 V is applied to this pin during

CLASS

classification. R

CLASS

values listed in Table 1.

UVLO turn-off delay programming. Connect a capacitor between VCC and this pin to program the UVLO

turn-off delay.

(2)

DELAY

DET

Connect the 24.9kΩ detection resistor (R ) between this pin and VDD.

DET

EN_DC

(1)

Ties to dc-to-dc converter’s shutdown or soft-start pin. Sinks 80µA until the load capacitor is fully charged.

Sets startup current limit level with a resistor to VEE. If using C > 180 µF, I must be less than

DC2DCIN RUSH

ILIM

400 mA. Extra capacitance on ILIM pin can cause oscillations in the current waveform.

Return pin. Connect this pin to input return side of the dc-to-dc converter.

Connection to PD input port positive voltage.

RTN

VDD

VEE

Input side power return for the controller.

25 kW

R_LIM

( )

1 A

_{+ 450 mA *}ǒ Ǔ

NOTE 1: I_INRUSH

NOTE 2: T_DELAY

100 ms

₊ǒ Ǔ

C_DELAY

DETAILED PIN DESCRIPTIONS

ILIM (Pin 1)

Inrush current limiting pin. This pin is used to program the inrush current of the device. Due to the low UVLO

hysteresis of this device, a 1.0-µF capacitor from this pin to VEE is necessary to allow startup with 20 Ω in series

with V

as required by the IEEE standards. By placing a resistor to VEE from this pin, the inrush current into

the load will be limited via the following equation:

25 kW

( )

1 A

_{+ 450 mA *}ǒ Ǔ

INRUSH

LIM

(1)

CLASS (Pin 2)

Classification pin. The PD can be optionally classified by adding a resistor from this pin to ground. The resistor

specific to each class is given in Table 1: PoE Classification Resistance Values.

DET (Pin3)

Detection pin. This pin is used to set up the detection resistance during PD detection. By tying a resistor, R

from this pin to VDD, the user sets the detection resistance. It should be noted that the device itself looks like

DET

approximately 1 MΩ of resistance in parallel with R

DET

VEE (Pin 4)

Negative supply to the device.

RET (Pin 5)

Negative supply to the load. This pin is the drain side of a FET between the RET pin and the VEE pin, providing

hot swap capabilities to the load. When the FET is switched on, there is approximately 300mΩ between this

pin and VEE.

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

DETAILED PIN DESCRIPTIONS (continued)

EN_DC (Pin 6)

Enable pin for the load. This pin is intended to be used with a dc-to-dc coverter with a soft start capacitor. When

power is not available to the dc-to-dc converter, this pin sinks 80-µA and hold off the softstart cap on the dc-to-dc

converter. Once the voltage across the load is within 1.5 V of its final value, the EN_DC pin stops drawing current

and become high impedance, allowing the dc-to-dc to soft start normally.

DELAY (Pin 7)

This pin controls the amount of time that the device ignores an undervoltage condition on VDD. That time is set

by the following equation:

100 ms

₊ǒ Ǔ

DELAY

(2)

VDD (Pin 8)

Positive supply to the device.

Table 1. PoE Classification Resistance Values

RESISTANCE

) VALUE (Ω)

POWERED DEVICES

(PDs) Power (W)

CLASSIFICATION

CURRENT (mA)

CLASS

4420

0.44 − 12.95

0.44 − 3.84

2.5

953

549

357

255

10.8

18.6

28.4

39.6

3.84 − 6.49

6.49 − 12.95

reserved for future use

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

INTERNAL BLOCK DIAGRAM

+VE SUPPLY

TO DC/DC’s

EN/SS

VDD

DET

24.9 kΩ

DELAY

UVLO, Detection,

Classification Control

CLASS

LDO

10 V

Precision Bandgap Reference

Precision Current Source

Internal Supplies

DET

BYBASS

VEE

EN_DC

5 V

15 V

80 µA

60 V

1.5 V

CLASS

5 V

RTN

ILIM

20 µA

2 kΩ

TO DC/DC’s

INPUT RETURN

0.1 Ω

LIM

VEE

LIM

−VE SUPPLY

UDG−03093

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

STATE DIAGRAM

DETECTION

< 10 V

= VDD/(R

Switch Resistance > 100 MΩ

) || 1 MΩ

DET

CLASSIFICATION

10 V < V

< 22 V

CLASS

≅ 10 V/(R

)

Switch Resistance > 100 MΩ

INRUSH MODE

> 36 V (rising edge)

= 450 mA − (25 kΩ/R

Switch Resistance ≈ 100 Ω

> 1.5 V

RTN

= I

) x (1 A)

RET INRUSH

LIM

LATCH OFF

> 30 V

< 1 mA

Switch Resistance ꢀ 100

MΩ

NORMAL OPERATION

> 30 V

) < 450 mA

= I

RET LOAD

Switch Resistance ≈ 0.3 Ω

YES

TSD

OVERLOAD/FAULT

Count < 7?

RET

> 30 V

= 450 mA

Switch Resistance ≈ 100 Ω

THERMAL SHUTDOWN

YES

V > 30 V

< 1 mA

< 145 _C?

Switch Resistance > 100 MΩ

MACHINE STATE

Detection

Normal Operation

(I = 450 mA)

UVLO ON

(Rising Edge)

UVLO OFF

(Falling Edge)

= 25 kΩ)

LOAD

Classification

30.5

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

APPLICATION INFORMATION

OVERVIEW

With the addition of power via media dependent interface (MDI) to the IEEE 802.3af Standard, all data terminal

equipment (DTE) now has the option to receive power over existing cabling that is used for data transmission.

The IEEE 802.3af Standard defines the requirements associated with providing and receiving power over the

existing cabling. The power sourcing equipment (PSE) provides the power on the cable and the powered device

(PD) receives the power. As part of the IEEE 802.3af Standard, the interface between the PSE and PD is defined

as it relates to the detection and classification protocol.

POWER SOURCING EQUIPMENT DETECTION OF A POWERED DEVICE

A powered device (PD) draws power or requests power by participating in a PD detection algorithm. This

algorithm requires the power sourcing equipment (PSE) to probe the link looking for a valid PD. The PSE probes

the link by sending out a voltage between 2.8 V and 10 V across the power lines. A valid PD detects this voltage

and places a resistance of between 23.75 kΩ and 26.25kΩ across the power lines. Naturally, the current varies

depending on the input voltage. Upon detecting this current, the PSE concludes that a valid PD is connected

at the end of the ethernet cable and is requesting power.

If the powered device (PD) is in a state in which it does not accept power, the PD is required to place a resistance

above or below the values listed for a valid PD. On the lower end, a range between 12 kΩ and 23.75 kΩ signifies

that the PD does not require power. On the higher end, the range is defined to be between 26.25 kΩ and 45

kΩ . Any resistance value less than 12 kΩ and greater than 45 kΩ, is interpreted by the PSE as a non-valid PD

detection signature.

The TPS2371 participates in the detection algorithm by activating an internal FET, which connects the DET pin

of the device to VEE. As a result, any resistance connected between VDD and the DET pin of the TPS2371 is,

in effect, across the power lines. This internal FET is active only when input power to the PD is between 2.8 V

and 10 V.

POWER SOURCING EQUIPMENT CLASSIFICATION OF A POWERED DEVICE

After the detection phase, the PSE can optionally initiate a classification of the PD. The classification of a PD

is used by the PSE to determine the maximum power required by the PD during normal operation. Five different

levels of classification are defined by the IEEE 802.3af Standard. These levels are shown in Table 2.

Table 2. Powered Device Classification Levels

POWER DEVICE

POWER

CLASSIFICATION

CURRENT

(mA)

CLASS

USAGE

(W)

MIN

0.44

3.84

6.49

MAX

12.95

3.84

MIN

MAX

Default

Optional

6.49

Optional

12.95

Not allowed

reserved for future use

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

APPLICATION INFORMATION

Classification of the PD is optionally performed by the PSE only after a valid PD has been detected. To determine

PD classification, the PSE increases the voltage across the power lines to between 15.5 V and 20.5 V. The

amount of current drawn by the PD determines the classification (see Table 2).

When the input voltage to the TPS2371 is between 14.0 V and 20.5 V, the TPS2371 uses an internal regulator

to generate a fixed voltage on the CLASS pin. A resistor connected between the CLASS pin and VEE draws

a fixed amount of current and thereby defines the classification level of the PD.

POWER SOURCING EQUIPMENT POWER TO THE POWERED DEVICE

Upon completion of the detection and optional classification phases, the PSE ramps its output voltage above

36 V . Once the UVLO threshold has been reached, the internal FET is turned on. At this point, the PD begins

to operate normally and it continues to operate normally as long as the input voltage remains above 30 V. For

most PDs, this input voltage is down-converted using an on board dc-to-dc converter to generate the required

voltages.

The TPS2371 is designed to apply the PSE output voltage of 36 V to 57 V across the input of the on board

dc-to-dc converter. This is accomplished on the TPS2371 by turning on an internal pass FET located across

the power return.

Programming the Inrush Current

During the initial turn-on of the pass FET, an inrush current is created from the charging of the capacitance at

the input of the dc-to-dc converter. According to the IEEE 802.3af specification, if the input capacitance is less

than 180-µF, the PSE limits the inrush current. If the input capacitance is greater than 180-µF, the IEEE 802.3af

specification requires the PD to limit the inrush current to less than 400 mA.

In order to satisfy the IEEE 802.3af requirements, the TPS2371 has been designed for a typical current limit

of 450 mA. This current limit setting satisfies the normal operation requirements as well as the inrush

requirements for a capacitive load of 180-µF or less. If a larger load capacitor is desired, the TPS2371 has been

designed with a programmable inrush current limit feature. This feature allows the designer the option of using

a capacitor larger than 180-µF. Note that the inrush current feature may also be used to lower voltage drops

in the cabling between the PSE and the PD during startup.

The programmable inrush current limit has a range of 50 mA to 449 mA. The limit is set by connecting an external

resistor from ILIM (pin 1) to VEE (pin 4) of the TPS2371. Equation (3) shows the calculation for the

programmable inrush current limit.

25 kW

( )

1 A

_{+ 450 mA *}ǒ Ǔ

INRUSH

LIM

(3)

where R

is a value between 63.5 kΩ and 25 MΩ.

LIM

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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

APPLICATION INFORMATION

Using EN_DC as a SoftStart or a PowerGood Function

The EN_DC pin is an output intended for use as a soft-start for a dc-to-dc converter. During the initial turn-on

of the pass FET, an internal 80-µA current sink is enabled on the EN_DC pin. This internal current sink is

removed only after the load capacitance has been charged to within 1.5-V of the supply voltage. By connecting

the EN_DC output to the soft start capacitor of a dc-to-dc converter, the internal current sink keeps the dc-to-dc

converter off during startup. Once the voltage across the converter has reached within 1.5 V of full voltage, the

dc-to-dc converter is allowed to soft start. A 5-V zener diode connected between EN_DC and RTN is required

for operation in this architecture.

For operation as a powergood output, the EN_DC requires an external pull-up. A 1-MΩ resistor is

recommended. The EN_DC output also requires a clamp to limit the output voltage to within recommended

operating levels. A 5-V zener diode connected between EN_DC and RTN (pin 5 of the TPS2371) is

recommended. This configuration allows the EN_DC pin to act as an open drain output with which many

designers are more familiar.

SURGE SUPPRESSION

As specified in the Absolute Maximum Ratings table, the absolute maximum input voltage of the TPS2371 is

68 V. The IEEE 802.3af Power-Over-Ethernet Standard specifies the voltage range of PSE output is between

44 V asd 57 V. This PSE output voltage range would be reduced by cable, connector and other IR drops

between the PSE and the TPS2371 in the PD. However, the use of extended cable lengths and transformers

in some applications may induce transients in excess of 68 V during a hot plug event. To manage these transient

events and keep them from significantly exceeding the application’s maximum voltage, a transorb such as the

SMAJ54A should be placed between the positive input supply, VDD (pin 8), and the negative input supply, VEE

(pin 4). This, combined with a 0.1-µF bypass capacitor in parallel with the transorb helps to protect the TPS2371

from damage caused by transients during hot plug events. The transorb or zener diode should be selected such

that it does not zener below the maximum required application voltage of 57 V, but before reaching the 68-V

absolute maximum rating. For layout purposes, the 0.1-µF capacitor should be placed as close as possible to

the device; the transorb or zener diode should be placed as close to the supply connector as possible. Based

on the nature of the PD application, these measures should be considered an implementation requirement.

USE OF BARREL RECTIFIERS

Many applications use barrel rectifiers after the RJ-45 connector in order to be polarity insensitive. Barrel

rectifiers in front of the TPS2371 cause the voltages at the device to be lower than the voltages at the RJ-45.

The TPS2371 allows for this and is IEEE802.3af compliant during the detection and classification phases. For

the detection phase, the device begins detection for voltages as low as 1.3 V across the supply pins. For the

optional classification phase, the device is guaranteed to start classification below 14 V across the supply pins.

Once classification has been engaged, it becomes latched-in and further voltage drops due to cable resistance

and class current does not cause it to switch out of classification. However, in cases where the PSE is operating

at minimum class voltage (15.5 V) and there is a 20-Ω, 100-m cable between the PSE and the PD, Class 3

devices may not classify correctly when using barrel rectifiers. Class 3 device designs should include schottky

diodes to handle all corner cases or switch to Class 0 devices when using barrel rectifiers.

Thermal Shutdown

In the event of a short circuit or overload condition, the TPS2371 begins to heat up until thermal shutdown is

reached. Once thermal shutdown is reached, the internal FET is switched off, removing the load from the supply.

After the device has cooled sufficiently, it retries by restarting the internal FET. If the overload or short is not

removed, the device cycles thermal shutdown seven times before latching the internal FET off. Once the internal

FET is latched off, power needs to be cycled to reset the latch.

www.ti.com

ꢀꢁ ꢂ ꢃꢄ ꢅꢆ

SLUS566A − JULY 2003 − REVISED NOVEMBER 2003

APPLICATION INFORMATION

Figure 1 shows an application where 40 V < V < 57 V. In this case, the brick supply is greater then 40 V and

goes through TPS2371.

PoE Powered Device Front End

V+

DET

LIM

DCDCIN

TPS2371

LIM

44 V

57 V

V−

VREG

DC/DC

Converter

Ethernet

Device

CLASS

V−

DC BRICK

SUPPLY

RJ−45

UDG−03094

Figure 1. For Applications 40 V < V < 57 V.

Figure 2 shows an application where V < 36 V. In this application, the brick supply is bypassing the hot swap

switch. Consequently, the dc-to-dc converter can operate from any voltage. However, for V

< 23 V, a Class

BRICK

0 resistor (R

= 4.42 kΩ) is recommended. This minimizes the power dissipation in TPS2371 if V

in the classification voltage range (15 V to 20 V). The 80-µA current sink on EN_DC pin is enabled only if

falls

CLASS

BRICK

VDD > 36 V.

PoE POWERED DEVICE FRONT END

V+

DET

LIM

DCDCIN

LIM

44 V

VREG

Ethernet

Device

TPS2371

DC/DC

Converter

V−

57 V

CLASS

V−

DC BRICK

SUPPLY

RJ−45

UDG−03095

Figure 2. For Applications V < 40 V.

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

TPS2371D

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

NRND

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

2371

TPS2371DG4

TPS2371DR

NRND

Green (RoHS

& no Sb/Br)

0 to 70

2371

SOIC

2500

150

Green (RoHS

& no Sb/Br)

0 to 70

TPS2371DRG4

TPS2371PW

SOIC

Green (RoHS

& no Sb/Br)

0 to 70

TSSOP

Green (RoHS

& no Sb/Br)

0 to 70

TPS2371PWG4

TPS2371PWR

TPS2371PWRG4

150

Green (RoHS

& no Sb/Br)

0 to 70

2000

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

0 to 70

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Jun-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TPS2371DR

SOIC

2500

2000

330.0

12.4

6.4

7.0

5.2

3.6

2.1

1.6

8.0

12.0

TPS2371PWR

TSSOP

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

11-Jun-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TPS2371DR

SOIC

2500

2000

340.5

367.0

338.1

367.0

20.6

35.0

TPS2371PWR

TSSOP

Pack Materials-Page 2

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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TPS2371DRG4 [TI]

相关型号：

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TPS2371PWG4

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TPS2371PWRG4

TPS2372

TPS2372-3RGWR

TPS2372-3RGWT

TPS2372-4RGWR

TPS2372-4RGWT

TPS2373

TPS2373-3RGWR

TPS2373-3RGWT