TPS2371PW [TI]
LEGACY IEEE802.3AF COMPATIBLE POWER INTERFACE SWITCH FOR POWER OVER ETHERNET POWERED DEVICES; LEGACY IEEE802.3AF兼容的电源接口开关,用于以太网供电的设备供电型号: | TPS2371PW |
厂家: | TEXAS INSTRUMENTS |
描述: | LEGACY IEEE802.3AF COMPATIBLE POWER INTERFACE SWITCH FOR POWER OVER ETHERNET POWERED DEVICES |
文件: | 总14页 (文件大小:281K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
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FEATURES
DESCRIPTION
D
Integrated Power Interface Switch for IEEE
802.3af Powered Devices (PDs)
Acting as an interface between the Power Source
Equipment (PSE) and the Powered Device (PD),
the TPS2371 performs all detection, class−
ification, inrush current limiting, and switch FET
control that is necessary for compatibility with
Legacy/IEEE 802.3af Standard. The TPS2371
incorporates precision UVLO thresholds and
hysteresis as well as a UVLO off-time delay to
enable Legacy IEEE802.3af PoE compatibilty. An
internal 0.3-Ω FET provides maximum power
delivery. As an additional feature, the TPS2371
interfaces with the enable/soft-start signal of a
dc-to-dc converter, eliminating the need to have
an accurate UVLO in the dc-to-dc converter.
D
D
D
D
D
D
D
D
D
Precision UVLO Thresholds
20-ms UVLO Off-Time Delay
Provides PD Detection Signature
Provides PD Classification Signature
(Class 0−4)
Programmable Inrush Current Limit
Internal 0.3-Ω Low-Side FET
Interfaces to DC/DC Soft-Start for DC/DC
Enable
Internal Thermal Protection – Disconnects
PD Load
At low input voltages (1.8 V to 10 V), the TPS2371
draws less than 12 µA, allowing accurate sensing
of the external 24.9-kΩ discovery resistor. At input
voltages between 15 V and 20 V, an external
resistor sets the level of current to be drawn during
classification mode. TPS2371 is compatible with
current as well as voltage measurement schemes
for classification. Above 20-V input, the
classification current is shut off, reducing internal
power dissipation.
8-Pin SOIC, 8-Pin TSSOP Packages
APPLICATIONS
D
D
D
D
VoIP Phones
Internet Appliances
Wireless LAN Access Points
Bluetooth Access Points
SIMPLIFIED APPLICATION DIAGRAM
V+
R
DET
8
C
C
DCDCIN
BYPASS
3
1
7
TPS2371
44 V
TO
57 V
R
LIM
C
DEL
DC/DC
Converter/
Controller
VREG
Ethernet
Appliance
C
LIM
6
5
R
CLASS
SMAJ54A
C
SS
2
4
5 V
V−
UDG−03092
Bluetooth is a trademark of the Bluetooth SIG, Inc.
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Copyright 1999 − 2003, Texas Instruments Incorporated
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ꢦ ꢪ ꢧ ꢦꢢ ꢣꢳ ꢞꢓ ꢒ ꢭꢭ ꢫꢒ ꢤ ꢒ ꢥ ꢪ ꢦ ꢪ ꢤ ꢧ ꢑ
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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
DESCRIPTION (continued)
The TPS2371 drives an internal low-side FET for control of the return side of the power path. The internal FET
is turned on when the input voltage reaches 36 V and above. When the input voltage decreases, the FET
remains on until the input voltage drops to below 30 V.
During initial turn-on of the switch (inrush mode), an external resistor is used to program the inrush current,
allowing a wide range of capacitor values to be used at the load. According to IEEE 802.3af specification, inrush
current of 400 mA is allowed only for 50 ms, limiting the load capacitor to approximately 180 µF. A programmable
inrush current limit removes this limitation, allowing a larger capacitor to be used with a lower inrush current limit.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted
(2)
TPS2371
UNIT
ILIM, DELAY
4
12
CLASS
Input voltage range, wrt V
EE
V
DET, RTN, EN_DC, VDD
68
Operating junction temperature range, T
−55 to 150
−65 to 150
300
°C
°C
°C
J
Storage temperature, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(2)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions”
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
Input voltage, V
48
57
70
V
I
Operating junction temperature, T
0
°C
J
(3)(4)
DISSIPATION RATINGS
T
< 25°C
T
= 25°C
T = 70°C
A
POWER RATING
A
A
THERMAL IMPEDANCE
JUNCTION-TO-AMBIENT
PACKAGE
POWER RATING
DERATING
FACTOR
8-Pin Plastic TSSOP (PW)
8-Pin Plastic SOIC (D)
258.5°C/W
176.0°C/W
464 mW
682 mW
3.9 mW/°C
5.7 mW/°C
290 mW
426 mW
(3)
(4)
Test board conditions:
1. 3” x 3”, 4 layers, thickness: 0.062”
2. 1.5 oz. copper traces located on the top of the PCB
3. 1.5 oz. copper ground plane on the bottom of the PCB
4. 0.5 oz. copper ground planes on the 2 internal layers
5. 12 thermal vias (see “Recommended Land Pattern” in applications section of this data sheet)
Maximum power dissipation may be limited by over current protection.
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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
ELECTRICAL CHARACTERISTICS
V
= 48 V; T = 0°C to 70°C; all voltages and currents are with respect to VEE; (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
Offset current
VDD = 1.8 V, DET = OPEN
1.8 V ≤ VDD < 10 V, DET = OPEN
3
12
I
I
Sleep current
5
73
DD
µA
R
R
= 24.9 kΩ, VDD = 1.8 V
= 24.9 kΩ, VDD = 9.5 V
70
380
76
DET
DET
Detection load current
DET
390
12.5
22.5
400
14.0
23.5
Turn on
10.0
21.5
Classification current threshold
VDD current class 0
V
Turn off
0.44 W ≤ P
15 V ≤ VDD ≤ 20 V,
≤ 12.95 W,
PoE
2.2
10.4
18.1
27.7
38.5
2.5
10.8
18.6
28.4
39.6
2.8
11.5
19.5
29.9
42.0
R
= 4.42 kΩ
= 953 Ω
= 549 Ω
= 357 Ω
CLASS
0.44 W ≤ P ≤ 3.84 W,
PoE
15 V ≤ VDD ≤ 20 V,
VDD current class 1
R
CLASS
3.84 W ≤ P
PoE
15 V ≤ VDD ≤ 20 V,
≤ 6.49 W,
VDD current class 2
mA
R
CLASS
6.49 W ≤ P
≤ 12.95 W,
PoE
15 V ≤ VDD ≤ 20 V,
VDD current class 3
R
CLASS
Reserved for future use,
VDD current class 4
15 V ≤ VDD ≤ 20 V,
30 V ≤ VDD ≤ 57 V,
Turn on
R
= 255 Ω
= 255 Ω
CLASS
CLASS
VDD quiescent current
R
500
35.0
30.5
4.5
800
36.1
31.5
µA
33.9
29.5
4.3
Input UVLO threshold
Turn off
V
UVLO hysteresis
UVLO off-time delay
EN_DC sink current
RTN threshold for EN_DC
C
= 180 nF
18
ms
µA
V
DELAY
40
1.2
80
200
1.8
1.5
DMOS R
DS(on)
I
= 200 mA
0.15
405
180
0.30
455
250
144
20
0.60
505
300
Ω
RTN
Full load current limit
V
< 1.5 V
RTN
mA
ILIM current limit programming
Thermal shutdown temperature
Thermal shutdown hysteresis
R
= 125 kΩ, V
> 1.5 V during startup
LIM
RTN
°C
D OR PW PACKAGE
(TOP VIEW)
ILIM
VDD
1
2
3
4
8
7
6
5
CLASS
DET
DELAY
EN_DC
RTN
VEE
ORDERING INFORMATION
(1)
T
PACKAGE
PART NUMBER
TPS2371PW
TPS2371D
A
Plastic TSSOP (PW)
Plastic SOIC (D)
0°C to 70°C
(1)
The PW and D packages are also available taped and reeled. Add an R suffix to the device type (i.e., TPS2371PWR).
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TERMINAL FUNCTIONS
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Sets classification level with a single resistor to VEE. A precision voltage of 10.0 V is applied to this pin during
CLASS
2
O
I
classification. R
CLASS
values listed in Table 1.
UVLO turn-off delay programming. Connect a capacitor between VCC and this pin to program the UVLO
turn-off delay.
(2)
DELAY
7
DET
3
6
O
O
Connect the 24.9kΩ detection resistor (R ) between this pin and VDD.
DET
EN_DC
(1)
Ties to dc-to-dc converter’s shutdown or soft-start pin. Sinks 80µA until the load capacitor is fully charged.
Sets startup current limit level with a resistor to VEE. If using C > 180 µF, I must be less than
DC2DCIN RUSH
ILIM
1
O
400 mA. Extra capacitance on ILIM pin can cause oscillations in the current waveform.
Return pin. Connect this pin to input return side of the dc-to-dc converter.
Connection to PD input port positive voltage.
RTN
VDD
VEE
5
8
4
O
I
I
Input side power return for the controller.
25 kW
RLIM
( )
1 A
+ 450 mA * ǒ Ǔ
NOTE 1: IINRUSH
NOTE 2: TDELAY
100 ms
+ ǒ Ǔ
CDELAY
mF
DETAILED PIN DESCRIPTIONS
ILIM (Pin 1)
Inrush current limiting pin. This pin is used to program the inrush current of the device. Due to the low UVLO
hysteresis of this device, a 1.0-µF capacitor from this pin to VEE is necessary to allow startup with 20 Ω in series
with V
as required by the IEEE standards. By placing a resistor to VEE from this pin, the inrush current into
DD
the load will be limited via the following equation:
25 kW
( )
1 A
+ 450 mA * ǒ Ǔ
I
INRUSH
R
LIM
(1)
CLASS (Pin 2)
Classification pin. The PD can be optionally classified by adding a resistor from this pin to ground. The resistor
specific to each class is given in Table 1: PoE Classification Resistance Values.
DET (Pin3)
Detection pin. This pin is used to set up the detection resistance during PD detection. By tying a resistor, R
from this pin to VDD, the user sets the detection resistance. It should be noted that the device itself looks like
,
DET
approximately 1 MΩ of resistance in parallel with R
.
DET
VEE (Pin 4)
Negative supply to the device.
RET (Pin 5)
Negative supply to the load. This pin is the drain side of a FET between the RET pin and the VEE pin, providing
hot swap capabilities to the load. When the FET is switched on, there is approximately 300mΩ between this
pin and VEE.
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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
DETAILED PIN DESCRIPTIONS (continued)
EN_DC (Pin 6)
Enable pin for the load. This pin is intended to be used with a dc-to-dc coverter with a soft start capacitor. When
power is not available to the dc-to-dc converter, this pin sinks 80-µA and hold off the softstart cap on the dc-to-dc
converter. Once the voltage across the load is within 1.5 V of its final value, the EN_DC pin stops drawing current
and become high impedance, allowing the dc-to-dc to soft start normally.
DELAY (Pin 7)
This pin controls the amount of time that the device ignores an undervoltage condition on VDD. That time is set
by the following equation:
100 ms
+ ǒ Ǔ
T
C
DELAY
DELAY
mF
(2)
VDD (Pin 8)
Positive supply to the device.
Table 1. PoE Classification Resistance Values
RESISTANCE
) VALUE (Ω)
POWERED DEVICES
(PDs) Power (W)
CLASSIFICATION
CURRENT (mA)
CLASS
(R
CLASS
4420
0
1
2
3
4
0.44 − 12.95
0.44 − 3.84
2.5
953
549
357
255
10.8
18.6
28.4
39.6
3.84 − 6.49
6.49 − 12.95
reserved for future use
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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
INTERNAL BLOCK DIAGRAM
+VE SUPPLY
TO DC/DC’s
EN/SS
VDD
R
DET
8
24.9 kΩ
DELAY
UVLO, Detection,
Classification Control
CLASS
7
C
SS
LDO
10 V
2
Precision Bandgap Reference
Precision Current Source
Internal Supplies
DET
3
C
BYBASS
VEE
EN_DC
5 V
15 V
80 µA
60 V
6
5
1.5 V
R
CLASS
5 V
RTN
ILIM
20 µA
2 kΩ
1
+
TO DC/DC’s
INPUT RETURN
0.1 Ω
4
R
LIM
VEE
C
LIM
−VE SUPPLY
UDG−03093
6
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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
STATE DIAGRAM
DETECTION
V
< 10 V
DD
I
= VDD/(R
Switch Resistance > 100 MΩ
) || 1 MΩ
DET
DD
CLASSIFICATION
10 V < V
DD
< 22 V
CLASS
I
≅ 10 V/(R
)
DD
Switch Resistance > 100 MΩ
INRUSH MODE
V
> 36 V (rising edge)
= 450 mA − (25 kΩ/R
Switch Resistance ≈ 100 Ω
V
> 1.5 V
RTN
DD
= I
I
) x (1 A)
RET INRUSH
LIM
LATCH OFF
V
DD
> 30 V
I
< 1 mA
DD
Switch Resistance ꢀ 100
MΩ
NORMAL OPERATION
V
> 30 V
) < 450 mA
DD
(I
= I
RET LOAD
NO
Switch Resistance ≈ 0.3 Ω
YES
TSD
OVERLOAD/FAULT
Count < 7?
V
RET
> 30 V
= 450 mA
DD
I
Switch Resistance ≈ 100 Ω
THERMAL SHUTDOWN
YES
NO
V > 30 V
DD
< 1 mA
T
J
< 145 _C?
I
DD
Switch Resistance > 100 MΩ
MACHINE STATE
Detection
Normal Operation
(I = 450 mA)
UVLO ON
(Rising Edge)
UVLO OFF
(Falling Edge)
(R
= 25 kΩ)
LOAD
Classification
DD
50
57
0
2
4
6
8
10
15
20
25
30.5
35
44
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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
APPLICATION INFORMATION
OVERVIEW
With the addition of power via media dependent interface (MDI) to the IEEE 802.3af Standard, all data terminal
equipment (DTE) now has the option to receive power over existing cabling that is used for data transmission.
The IEEE 802.3af Standard defines the requirements associated with providing and receiving power over the
existing cabling. The power sourcing equipment (PSE) provides the power on the cable and the powered device
(PD) receives the power. As part of the IEEE 802.3af Standard, the interface between the PSE and PD is defined
as it relates to the detection and classification protocol.
POWER SOURCING EQUIPMENT DETECTION OF A POWERED DEVICE
A powered device (PD) draws power or requests power by participating in a PD detection algorithm. This
algorithm requires the power sourcing equipment (PSE) to probe the link looking for a valid PD. The PSE probes
the link by sending out a voltage between 2.8 V and 10 V across the power lines. A valid PD detects this voltage
and places a resistance of between 23.75 kΩ and 26.25kΩ across the power lines. Naturally, the current varies
depending on the input voltage. Upon detecting this current, the PSE concludes that a valid PD is connected
at the end of the ethernet cable and is requesting power.
If the powered device (PD) is in a state in which it does not accept power, the PD is required to place a resistance
above or below the values listed for a valid PD. On the lower end, a range between 12 kΩ and 23.75 kΩ signifies
that the PD does not require power. On the higher end, the range is defined to be between 26.25 kΩ and 45
kΩ . Any resistance value less than 12 kΩ and greater than 45 kΩ, is interpreted by the PSE as a non-valid PD
detection signature.
The TPS2371 participates in the detection algorithm by activating an internal FET, which connects the DET pin
of the device to VEE. As a result, any resistance connected between VDD and the DET pin of the TPS2371 is,
in effect, across the power lines. This internal FET is active only when input power to the PD is between 2.8 V
and 10 V.
POWER SOURCING EQUIPMENT CLASSIFICATION OF A POWERED DEVICE
After the detection phase, the PSE can optionally initiate a classification of the PD. The classification of a PD
is used by the PSE to determine the maximum power required by the PD during normal operation. Five different
levels of classification are defined by the IEEE 802.3af Standard. These levels are shown in Table 2.
Table 2. Powered Device Classification Levels
POWER DEVICE
POWER
CLASSIFICATION
CURRENT
(mA)
CLASS
USAGE
(W)
MIN
0.44
0.44
3.84
6.49
MAX
12.95
3.84
MIN
0
MAX
4
0
1
2
3
4
Default
Optional
9
12
20
30
44
Optional
6.49
17
26
36
Optional
12.95
Not allowed
reserved for future use
8
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SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
APPLICATION INFORMATION
Classification of the PD is optionally performed by the PSE only after a valid PD has been detected. To determine
PD classification, the PSE increases the voltage across the power lines to between 15.5 V and 20.5 V. The
amount of current drawn by the PD determines the classification (see Table 2).
When the input voltage to the TPS2371 is between 14.0 V and 20.5 V, the TPS2371 uses an internal regulator
to generate a fixed voltage on the CLASS pin. A resistor connected between the CLASS pin and VEE draws
a fixed amount of current and thereby defines the classification level of the PD.
POWER SOURCING EQUIPMENT POWER TO THE POWERED DEVICE
Upon completion of the detection and optional classification phases, the PSE ramps its output voltage above
36 V . Once the UVLO threshold has been reached, the internal FET is turned on. At this point, the PD begins
to operate normally and it continues to operate normally as long as the input voltage remains above 30 V. For
most PDs, this input voltage is down-converted using an on board dc-to-dc converter to generate the required
voltages.
The TPS2371 is designed to apply the PSE output voltage of 36 V to 57 V across the input of the on board
dc-to-dc converter. This is accomplished on the TPS2371 by turning on an internal pass FET located across
the power return.
Programming the Inrush Current
During the initial turn-on of the pass FET, an inrush current is created from the charging of the capacitance at
the input of the dc-to-dc converter. According to the IEEE 802.3af specification, if the input capacitance is less
than 180-µF, the PSE limits the inrush current. If the input capacitance is greater than 180-µF, the IEEE 802.3af
specification requires the PD to limit the inrush current to less than 400 mA.
In order to satisfy the IEEE 802.3af requirements, the TPS2371 has been designed for a typical current limit
of 450 mA. This current limit setting satisfies the normal operation requirements as well as the inrush
requirements for a capacitive load of 180-µF or less. If a larger load capacitor is desired, the TPS2371 has been
designed with a programmable inrush current limit feature. This feature allows the designer the option of using
a capacitor larger than 180-µF. Note that the inrush current feature may also be used to lower voltage drops
in the cabling between the PSE and the PD during startup.
The programmable inrush current limit has a range of 50 mA to 449 mA. The limit is set by connecting an external
resistor from ILIM (pin 1) to VEE (pin 4) of the TPS2371. Equation (3) shows the calculation for the
programmable inrush current limit.
25 kW
( )
1 A
+ 450 mA * ǒ Ǔ
I
INRUSH
R
LIM
(3)
where R
is a value between 63.5 kΩ and 25 MΩ.
LIM
9
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ꢀ ꢁ ꢂ ꢃ ꢄꢅ ꢆ
SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
APPLICATION INFORMATION
Using EN_DC as a SoftStart or a PowerGood Function
The EN_DC pin is an output intended for use as a soft-start for a dc-to-dc converter. During the initial turn-on
of the pass FET, an internal 80-µA current sink is enabled on the EN_DC pin. This internal current sink is
removed only after the load capacitance has been charged to within 1.5-V of the supply voltage. By connecting
the EN_DC output to the soft start capacitor of a dc-to-dc converter, the internal current sink keeps the dc-to-dc
converter off during startup. Once the voltage across the converter has reached within 1.5 V of full voltage, the
dc-to-dc converter is allowed to soft start. A 5-V zener diode connected between EN_DC and RTN is required
for operation in this architecture.
For operation as a powergood output, the EN_DC requires an external pull-up. A 1-MΩ resistor is
recommended. The EN_DC output also requires a clamp to limit the output voltage to within recommended
operating levels. A 5-V zener diode connected between EN_DC and RTN (pin 5 of the TPS2371) is
recommended. This configuration allows the EN_DC pin to act as an open drain output with which many
designers are more familiar.
SURGE SUPPRESSION
As specified in the Absolute Maximum Ratings table, the absolute maximum input voltage of the TPS2371 is
68 V. The IEEE 802.3af Power-Over-Ethernet Standard specifies the voltage range of PSE output is between
44 V asd 57 V. This PSE output voltage range would be reduced by cable, connector and other IR drops
between the PSE and the TPS2371 in the PD. However, the use of extended cable lengths and transformers
in some applications may induce transients in excess of 68 V during a hot plug event. To manage these transient
events and keep them from significantly exceeding the application’s maximum voltage, a transorb such as the
SMAJ54A should be placed between the positive input supply, VDD (pin 8), and the negative input supply, VEE
(pin 4). This, combined with a 0.1-µF bypass capacitor in parallel with the transorb helps to protect the TPS2371
from damage caused by transients during hot plug events. The transorb or zener diode should be selected such
that it does not zener below the maximum required application voltage of 57 V, but before reaching the 68-V
absolute maximum rating. For layout purposes, the 0.1-µF capacitor should be placed as close as possible to
the device; the transorb or zener diode should be placed as close to the supply connector as possible. Based
on the nature of the PD application, these measures should be considered an implementation requirement.
USE OF BARREL RECTIFIERS
Many applications use barrel rectifiers after the RJ-45 connector in order to be polarity insensitive. Barrel
rectifiers in front of the TPS2371 cause the voltages at the device to be lower than the voltages at the RJ-45.
The TPS2371 allows for this and is IEEE802.3af compliant during the detection and classification phases. For
the detection phase, the device begins detection for voltages as low as 1.3 V across the supply pins. For the
optional classification phase, the device is guaranteed to start classification below 14 V across the supply pins.
Once classification has been engaged, it becomes latched-in and further voltage drops due to cable resistance
and class current does not cause it to switch out of classification. However, in cases where the PSE is operating
at minimum class voltage (15.5 V) and there is a 20-Ω, 100-m cable between the PSE and the PD, Class 3
devices may not classify correctly when using barrel rectifiers. Class 3 device designs should include schottky
diodes to handle all corner cases or switch to Class 0 devices when using barrel rectifiers.
Thermal Shutdown
In the event of a short circuit or overload condition, the TPS2371 begins to heat up until thermal shutdown is
reached. Once thermal shutdown is reached, the internal FET is switched off, removing the load from the supply.
After the device has cooled sufficiently, it retries by restarting the internal FET. If the overload or short is not
removed, the device cycles thermal shutdown seven times before latching the internal FET off. Once the internal
FET is latched off, power needs to be cycled to reset the latch.
10
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ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
SLUS566A − JULY 2003 − REVISED NOVEMBER 2003
APPLICATION INFORMATION
Figure 1 shows an application where 40 V < V < 57 V. In this case, the brick supply is greater then 40 V and
IN
goes through TPS2371.
PoE Powered Device Front End
3
V+
RX
TX
R
DET
8
C
6
1
C
LIM
SS
3
7
C
DCDCIN
TPS2371
R
LIM
44 V
TO
57 V
1
2
V−
VREG
DC/DC
Converter
Ethernet
Device
2
4
5
6
5
R
CLASS
S
P
A
R
E
V−
4
7
8
DC BRICK
SUPPLY
RJ−45
UDG−03094
Figure 1. For Applications 40 V < V < 57 V.
IN
Figure 2 shows an application where V < 36 V. In this application, the brick supply is bypassing the hot swap
IN
switch. Consequently, the dc-to-dc converter can operate from any voltage. However, for V
< 23 V, a Class
BRICK
0 resistor (R
= 4.42 kΩ) is recommended. This minimizes the power dissipation in TPS2371 if V
in the classification voltage range (15 V to 20 V). The 80-µA current sink on EN_DC pin is enabled only if
falls
CLASS
BRICK
VDD > 36 V.
PoE POWERED DEVICE FRONT END
3
V+
RX
TX
R
DET
6
1
8
C
C
LIM
DCDCIN
3
7
C
SS
R
LIM
44 V
TO
1
2
VREG
Ethernet
Device
TPS2371
DC/DC
Converter
V−
57 V
2
4
5
6
5
R
CLASS
S
P
A
R
E
V−
4
7
8
DC BRICK
SUPPLY
RJ−45
UDG−03095
Figure 2. For Applications V < 40 V.
IN
11
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MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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