TPIC5303D_技术文档

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ꢖ

SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

• Low r

. . . 0.4 Ω Typ

D PACKAGE

(TOP VIEW)

DS(on)

• High Voltage Output . . . 60 V

• Extended ESD Capability . . . 4000 V

• Pulsed Current . . . 5 A Per Channel

• Fast Commutation Speed

GATE1

DRAIN2

SOURCE2

GATE2

1

2

3

4

5

6

7

8

16

15

14

SOURCE1

13 DRAIN1

12 DRAIN1

11

10

9

description

SOURCE3

GATE3

DRAIN3

GND

The TPIC5303 is a monolithic gate-protected

power DMOS array that consists of three

independent electrically isolated N-channel

enhancement-mode DMOS transistors. Each

transistor features integrated high-current zener

diodes (Z

and Z

) to prevent gate damage in the event that an overstress condition occurs. These zener

CXa

CXb

diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF

capacitor in series with a 1.5-kΩ resistor.

The TPIC5303 is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized for

operation over the case temperature range of −40°C to 125°C.

schematic

DRAIN1

12, 13

GATE2

5

DRAIN2

1, 2

GATE3

9

DRAIN3

6, 7

Q1

Q2

Q3

D1

D2

D3

Z1

Z2

16

Z3

GATE1

Z

C2b

Z

C3b

C1b

Z

C1a

Z

C3a

C2a

14, 15

SOURCE1

8

GND

3, 4

SOURCE2

10, 11

SOURCE3

NOTE A: For correct operation, no terminal pin may be taken below GND.

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Copyright  1995, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

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SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

†

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Drain-to-source voltage, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V

DS

Source-to-GND voltage (Q1, Q2, and Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V

Drain-to-GND voltage (Q1, Q2, and Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V

Gate-to-source voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −9 V to 18 V

GS

Continuous drain current, each output, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A

C

Continuous source-to-drain diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A

C

Pulsed drain current, each output, I

, T = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 5 A

max

C

Continuous gate-to-source zener-diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

C

Pulsed gate-to-source zener-diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mA

C

Single-pulse avalanche energy, E , T = 25°C (see Figures 4, 15, and 16) . . . . . . . . . . . . . . . . . . . 10.2 mJ

AS

C

Continuous total power dissipation, T = 25°C (see Figure 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.08 W

C

Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C

J

Operating case temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C

C

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Pulse duration = 10 ms, duty cycle = 2%

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢖ

SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

electrical characteristics, T = 25°C (unless otherwise noted)

C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

Drain-to-source breakdown voltage

I

= 250 µA,

V

= 0

= V

60

V

(BR)DSX

D

GS

= 1 mA,

D

DS

GS,

Gate-to-source threshold voltage

1.5

1.8

2.2

V

GS(th)

See Figure 5

V

Gate-to-source breakdown voltage

Source-to-gate breakdown voltage

I

= 250 µA

18

9

V

(BR)GS

GS

(BR)SG

SG

Reverse drain-to-GND breakdown voltage (across

D1, D2, D3)

V

Drain-to-GND current = 250 µA

100

V

(BR)

I

= 1.4 A, = 10 V,

V

GS

D

V

Drain-to-source on-state voltage

0.56

0.9

5

0.64

1.1

DS(on)

See Notes 2 and 3

I

= 1.4 A,

= 0 (Z1, Z2, Z3),

S

V

F(SD)

V

F

Forward on-state voltage, source-to-drain

V

GS

See Notes 2 and 3 and Figure 12

I

= 1.4 A (D1, D2, D3),

D

Forward on-state voltage, GND-to-drain

Zero-gate-voltage drain current

See Notes 2 and 3

T

= 25°C

0.05

0.5

1

V

DS

V

GS

= 48 V,

= 0

C

I

µA

nA

DSS

= 125°C

10

C

Forward-gate current, drain short circuited to

source

V

= 15 V,

= 5 V,

V

= 0

20

10

200

100

GSSF

GSSR

GS

SG

DS

Reverse-gate current, drain short circuited to

source

V

DS

T

= 25°C

0.05

0.5

1

C

I

Leakage current, drain-to-GND

V = 48 V

DGND

µA

lkg

= 125°C

10

C

V

= 10 V,

GS

= 1.4 A,

T

= 25°C

0.4

0.62

1.19

0.46

0.66

C

I

D

r

Static drain-to-source on-state resistance

Forward transconductance

Ω

DS(on)

See Notes 2 and 3

and Figures 6 and 7

= 125°C

C

V

= 15 V,

I = 0.7 A,

D

DS

See Notes 2 and 3 and Figure 9

g

1

S

fs

C

Short-circuit input capacitance, common source

Short-circuit output capacitance, common source

107

71

137

89

iss

V

= 25 V,

V

= 0,

oss

DS

f = 1 MHz,

GS

See Figure 11

pF

Short-circuit reverse transfer capacitance, common

source

C

22

28

rss

NOTES: 2. Technique should limit T − T to 10°C maximum.

J

C

3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

source-to-drain and GND-to-drain diode characteristics, T = 25°C

C

PARAMETER

TEST CONDITIONS

MIN

TYP

92

MAX

UNIT

Z1, Z2, and Z3

D1, D2, and D3

Z1, Z2, and Z3

D1, D2, and D3

t

rr

Reverse-recovery time

ns

I

V

= 0.7 A,

= 0,

V

= 48 V,

S

DS

di/dt = 100 A/µs,

244

0.1

1.3

GS

See Figures 1 and 14

Q

Total diode charge

µC

RR

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢁꢑꢒ ꢋꢐ ꢍꢎ ꢓꢑ ꢔꢍꢉꢐ ꢐꢉꢕ

ꢖ

SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

resistive-load switching characteristics, T = 25°C

C

PARAMETER

TEST CONDITIONS

MIN

TYP

25

27

15

7

MAX

40

UNIT

t

Turn-on delay time

d(on)

d(off)

r2

Turn-off delay time

Rise time

40

V

t

= 25 V,

R

= 36 Ω,

t

r1

= 10 ns,

DD

= 10 ns,

L

ns

See Figure 2

25

f1

Fall time

14

f2

Q

Total gate charge

2.1

0.3

1.2

5

2.6

0.38

1.5

g

V

= 48 V,

I

D

= 0.7 A,

V

GS

= 10 V,

DS

See Figure 3

Threshold gate-to-source charge

Gate-to-drain charge

Internal drain inductance

Internal source inductance

Internal gate resistance

nC

gs(th)

gd

L

D

nH

5

S

R

0.25

Ω

g

thermal resistance

PARAMETER

TEST CONDITIONS

See Notes 4 and 7

See Notes 5 and 7

See Notes 6 and 7

MIN

TYP

115

64

MAX

UNIT

R

Junction-to-ambient thermal resistance

Junction-to-board thermal resistance

Junction-to-pin thermal resistance

θJA

θJB

θJP

°C/W

33

NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink.

2

5. Package mounted on a 24 inch , 4-layer FR4 printed-circuit board.

6. Package mounted in intimate contact with infinite heatsink.

7. All outputs with equal power

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

1

Reverse di/dt = 100 A/µs

0.5

0

− 0.5

†

25% of I

RM

− 1

− 1.5

− 2

Shaded Area = QRR

V

= 48 V

= 0

= 25°C

DS

GS

− 2.5

− 3

T

J

†

‡

I

Z1, Z2, and Z3

RM

t

rr(SD)

0

100 200 300 400 500 600 700 800 900 1000

Time − ns

†

‡

I

= maximum recovery current

RM

The above waveform is representative of D1, D2, and D3 in shape only.

Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

V

DD

= 25 V

t

r1

f1

10 V

R

L

V

DS

V

GS

0 V

Pulse Generator

V

GS

t

d(off)

t

d(on)

DUT

t

r2

t

f2

C

30 pF

R

50 Ω

L

gen

V

DD

(see Note A)

50 Ω

V

DS

V

DS(on)

VOLTAGE WAVEFORMS

TEST CIRCUIT

NOTE A: C includes probe and jig capacitance.

L

Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms

Current

Regulator

Q

Same Type

as DUT

g

12-V

Battery

0.2 µF

50 kΩ

10 V

0.3 µF

Q

gs(th)

gd

V

DD

V

DS

V

GS

DUT

I

G

= 100 µA

Gate Voltage

Time

0 V

I

Current-

I Current-

D

Sampling Resistor

G

VOLTAGE WAVEFORM

Sampling Resistor

TEST CIRCUIT

Figure 3. Gate-Charge Test Circuit and Waveform

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢁꢑ ꢒ ꢋꢐꢍ ꢎꢓ ꢑꢔ ꢍꢉ ꢐꢐ ꢉꢕ

ꢖ

SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

V

DD

= 25 V

t

av

t

w

476 µH

15 V

0 V

V

GS

V

DS

Pulse Generator

(see Note A)

I

D

I

AS

V

GS

(see Note B)

I

D

DUT

50 Ω

0 V

R

gen

V

= 60 V Min

50 Ω

(BR)DSX

V

DS

0 V

VOLTAGE AND CURRENT WAVEFORMS

TEST CIRCUIT

NOTES: A. The pulse generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, Z = 50 Ω.

r

f

O

B. Input pulse duration (t ) is increased until peak current I

= 5 A.

w

AS

I

V

t

av

AS

(BR)DSX

Energy test level is defined as E

+

+ 10.2 mJ, where

AS

2

t

av

= avalanche time.

Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms

TYPICAL CHARACTERISTICS

GATE-TO-SOURCE THRESHOLD VOLTAGE

STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE

vs

JUNCTION TEMPERATURE

0.8

JUNCTION TEMPERATURE

2.5

2

V

DS

= V

GS

I

D

= 1.4 A

0.6

0.4

0.2

0

I

= 1 mA

D

1.5

1

V

= 10 V

GS

I

D

= 100 µA

V

GS

= 15 V

0.5

0

T

20 40 60 80 100 120 140 160

0

20 40 60 80 100 120 140 160

−40 −20

− Junction Temperature − °C

T

− Junction Temperature − °C

J

Figure 5

Figure 6

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

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ꢖ

SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE

DRAIN CURRENT

vs

DRAIN CURRENT

DRAIN-TO-SOURCE VOLTAGE

1

5

4.5

4

0.9

V

GS

= 15 V

V = 5.6 V

GS

T

J

= 25°C

0.8

0.7

nV

= 0.4 V

GS

= 25°C

T

J

0.6

0.5

0.4

(unless otherwise

noted

3.5

V

GS

= 10 V

3

V

GS

= 10 V

2.5

0.3

0.2

V

GS

= 15 V

V

GS

= 4 V

2

1.5

1

V

= 2.8 V

GS

0.5

0

0.1

1

10

0

2

4

6

8

I

D

− Drain Current − A

V

DS

− Drain-to-Source Voltage − V

Figure 7

Figure 8

DRAIN CURRENT

vs

DISTRIBUTION OF

GATE-TO-SOURCE VOLTAGE

FORWARD TRANSCONDUCTANCE

5

75

70

65

60

55

50

Total Number of

Units = 2064

T

J

= −40°C

V

= 15 V

= 0.7 A

= 25°C

DS

T

J

= 25°C

4

3

2

1

0

I

D

T

J

= 75°C

J

T

J

= 125°C

45

40

35

30

25

20

15

10

T

J

= 150°C

5

0

1

2

3

4

5

6

7

8

V

GS

− Gate-to-Source Voltage − V

g

fs

− Forward Transconductance − S

Figure 9

Figure 10

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢅ

ꢅ ꢇꢃꢈꢉ ꢊꢊꢋꢌꢍꢂ ꢊꢎꢋ ꢁꢋꢊꢎ ꢋꢊꢀ ꢍꢏ ꢉꢀ ꢋꢇꢁꢐꢑ ꢀ ꢋꢃ ꢀꢋ ꢎ

ꢁꢑ ꢒ ꢋꢐꢍ ꢎꢓ ꢑꢔ ꢍꢉ ꢐꢐ ꢉꢕ

ꢖ

SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

SOURCE-TO-DRAIN DIODE CURRENT

CAPACITANCE

vs

DRAIN-TO-SOURCE VOLTAGE

vs

SOURCE-TO-DRAIN VOLTAGE

10

250

225

200

175

150

125

100

75

V

= 0

GS

V

= 0

GS

f = 1 MHz

T

J

= 25°C

@ 0 V = 160 pF

C

iss

@ 0 V = 216 pF

@ 0 V = 78 pF

oss

rss

1

C

iss

T

= 75°C

= 25°C

J

C

oss

T

J

T

= 125°C

= 150°C

J

50

25

0

T

= −40°C

J

C

rss

0.1

0

4

8

12 16 20 24 28 32 36 40

− Drain-to-Source Voltage − V

1

10

V

DS

V

SD

− Source-to-Drain Voltage − V

Figure 11

Figure 12

DRAIN-TO-SOURCE VOLTAGE AND

GATE-TO-SOURCE VOLTAGE

vs

REVERSE-RECOVERY TIME

vs

GATE CHARGE

REVERSE di/dt

280

60

12

10

8

I

T

= 0.7 A

= 25°C

D

J

V

= 48 V

= 0

= 0.7 A

DS

GS

260

See Figure 3

240

220

200

180

160

140

120

100

I

T

S

J

50

40

30

20

10

= 25°C

V

= 20 V

DD

See Figure 1

V

= 30 V

DD

D1, D2, and D3

6

4

V

DD

= 48 V

80

60

40

Z1, Z2, and Z3

2

V

= 20 V

2.5

DD

20

0

100

200

300

400

500

600

0

0.5

1

1.5

2

3

3.5

4

Reverse di/dt − A/µs

Q

− Gate Charge − nC

g

Figure 13

Figure 14

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢆꢅ

ꢅ ꢇꢃ ꢈꢉ ꢊ ꢊ ꢋꢌꢍ ꢂ ꢊꢎ ꢋꢁ ꢋ ꢊꢎꢋ ꢊ ꢀꢍ ꢏ ꢉꢀꢋ ꢇꢁ ꢐꢑ ꢀ ꢋꢃꢀ ꢋꢎ

ꢁꢑꢒ ꢋꢐ ꢍꢎ ꢓꢑ ꢔꢍꢉꢐ ꢐꢉꢕ

ꢖ

SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

THERMAL INFORMATION

MAXIMUM DRAIN CURRENT

vs

DRAIN-TO-SOURCE VOLTAGE

10

T

C

= 25°C

†

1 µs

†

10 ms

†

1 ms

1

†

500 µs

§

‡

R

θJP

θJA

DC Conditions

1

0.1

10

100

V

− Drain-to-Source Voltage − V

DS

Less than 2% duty cycle

†

‡

§

Device mounted on FR4 printed-circuit board with no heatsink.

Device mounted in intimate contact with infinite heatsink.

Figure 15

MAXIMUM PEAK AVALANCHE CURRENT

vs

TIME DURATION OF AVALANCHE

10

See Figure 4

T

C

= 25°C

T

C

= 125°C

1

0.01

0.1

1

10

t

− Time Duration of Avalanche − ms

av

Figure 16

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢅ

ꢅ ꢇꢃꢈꢉ ꢊꢊꢋꢌꢍꢂ ꢊꢎꢋ ꢁꢋꢊꢎ ꢋꢊꢀ ꢍꢏ ꢉꢀ ꢋꢇꢁꢐꢑ ꢀ ꢋꢃ ꢀꢋ ꢎ

ꢁꢑ ꢒ ꢋꢐꢍ ꢎꢓ ꢑꢔ ꢍꢉ ꢐꢐ ꢉꢕ

ꢖ

SLIS039A − SEPTEMBER 1994 − REVISED SEPTEMBER 1995

THERMAL INFORMATION

†

D PACKAGE

JUNCTION-TO-BOARD THERMAL RESISTANCE

vs

PULSE DURATION

100

DC Conditions

d = 0.5

d = 0.2

d = 0.1

10

d = 0.05

d = 0.02

d = 0.01

1

Single Pulse

t

c

t

w

I

D

0

0.1

0.0001

0.001

0.01

0.1

1

10

100

t

− Pulse Duration − s

w

†

2

Device mounted on 24 in , 4-layer FR4 printed-circuit board with no heatsink

NOTE A: Z (t) = r(t) R

θJB

t

= pulse duration

= cycle time

w

c

d = duty cycle = t /t

w c

Figure 17

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

^{POST OFFICE BOX 1443}• HOUSTON, TEXAS 77251−1443

PACKAGE OPTION ADDENDUM

www.ti.com

8-Apr-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

TPIC5303D

OBSOLETE

SOIC

D

16

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

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Addendum-Page 1

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型号：	TPIC5303D
厂家：	TEXAS INSTRUMENTS
描述：	3-CHANNEL INDEPENDENT GATE-PROTECTED POWER DMOS ARRAY 3通道独立门保护的功率DMOS阵列
文件：	总14页 (文件大小：264K)
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