TPIC5323L [TI]
3-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY; 3通道独立门保护逻辑电平功率DMOS阵列
| 型号： | TPIC5323L |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL POWER DMOS ARRAY |
| 文件： | 总13页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL
POWER DMOS ARRAY
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
D PACKAGE
(TOP VIEW)
Low r
. . . 0.6 Ω Typ
DS(on)
Voltage Output . . . 60 V
Input Protection Circuitry . . . 18 V
Pulsed Current . . . 3 A Per Channel
Extended ESD Capability . . . 4000 V
Direct Logic-Level Interface
GATE1
DRAIN2
DRAIN2
SOURCE2
SOURCE2
GATE2
1
2
3
4
5
6
7
8
16
15
14
SOURCE1
SOURCE1
13 DRAIN1
12 DRAIN1
11
description
SOURCE3
DRAIN3
DRAIN3
GND
10
9
SOURCE3
GATE3
The TPIC5323L is a monolithic gate-protected
logic-level power DMOS array that consists of
three electrically isolated independent N-channel
enhancement-mode DMOS transistors. Each transistor features integrated high-current zener diodes (Z
CXa
and Z
) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also
CXb
provideupto4000VofESDprotectionwhentestedusingthehuman-bodymodelofa100-pFcapacitorinseries
with a 1.5-kΩ resistor.
The TPIC5323L is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized
for operation over the case temperature of –40°C to 125°C.
schematic
DRAIN1
12, 13
GATE2
5
DRAIN2
1, 2
GATE3
9
DRAIN3
6, 7
Q1
Q2
Q3
D1
D2
D3
Z1
Z2
16
Z3
GATE1
Z
Z
Z
Z
Z
C1b
C2b
C3b
Z
C1a
C2a
C3a
14, 15
SOURCE1
8
GND
3, 4
SOURCE2
10, 11
SOURCE3
NOTE A: For correct operation, no terminal can be taken below GND.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-to-source voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
DS
Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Gate-to-source voltage range, V
Continuous drain current, each output, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Continuous source-to-drain diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
Pulsed drain current, each output, I
Continuous gate-to-source zener diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Pulsed gate-to-source zener diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mA
Single-pulse avalanche energy, E , T = 25°C (see Figures 4 and 16) . . . . . . . . . . . . . . . . . . . . . . . 22.5 mJ
Continuous total power dissipation, T = 25°C (see Figure 15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.09 W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –9 V to 18 V
GS
C
C
, T = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 3 A
max
C
C
C
AS
C
C
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
Operating case temperature range, T
J
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
C
Storage temperature range, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
electrical characteristics, T = 25°C (unless otherwise noted)
C
PARAMETER
TEST CONDITIONS
MIN
60
TYP
MAX
UNIT
V
V
Drain-to-source breakdown voltage
I
I
= 250 µA,
V
V
= 0
= V
V
(BR)DSX
D
GS
= 1 mA,
,
D
DS
GS
Gate-to-source threshold voltage
1.5
1.8
2.2
V
GS(th)
See Figure 5
V
V
Gate-to-source breakdown voltage
Source-to-gate breakdown voltage
I
I
= 250 µA
= 250 µA
18
9
V
V
(BR)GS
GS
(BR)SG
SG
Reverse drain-to-GND breakdown voltage (across
D1, D2, D3)
V
Drain-to-GND current = 250 µA
= 1 A, = 5 V,
100
V
V
(BR)
I
D
V
GS
V
Drain-to-source on-state voltage
0.6
0.9
4
0.7
1.1
DS(on)
See Notes 2 and 3
I
= 1 A,
= 0 (Z1, Z2, Z3),
S
V
V
Forward on-state voltage, source-to-drain
V
V
F(SD)
GS
See Notes 2 and 3 and Figure 12
I
= 1 A (D1, D2, D3),
D
Forward on-state voltage, GND-to-drain
Zero-gate-voltage drain current
V
F
See Notes 2 and 3
T
T
= 25°C
0.05
0.5
20
1
10
V
DS
V
GS
= 48 V,
= 0
C
I
µA
DSS
= 125°C
C
I
I
Forward-gate current, drain short circuited to source
Reverse-gate current, drain short circuited to source
V
= 15 V,
= 5 V,
V
V
= 0
= 0
200
100
1
nA
nA
GSSF
GS
SG
DS
V
10
GSSR
DS
T
= 25°C
0.05
0.5
C
C
I
Leakage current, drain-to-GND
V = 48 V
DGND
µΑ
lkg
T
= 125°C
10
V
= 5 V,
GS
= 1 A,
T
T
= 25°C
0.6
0.85
1.06
0.65
0.9
C
I
r
Static drain-to-source on-state resistance
Forward transconductance
Ω
DS(on)
See Notes 2 and 3
and Figures 6 and 7
= 125°C
C
V
= 15 V,
I = 500 mA,
D
DS
See Notes 2 and 3 and Figure 9
g
0.89
S
fs
C
C
Short-circuit input capacitance, common source
Short-circuit output capacitance, common source
107
71
137
89
iss
V
= 25 V,
V
= 0,
oss
DS
f = 1 MHz,
GS
See Figure 11
pF
Short-circuit reverse transfer capacitance,
common source
C
22
28
rss
NOTES: 2. Technique should limit T – T to 10°C maximum.
J
C
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, T = 25°C
C
PARAMETER
TEST CONDITIONS
MIN
TYP
75
MAX
UNIT
Z1, Z2, and Z3
D1, D2, and D3
Z1, Z2, and Z3
D1, D2, and D3
t
rr
Reverse-recovery time
ns
I
V
= 500 mA,
= 0,
V
= 48 V,
S
DS
di/dt = 100 A/µs,
190
0.08
0.85
GS
See Figures 1 and 14
Q
Total diode charge
µC
RR
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
resistive-load switching characteristics, T = 25°C
C
PARAMETER
TEST CONDITIONS
MIN
TYP
34
50
20
15
2
MAX
50
UNIT
t
t
t
t
Turn-on delay time
Turn-off delay time
Rise time
d(on)
d(off)
r2
70
V
t
= 25 V,
DD
= 10 ns,
R
= 50 Ω,
t
r1
= 10 ns,
L
ns
See Figure 2
30
f1
Fall time
25
f2
Q
Q
Q
Total gate charge
2.45
0.95
1.48
g
V
= 48 V,
DS
See Figure 3
I
D
= 500 mA,
V
= 5 V,
GS
Threshold gate-to-source charge
Gate-to-drain charge
Internal drain inductance
Internal source inductance
Internal gate resistance
0.3
1.2
5
nC
gs(th)
gd
L
D
nH
L
S
5
R
0.25
Ω
g
thermal resistance
PARAMETER
TEST CONDITIONS
See Notes 4 and 7
See Notes 5 and 7
See Notes 6 and 7
MIN
TYP
115
64
MAX
UNIT
R
R
R
Junction-to-ambient thermal resistance
Junction-to-board thermal resistance
Junction-to-pin thermal resistance
θJA
θJB
θJP
°C/W
33
NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink.
2
5. Package mounted on a 24 in , 4-layer FR4 printed-circuit board.
6. Package mounted in intimate contact with infinite heatsink.
7. All outputs with equal power
PARAMETER MEASUREMENT INFORMATION
1
Reverse di/dt = 100 A/µs
0.5
0
†
– 0.5
25% of I
RM
– 1
– 1.5
– 2
Shaded Area = Q
RR
†
I
RM
T
= 25°C
J
– 2.5
– 3
‡
t
Z1, Z2, and Z3
rr(SD)
0
50 100 150 200 250 300 350 400 450 500
Time – ns
†
‡
I
= maximum recovery current
RM
The above waveform is representative of D1, D2, and D3 in shape only.
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
V
DD
= 25 V
t
r1
t
f1
5 V
R
L
V
DS
V
GS
0 V
Pulse Generator
V
GS
t
d(off)
t
d(on)
DUT
t
r2
t
f2
C
= 30 pF
R
50 Ω
L
gen
V
DD
(see Note A)
50 Ω
V
DS
V
DS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: C includes probe and jig capacitance.
L
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
Current
Regulator
Q
Same Type
as DUT
g
12-V
Battery
0.2 µF
50 kΩ
5 V
0.3 µF
Q
Q
gd
V
DD
gs(th)
V
DS
V
GS
DUT
I
G
= 100 µA
Gate Voltage
Time
0 V
I
Current-
I Current-
D
Sampling Resistor
G
VOLTAGE WAVEFORM
Sampling Resistor
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Waveform
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
V
DD
= 25 V
†
t
av
t
w
2.92 mH
5 V
0 V
V
GS
V
DS
Pulse Generator
(see Note A)
I
D
I
AS
V
GS
(see Note B)
I
D
DUT
50 Ω
0 V
R
gen
V
= 60 V Min
(BR)DSX
50 Ω
V
DS
0 V
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
Non-JEDEC symbol for avalanche time
†
NOTES: A. The pulse generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, Z = 50 Ω.
r
f
O
B. Input pulse duration (t ) is increased until peak current I
AS
= 3 A.
w
I
V
t
av
AS
(BR)DSX
2
Energy test level is defined as E
22.5 mJ, where t
avalanche time.
av
AS
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
1.2
2.5
2
V
DS
= V
I = 1 A
D
GS
1
V
GS
= 4.5 V
V
I
= 1 mA
D
0.8
1.5
1
= 5 V
GS
I
D
= 100 µA
0.6
0.4
0.2
0
0.5
0
–40 –20
0
20 40 60 80 100 120 140 160
–40 –20
0
T
20 40 60 80 100 120 140 160
T
– Junction Temperature – °C
J
– Junction Temperature – °C
J
Figure 5
Figure 6
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN-TO-SOURCE VOLTAGE
DRAIN CURRENT
3
2.5
2
10
V
J
= 0.4 V
GS
= 25°C
T
J
= 25°C
T
V
= 4 V
GS
1
1.5
1
V
= 4.5 V
= 5 V
GS
V
GS
V
GS
= 2.8 V
0.5
0
0.1
0.1
0
2
4
6
8
10
1
10
I
D
– Drain Current – A
V
DS
– Drain-to-Source Voltage – V
Figure 7
Figure 8
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
3
50
45
40
35
30
25
20
15
Total Number of
Units = 2064
T
J
= –40°C
V
I
T
= 15 V
= 0.5 A
= 25°C
DS
D
T
= 25°C
J
T
J
= 125°C
J
J
T
J
= 75°C
2
1
0
T
= 150°C
10
5
0
0
1
2
3
4
5
6
7
8
V
GS
– Gate-to-Source Voltage – V
g
fs
– Forward Transconductance – S
Figure 9
Figure 10
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
SOURCE-TO-DRAIN DIODE CURRENT
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
vs
SOURCE-TO-DRAIN VOLTAGE
5
4
250
225
200
175
150
125
100
75
V
= 0
V
= 0
GS
GS
f = 1 MHz
= 25°C
3
2
T
J
C
C
C
= 160 pF
= 216 pF
= 78 pF
iss(0)
oss(0)
rss(0)
1
C
iss
T
= 75°C
= 25°C
J
C
oss
T
J
T
= 125°C
= 150°C
J
50
25
0
T
J
= –40°C
T
J
C
rss
0.1
4
8
12 16 20 24 28 32 36 40
– Drain-to-Source Voltage – V
1
10
V
DS
V
SD
– Source-to-Drain Voltage – V
Figure 11
Figure 12
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
GATE CHARGE
220
200
180
160
140
120
100
80
60
12
10
8
I
T
= 500 mA
= 25°C
D
J
V
V
= 48 V
= 0
= 500 mA
DS
GS
See Figure 3
I
T
S
J
50
40
30
20
10
= 25°C
V
= 20 V
DD
See Figure 1
V
DD
= 30 V
D1, D2, and D3
6
4
V
DD
= 48 V
60
40
2
Q1, Q2, and Q3
V
= 20 V
2.5
20
0
DD
0
0
100
200
300
400
500
600
0.5
1
1.5
2
3
3.5
4
Reverse di/dt – A/µs
Q
– Gate Charge – nC
g
Figure 13
Figure 14
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
MAXIMUM PEAK AVALANCHE CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
TIME DURATION OF AVALANCHE
10
5
4
T
C
= 25°C
See Figure 4
†
1 µs
3
2
†
10 ms
T
C
= 25°C
†
1 ms
1
T
C
= 125°C
†
500 µs
‡
§
θ
θ
JP
JA
DC Conditions
1
1
0.01
0.1
10
100
0.1
1
10
V
DS
– Drain-to-Source Voltage – V
t
av
– Time Duration of Avalanche – ms
†
‡
§
Less than 2% duty cycle
Device mounted in intimate contact with infinite heatsink.
Device mounted on FR4 printed-circuit board with no heatsink.
Figure 16
Figure 15
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995
THERMAL INFORMATION
†
D PACKAGE
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
100
10
1
DC Conditions
d = 0.5
d = 0.2
d = 0.1
d = 0.05
d = 0.02
d = 0.01
Single Pulse
t
c
t
w
I
D
0
0.1
0.0001
0.001
0.01
0.1
1
10
100
t
w
– Pulse Duration – s
†
2
Device mounted on 24 in , 4-layer FR4 printed-circuit board with no heatsink.
NOTE A: Z (t) = r(t) R
θB θJB
t
t
d
pulse duration
cycle time
w
c
duty cycle
t
t
w
c
Figure 17
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPIC5323LD
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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相关型号：
TPIC5401DWR
1.7A, 60V, 0.35ohm, 4 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-013AC, MS-013, 20 PIN
TI
TPIC5404DWR
1.7A, 60V, 0.35ohm, 4 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-013AC, PLASTIC, SOIC-20
TI
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