TPIC5401DWR [TI]
1.7A, 60V, 0.35ohm, 4 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-013AC, MS-013, 20 PIN;
| 型号： | TPIC5401DWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1.7A, 60V, 0.35ohm, 4 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-013AC, MS-013, 20 PIN 开关 脉冲 光电二极管 晶体管 |
| 文件： | 总15页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
Low r
. . . 0.3 Ω Typ
Pulsed Current . . . 10 A Per Channel
Fast Commutation Speed
DS(on)
High Voltage Output . . . 60 V
Extended ESD Capability . . . 4000 V
description
The TPIC5401 is a monolithic gate-protected power DMOS array that consists of four N-channel
enhancement-mode DMOS transistors, two of which are configured with a common source. Each transistor
features integrated high-current zener diodes (Z
overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using
and Z
) to prevent gate damage in the event that an
CXa
CXb
the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor.
The TPIC5401 is offered in a 16-pin thermally enhanced dual-in-line (NE) package and a 20-pin wide-body
surface-mount (DW) package and is characterized for operation over the case temperature range of –40°C to
125°C.
NE PACKAGE
(TOP VIEW)
DW PACKAGE
(TOP VIEW)
SOURCE1
DRAIN1
GATE1
DRAIN2
SOURCE2/GND
GATE2
GND
SOURCE4/GND
GATE4
SOURCE2/GND
GATE2
NC
1
2
3
4
5
6
7
8
16
15
14
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
13 GND
12 GND
GND
NC
NC
GND
DRAIN4
SOURCE3
DRAIN3
GATE3
DRAIN2
11
10
9
GATE3
GATE4
15 SOURCE1
DRAIN3
SOURCE3
14
13
12
11
SOURCE4/GND
DRAIN4
DRAIN1
GATE1
NC
NC
NC
NC
NC – No internal connection
schematic
DRAIN1
DRAIN3
Q1
Q3
Z1
D1
D2
Z3
GATE3
GATE1
Z
Z
Z
C3b
C1b
Z
SOURCE1
DRAIN2
C1a
C3a
SOURCE3
DRAIN4
Q2
Q4
GATE4
GATE2
Z
Z2
Z4
Z
Z
C4b
C2b
Z
C2a
C4a
GND, SOURCE2, SOURCE4
NOTE: For correct operation, no terminal pin may be taken below GND.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-to-source voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
DS
Source-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage (Q1, Q3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage (Q2, Q4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
Gate-to-source voltage range, V
Continuous drain current, each output, T = 25°C: DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7 A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –9 V to 18 V
GS
C
NE package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
Continuous source-to-drain diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 A
C
Pulsed drain current, each output, I
, T = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . 10 A
max
C
Continuous gate-to-source zener-diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
C
Pulsed gate-to-source zener-diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 mA
C
Single-pulse avalanche energy, E , T = 25°C (see Figures 4, 15, and 16) . . . . . . . . . . . . . . . . . . . . . . 21 mJ
AS
C
Continuous total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
J
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
C
Storage temperature range, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
DISSIPATION RATING TABLE
≤ 25°C DERATING FACTOR
T
C
T = 125°C
C
POWER RATING
PACKAGE
POWER RATING
ABOVE T = 25°C
C
DW
NE
1389 mW
2075 mW
11.1 mW/°C
16.6 mW/°C
279 mW
415 mW
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
electrical characteristics, T = 25°C (unless otherwise noted)
C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
Drain-to-source breakdown voltage
I
I
= 250 µA,
V
V
= 0
= V
60
V
(BR)DSX
D
GS
= 1 mA,
D
DS
GS,
Gate-to-source threshold voltage
1.5
1.85
2.2
V
GS(th)
See Figure 5
V
V
Gate-to-source breakdown voltage
Source-to-gate breakdown voltage
I
I
= 250 µA
= 250 µA
18
9
V
V
(BR)GS
GS
(BR)SG
SG
Reverse drain-to-GND breakdown voltage
(across D1, D2)
V
Drain-to-GND current = 250 µA
= 2 A, = 10 V,
100
V
V
(BR)
I
D
V
GS
V
Drain-to-source on-state voltage
0.6
1
0.7
1.2
DS(on)
See Notes 2 and 3
I
= 2 A,
= 0 (Z1, Z2, Z3, Z4),
S
V
V
Forward on-state voltage, source-to-drain
V
V
F(SD)
GS
See Notes 2 and 3 and Figure 12
I
= 2 A (D1, D2),
D
Forward on-state voltage, GND-to-drain
Zero-gate-voltage drain current
7.5
V
F
See Notes 2 and 3
T
T
= 25°C
0.05
0.5
20
1
10
V
DS
V
GS
= 48 V,
= 0
C
I
µA
DSS
= 125°C
C
I
I
Forward-gate current, drain short circuited to source
Reverse-gate current, drain short circuited to source
V
= 15 V,
= 5 V,
V
V
= 0
= 0
200
100
1
nA
nA
GSSF
GS
SG
DS
V
10
GSSR
DS
T
= 25°C
0.05
0.5
C
C
I
Leakage current, drain-to-GND
V = 48 V
DGND
µA
lkg
T
= 125°C
10
V
= 10 V,
GS
= 2 A,
T
T
= 25°C
0.3
0.47
1.9
0.35
0.5
C
I
r
Static drain-to-source on-state resistance
Forward transconductance
Ω
DS(on)
See Notes 2 and 3
and Figures 6 and 7
= 125°C
C
V
= 15 V,
I = 1 A,
D
DS
See Notes 2 and 3 and Figure 9
g
1.6
S
fs
C
C
Short-circuit input capacitance, common source
Short-circuit output capacitance, common source
220
120
275
150
iss
V
= 25 V,
V
= 0,
oss
DS
f = 1 MHz,
GS
See Figure 11
pF
Short-circuit reverse-transfer capacitance,
common source
C
100
125
rss
NOTES: 2. Technique should limit T – T to 10°C maximum.
J
C
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, T = 25°C
C
PARAMETER
TEST CONDITIONS
MIN
TYP
120
280
260
0.12
0.9
MAX
UNIT
Z1 and Z3
Z2 and Z4
D1 and D2
Z1 and Z3
Z2 and Z4
D1 and D2
t
rr
Reverse-recovery time
ns
I
V
= 1 A,
= 0,
V
= 48 V,
S
DS
di/dt = 100 A/µs,
GS
See Figures 1 and 14
Q
Total diode charge
µC
RR
2.2
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
resistive-load switching characteristics, T = 25°C
C
PARAMETER
Turn-on delay time
TEST CONDITIONS
MIN
TYP
32
MAX
65
80
30
50
8
UNIT
t
t
t
t
d(on)
Turn-off delay time
Rise time
40
d(off)
V
t
= 25 V,
= 10 ns, See Figure 2
R
= 25 Ω,
t
en
= 10 ns,
DD
dis
L
ns
15
r
f
Fall time
25
Q
Q
Q
Total gate charge
6.6
0.8
2.6
5
g
V
DS
= 48 V,
See Figure 3
I
D
= 1 A,
V
= 10 V,
GS
Threshold gate-to-source charge
Gate-to-drain charge
Internal drain inductance
Internal source inductance
Internal gate resistance
1
nC
gs(th)
gd
3.2
L
d
nH
L
5
s
R
0.25
Ω
g
thermal resistances
PARAMETER
TEST CONDITIONS
MIN
TYP
90
MAX
UNIT
DW
NE
R
R
R
Junction-to-ambient thermal resistance (see Note 4)
Junction-to-board thermal resistance
θJA
θJB
θJP
60
DW
DW
NE
All outputs with equal power
53
°C/W
30
Junction-to-pin thermal resistance
25
NOTE 4: Package mounted on an FR4 printed-circuit board with no heatsink.
PARAMETER MEASUREMENT INFORMATION
2
V
V
= 48 V
= 0
DS
GS
T
J
= 25°C
1
0
Reverse di/dt = 100 A/µs
‡
Z1 and Z3
†
RM
25% of I
– 1
– 2
– 3
– 4
Shaded Area = Q
RR
†
I
RM
t
rr(SD)
0
200
400
600
Time – ns
800
1000
1200
†
‡
I
= maximum recovery current
RM
The above waveform is representative of Z2, Z4, D1, and D2 in shape only.
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
V
DD
= 25 V
t
en
t
dis
10 V
R
L
V
DS
V
GS
0 V
Pulse Generator
V
GS
t
d(off)
t
d(on)
DUT
t
r
t
f
C
30 pF
R
50 Ω
L
gen
V
V
DD
(see Note A)
50 Ω
V
DS
DS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: C includes probe and jig capacitance.
L
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
Current
Regulator
Q
g
Same Type
as DUT
12-V
Battery
0.2 µF
50 kΩ
10 V
0.3 µF
Q
Q
gd
gs(th)
V
DD
V
GS
V
DS
Gate Voltage
Time
DUT
I
G
= 100 µA
0 V
WAVEFORM
I
Current-
I Current-
D
Sampling Resistor
G
Sampling Resistor
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Waveform
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
PARAMETER MEASUREMENT INFORMATION
V
DD
= 25 V
t
av
t
w
354 µH
15 V
0 V
V
GS
V
DS
Pulse Generator
(see Note A)
I
D
I
(see Note B)
V
GS
AS
I
D
DUT
50 Ω
0 V
R
gen
V
= 60 V Min
50 Ω
(BR)DSX
V
DS
0 V
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, Z = 50 Ω.
r
f
O
B. Input pulse duration (t ) is increased until peak current I
AS
= 10 A.
w
I
V
t
av
AS
(BR)DSX
2
Energy test level is defined as E
21 mJ.
AS
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE THRESHOLD VOLTAGE
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.5
2
0.5
V
DS
= V
GS
I
D
= 2 A
V
= 10 V
GS
0.4
0.3
0.2
0.1
0
I
= 1 mA
D
1.5
1
V
= 15 V
GS
I
= 100 µA
D
0.5
0
– 40 – 20
0
20 40 60 80 100 120 140 160
– 40 – 20
0
20 40 60 80 100 120 140 160
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 5
Figure 6
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN-TO-SOURCE VOLTAGE
DRAIN CURRENT
1
0.9
0.8
0.7
5
4
3
2
1
0
V
= 0.2 V
GS
T
J
= 25°C
V
= 10 V
GS
T
= 25°C
J
(unless otherwise
noted)
V
= 15 V
GS
0.6
0.5
V
GS
= 4 V
0.4
0.3
V
= 10 V
GS
V
GS
= 15 V
0.2
V
GS
= 3 V
0.1
0.01
0
2
4
6
8
10 12 14 16 18 20
0.10
1
10
V
DS
– Drain-to-Source Voltage – V
I
D
– Drain Current – A
Figure 7
Figure 8
DRAIN CURRENT
vs
DISTRIBUTION OF
GATE-TO-SOURCE VOLTAGE
FORWARD TRANSCONDUCTANCE
10
9
8
7
6
5
4
3
2
1
0
30
25
20
15
T
J
= 25°C
Total Number of Units = 1040
= 15 V
T
= 75°C
V
J
DS
= 1 A
I
T
D
J
= 25°C
T
= 125°C
J
10
5
T
= 150°C
J
T
J
= –40°C
0
0
1
2
3
4
5
6
7
8
9
10
V
GS
– Gate-to-Source Voltage – V
g
fs
– Forward Transconductance – S
Figure 9
Figure 10
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
TYPICAL CHARACTERISTICS
CAPACITANCE
vs
SOURCE-TO-DRAIN DIODE CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
SOURCE-TO-DRAIN VOLTAGE
500
10
6
f = 1 MHz
V
GS
= 0
450
400
350
300
250
200
150
100
50
V
T
= 0
= 25°C
GS
J
4
2
1
C
C
iss
0.6
0.4
T
T
= 125°C
= 150°C
J
T
= –40°C
= 25°C
J
oss
J
T
J
C
rss
0.2
0.1
T
J
= 75°C
0
0
10
20
30
40
0.1
10
1
V
DS
– Drain-to-Source Voltage – V
V
SD
– Source-to-Drain Voltage – V
Figure 11
Figure 12
DRAIN-TO-SOURCE VOLTAGE
AND GATE-TO-SOURCE VOLTAGE
vs
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
GATE CHARGE
400
350
300
250
12
10
60
50
V
V
= 48 V
= 0
= 1 A
DS
GS
I
T
= 1 A
= 25°C
D
J
I
T
S
J
See Figure 3
= 25°C
V
= 20 V
DD
See Figure 1
V
= 30 V
8
6
4
DD
40
30
20
10
0
Z2 and Z4
200
150
Z1 and Z3
100
50
V
DD
= 48 V
2
0
V
= 20 V
4
DD
0
0
100
200
300
400
500
600
0
1
2
3
5
6
7
Reverse di/dt – A/µs
Q
– Gate Charge – nC
g
Figure 13
Figure 14
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
MAXIMUM PEAK-AVALANCHE CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
TIME DURATION OF AVALANCHE
100
10
1
30
10
T
C
= 25°C
See Figure 4
†
1 µs
†
10 ms
†
1 ms
500 µs
T
C
= 25°C
†
T
C
= 125°C
DW Pkg
NE Pkg
10
DC Conditions
1
1
0.1
0.1
100
0.01
0.1
1
10
100
V
DS
– Drain-to-Source Voltage – V
t
av
– Time Duration of Avalanche – ms
†
Less than 2% duty cycle
Figure 15
Figure 16
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
THERMAL INFORMATION
†
NE PACKAGE
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
10
DC Conditions
1
d = 0.5
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
Single Pulse
0.001
t
c
t
w
I
D
0
0.0001
0.0001
0.001
0.01
0.1
– Pulse Duration – s
1
10
t
w
†
Device mounted on FR4 printed-circuit board with no heatsink.
NOTE A: Z (t) = r(t) R
θJA θJA
t
= pulse duration
w
t = cycle time
c
d = duty cycle = t /t
w c
Figure 17
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY
SLIS024A – DECEMBER 1993 – REVISED MARCH 1994
THERMAL INFORMATION
†
DW PACKAGE
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
100
DC Conditions
d = 0.5
d = 0.2
d = 0.1
10
d = 0.05
d = 0.02
1
d = 0.01
t
c
Single Pulse
t
w
I
D
0
0.1
0.0001
0.001
0.01
0.1
– Pulse Duration – s
1
10
t
w
†
2
Device mounted on 24 in , 4-layer FR4 printed-circuit board with no heatsink.
NOTE B: Z (t) = r(t) R
θJB θJB
= pulse duration
t
w
t = cycle time
c
d = duty cycle = t /t
w c
Figure 18
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SOIC
PDIP
Drawing
TPIC5401DW
TPIC5401NE
OBSOLETE
OBSOLETE
DW
20
16
TBD
TBD
Call TI
Call TI
Call TI
Call TI
NE
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDI003 – OCTOBER 1994
NE (R-PDIP-T**)
PLASTIC DUAL-IN-LINE PACKAGE
20 PIN SHOWN
0.070 (1,78) MAX
11
20
PINS **
16
20
DIM
0.914 (23,22)
MIN
A
C
0.780 (19,80) 0.975 (24,77)
0.930 (23,62)
MAX
MIN
B
C
1.000 (25,40)
MAX
1
10
MIN
0.240 (6,10)
0.260 (6,61)
0.280 (7,11)
MAX 0.260 (6,60)
0.020 (0,51) MIN
0.200 (5,08) MAX
A
Seating Plane
0.155 (3,94)
0.125 (3,17)
0.100 (2,54)
0.021 (0,533)
0.015 (0,381)
0.010 (0,25)
M
0.310 (7,87)
B
0.020 (0,51) MIN
0.290 (7,37)
0.200 (5,08) MAX
Seating Plane
0.155 (3,94)
0.125 (3,17)
0°–15°
0.100 (2,54)
0.021 (0,533)
0.015 (0,381)
0.010 (0,25)
M
0.010 (0,25) NOM
4040054/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001 (16 pin only)
1
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相关型号：
TPIC5404DWR
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