TPIC5322LDR [TI]
1A, 60V, 0.525ohm, 3 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-012AC, PLASTIC, SOIC-16;
| 型号： | TPIC5322LDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1A, 60V, 0.525ohm, 3 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-012AC, PLASTIC, SOIC-16 |
| 文件： | 总12页 (文件大小：228K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆꢇ
ꢅ ꢈꢃꢉ ꢊꢋꢋ ꢌꢇ ꢂꢋ ꢍꢌꢁꢌ ꢋꢍꢌꢋ ꢀ ꢇ ꢎꢏ ꢂ ꢃꢈꢇ ꢌꢐꢌ ꢇ ꢁꢎ ꢑ ꢌꢒ ꢍꢓ ꢎ ꢔ ꢊ ꢒꢒ ꢊꢕ
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
D PACKAGE
(TOP VIEW)
D
D
D
D
D
Low r
. . . 0.45 Ω Typ
DS(on)
High-Voltage Outputs . . . 60 V
Pulsed Current . . . 3 A Per Channel
Fast Commutation Speed
DRAIN1
DRAIN1
GATE1
GND
1
2
3
4
5
6
7
8
16
15
14
SOURCE1
SOURCE1
SOURCE2
SOURCE2
SOURCE3
SOURCE3
GATE3
Direct Logic-Level Interface
13 DRAIN2
12 DRAIN2
11
10
9
description
GATE2
DRAIN3
DRAIN3
The TPIC5322L is a monolithic logic-level power
DMOS array that consists of three electrically
isolated independent N-channel enhancement-
mode DMOS transistors.
The TPIC5322L is offered in a standard 16-pin
small-outline surface-mount (D) package and is
characterized for operation over the case
temperature range of −40°C to 125°C.
schematic
DRAIN1
15, 16
GATE2
11
DRAIN2
12, 13
GATE3
8
DRAIN3
9, 10
Q1
Q2
Q3
D1
D2
D3
Z1
Z2
14
Z3
GATE1
2, 3
SOURCE1
1
GND
4, 5
SOURCE2
6, 7
SOURCE3
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-to-source voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
DS
Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Gate-to-source voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
GS
Continuous drain current, each output, all outputs on, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
C
Continuous source-to-drain diode current, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 A
C
Pulsed drain current, each output, I
, T = 25°C (see Note 1 and Figure 15) . . . . . . . . . . . . . . . . . . . . . 3 A
max
C
Single-pulse avalanche energy, E , T = 25°C (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40.5 mJ
AS
C
Continuous total power dissipation at (or below) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.09 W
C
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 150°C
J
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 125°C
C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms and duty cycle = 2%.
ꢁꢒ ꢎ ꢍꢖ ꢃ ꢀꢂ ꢎ ꢋ ꢍ ꢊꢀꢊ ꢗꢘ ꢙ ꢚꢛ ꢜ ꢝꢞ ꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞ ꢗꢚꢘ ꢦꢝ ꢞꢢ ꢧ
ꢁꢛ ꢚ ꢦꢡꢠ ꢞ ꢟ ꢠ ꢚꢘ ꢙꢚ ꢛ ꢜ ꢞ ꢚ ꢟ ꢣꢢ ꢠ ꢗꢙ ꢗꢠꢝ ꢞꢗ ꢚꢘꢟ ꢣꢢ ꢛ ꢞꢨ ꢢ ꢞꢢ ꢛ ꢜꢟ ꢚꢙ ꢀꢢꢩ ꢝꢟ ꢂꢘꢟ ꢞꢛ ꢡꢜ ꢢꢘꢞ ꢟ
ꢟ ꢞ ꢝ ꢘꢦ ꢝ ꢛꢦ ꢪ ꢝ ꢛꢛ ꢝ ꢘ ꢞꢫꢧ ꢁꢛ ꢚ ꢦꢡꢠ ꢞꢗꢚꢘ ꢣꢛ ꢚꢠ ꢢꢟ ꢟꢗ ꢘꢬ ꢦꢚꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢫ ꢗꢘꢠ ꢥꢡꢦ ꢢ
ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ
Copyright 1994, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢆ ꢇ
ꢅꢈ ꢃꢉꢊ ꢋ ꢋ ꢌꢇ ꢂ ꢋ ꢍ ꢌꢁ ꢌꢋ ꢍꢌ ꢋꢀ ꢇꢎ ꢏ ꢂꢃ ꢈꢇꢌ ꢐꢌ ꢇ ꢁꢎ ꢑ ꢌꢒ ꢍꢓ ꢎ ꢔ ꢊꢒꢒ ꢊꢕ
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
electrical characteristics, T = 25°C (unless otherwise noted)
C
PARAMETER
TEST CONDITIONS
MIN
60
TYP
MAX
UNIT
V
V
Drain-to-source breakdown voltage
I
I
= 250 µA,
V
V
= 0
= V
V
(BR)DSX
D
GS
= 1 mA,
See Figure 5
,
D
DS
GS
Gate-to-source threshold voltage
1.5
1.85
2.2
V
V
V
GS(th)
Reverse drain-to-GND breakdown voltage (across
D1, D2, and D3)
V
V
Drain-to-GND current = 250 µA
100
(BR)
I
D
= 1 A,
See Notes 2 and 3
V
V
= 5 V,
GS
Drain-to-source on-state voltage
0.45 0.525
DS(on)
I
S
= 1 A,
= 0,
GS
V
V
Forward on-state voltage, source-to-drain
Forward on-state voltage, GND-to-drain
0.85
1
V
V
F(SD)
See Notes 2 and 3 and Figure 12
I
D
= 1 A
3.7
0.05
0.5
F
T
T
= 25°C
1
V
V
= 48 V,
= 0
C
DS
GS
I
I
I
Zero-gate-voltage drain current
µA
nA
nA
DSS
= 125°C
10
C
Forward gate current, drain short circuited to
source
V
= 16 V,
V
V
= 0
= 0
10
10
100
100
GSSF
GSSR
GS
DS
Reverse gate current, drain short circuited to
source
V
= 16 V,
SG
DS
T
T
= 25°C
0.05
0.5
1
C
I
Leakage current, drain-to-GND
V
= 48 V
DGND
µA
lkg
= 125°C
10
C
V
= 5 V,
GS
= 1 A,
T
T
= 25°C
0.45 0.525
C
I
D
r
Static drain-to-source on-state resistance
Forward transconductance
Ω
DS(on)
See Notes 2 and 3
and Figures 6 and 7
= 125°C
0.7
0.78
C
V
= 10 V,
I = 0.5 A,
D
DS
See Notes 2 and 3 and Figure 9
g
1
1.24
S
fs
C
C
Short-circuit input capacitance, common source
Short-circuit output capacitance, common source
135
80
170
100
iss
V
= 25 V,
V
= 0,
oss
DS
f = 1 MHz,
GS
See Figure 11
pF
Short-circuit reverse-transfer capacitance,
common source
C
30
40
rss
NOTES: 2. Technique should limit T − T to 10°C maximum.
J
C
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain and GND-to-drain diode characteristics, T = 25°C
C
PARAMETER
TEST CONDITIONS
MIN
TYP
35
MAX
UNIT
Z1, Z2, Z3
D1, D2, D3
Z1, Z2,Z3
D1, D2, D2
t
rr
Reverse-recovery time
ns
I
V
= 0.5 A,
= 0,
V
= 48 V,
S
DS
di/dt = 100 A/µs,
110
0.035
0.35
GS
See Figures 1 and 14
Q
Total diode charge
µC
RR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆꢇ
ꢊ
ꢅ
ꢈ
ꢃ
ꢉ
ꢊ
ꢋ
ꢋ
ꢌ
ꢇ
ꢂ
ꢋ
ꢍ
ꢌ
ꢁ
ꢌ
ꢋ
ꢍ
ꢌ
ꢋ
ꢀ
ꢇ
ꢎ
ꢏ
ꢂ
ꢃ
ꢈ
ꢇ
ꢌ
ꢐ
ꢌ
ꢇ
ꢁ
ꢎ
ꢑ
ꢌ
ꢒ
ꢍ
ꢓ
ꢎ
ꢔ
ꢒ
ꢒ
ꢊ
ꢕ
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
resistive-load switching characteristics, T = 25°C
C
PARAMETER
TEST CONDITIONS
MIN
TYP
21
MAX
42
UNIT
t
t
t
t
Turn-on delay time
d(on)
Turn-off delay time
Rise time
20
5
40
10
d(off)
V
t
= 25 V,
R
= 50 Ω,
t
= 10 ns,
DD
= 10 ns,
L
en
ns
See Figure 2
dis
r
f
Fall time
13
3.1
0.4
1.3
5
26
Q
Q
Q
Total gate charge
3.8
0.5
1.6
g
V
= 48 V,
I
D
= 0.5 A,
V
= 5 V,
DS
See Figure 3
GS
Threshold gate-to-source charge
Gate-to-drain charge
Internal drain inductance
Internal source inductance
Internal gate resistance
nC
gs(th)
gd
L
D
nH
L
5
S
R
0.25
Ω
g
thermal resistance
PARAMETER
TEST CONDITIONS
MIN
TYP
115
32
MAX
UNIT
°C/W
°C/W
Junction-to-ambient thermal resistance
(see Note 4)
R
R
θJA
θJP
All outputs with equal power
Junction-to-pin thermal resistance
NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink
PARAMETER MEASUREMENT INFORMATION
1
Reverse di/dt = 100 A/µs
0.5
0
†
− 0.5
− 1
25% of I
RM
Shaded Area = Q
RR
− 1.5
− 2
†
I
RM
V
V
T
DS = 48 V
GS = 0
− 2.5
− 3
= 25°C
t
J
rr(SD)
Z1, Z2, and Z3
0
25
50
75 100 125 150 175 200 225 250
t − Time − ns
†
I
= maximum recovery current
RM
NOTE A: The above waveform is representative of D1, D2, and D3 in shape only.
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢆ ꢇ
ꢅꢈ ꢃꢉꢊ ꢋ ꢋ ꢌꢇ ꢂ ꢋ ꢍ ꢌꢁ ꢌꢋ ꢍꢌ ꢋꢀ ꢇꢎ ꢏ ꢂꢃ ꢈꢇꢌ ꢐꢌ ꢇ ꢁꢎ ꢑ ꢌꢒ ꢍꢓ ꢎ ꢔ ꢊꢒꢒ ꢊꢕ
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
V
DD
= 25 V
t
dis
t
en
R
L
V
DS
5 V
V
GS
Pulse Generator
V
GS
0
DUT
t
d(off)
t
d(on)
C
= 30 pF
R
50 Ω
L
t
r
gen
t
f
(see Note A)
V
V
DD
50 Ω
V
DS
DS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: C includes probe and jig capacitance.
L
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
Current
Regulator
Q
g
Same Type
as DUT
12-V
Battery
0.2 µF
50 kΩ
5 V
V
0.3 µF
Q
Q
gs(th)
gd
V
DD
V
DS
GS
DUT
Gate Voltage
Time
I
G
= 1 µA
0
I
Current-
I Current-
D
Sampling Resistor
G
VOLTAGE WAVEFORM
Sampling Resistor
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Voltage Waveform
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆꢇ
ꢅ ꢈꢃꢉ ꢊꢋꢋ ꢌꢇ ꢂꢋ ꢍꢌꢁꢌ ꢋꢍꢌꢋ ꢀ ꢇ ꢎꢏ ꢂ ꢃꢈꢇ ꢌꢐꢌ ꢇ ꢁꢎ ꢑ ꢌꢒ ꢍꢓ ꢎ ꢔ ꢊ ꢒꢒ ꢊꢕ
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
V
DD
= 25 V
t
av
t
w
5.25 mH
5 V
V
GS
V
DS
Pulse Generator
(see Note A)
0
I
D
I
AS
V
GS
(see Note B)
I
D
DUT
50 Ω
0
R
gen
V
= 60 V Min
(BR)DSX
50 Ω
V
DS
0
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, Z = 50 Ω.
r
f
O
B. Input pulse duration (t ) is increased until peak current I
= 3 A.
w
AS
I
V
t
av
AS
(BR)DSX
Energy test level is defined as E
+
+ 40.5 mJ.
AS
2
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE THRESHOLD VOLTAGE
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.5
2
1
V
DS
= V
GS
I = 1 A
D
0.8
0.6
0.4
I
= 1 mA
D
V
GS
= 4.5 V
1.5
1
I
D
= 100 µA
V
GS
= 5 V
0.5
0
0.2
0
0
20 40 60 80 100 120 140 160
0
20 40 60 80 100 120 140 160
−40 −20
−40 −20
T
J
− Junction Temperature − °C
T
J
− Junction Temperature − °C
Figure 5
Figure 6
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢆ ꢇ
ꢅꢈ ꢃꢉꢊ ꢋ ꢋ ꢌꢇ ꢂ ꢋ ꢍ ꢌꢁ ꢌꢋ ꢍꢌ ꢋꢀ ꢇꢎ ꢏ ꢂꢃ ꢈꢇꢌ ꢐꢌ ꢇ ꢁꢎ ꢑ ꢌꢒ ꢍꢓ ꢎ ꢔ ꢊꢒꢒ ꢊꢕ
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANC
vs
DRAIN CURRENT
3
2.5
2
1
V
GS
= 5 V
T
J
= 25°C
V
= 4 V
GS
0.9
0.8
nV
= 0.2 V
GS
= 25°C
T
J
0.7
0.6
1.5
1
V
GS
= 4.5 V
V
GS
= 3 V
0.5
0.5
0
V
GS
= 5 V
0.4
0
1
2
3
4
5
6
7
8
9
10
0.01
0.1
1
10
V
DS
− Drain-to-Source Voltage − V
I
D
− Drain Current − A
Figure 7
Figure 8
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
3
40
35
30
T
= 25°C
J
Total Number of Units = 819
V
I
T
= 10 V
= 0.5 A
= 25°C
DS
D
T
= 125°C
T = 75°C
J
J
2.5
J
2
1.5
1
25
20
15
10
T
J
= 150°C
0.5
0
5
0
T
J
= −40°C
0
1
2
3
4
5
V
GS
− Gate-to-Source Voltage − V
g
fs
− Forward Transconductance − S
Figure 9
Figure 10
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆꢇ
ꢅ ꢈꢃꢉ ꢊꢋꢋ ꢌꢇ ꢂꢋ ꢍꢌꢁꢌ ꢋꢍꢌꢋ ꢀ ꢇ ꢎꢏ ꢂ ꢃꢈꢇ ꢌꢐꢌ ꢇ ꢁꢎ ꢑ ꢌꢒ ꢍꢓ ꢎ ꢔ ꢊ ꢒꢒ ꢊꢕ
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
TYPICAL CHARACTERISTICS
CAPACITANCE
vs
SOURCE-TO-DRAIN DIODE CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
SOURCE-TO-DRAIN VOLTAGE
10
250
225
200
175
150
125
100
75
f = 1 MHz
= 0
V
GS
= 0
V
GS
= 25°C
T
J
1
C
iss
T
= 125°C
J
T
= −40°C
= 25°C
J
T
J
= 150°C
C
oss
T
J
0.1
T
J
= 75°C
50
25
0
C
rss
0.01
0
4
8
12 16 20 24 28 32 36 40
− Drain-to-Source Voltage − V
0.1
1
10
V
DS
V
SD
− Source-to-Drain Voltage − V
Figure 11
Figure 12
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
GATE CHARGE
150
125
100
75
80
16
14
12
V
V
= 48 V
= 0
= 0.5 A
DS
GS
I
T
= 0.5 A
= 25°C
D
J
70
60
I
T
S
J
See Figure 3
= 25°C
See Figure 1
50
40
30
20
10
0
10
8
D1, D2, and D3
Z1, Z2, and Z3
V
= 20 V
DD
V
DD
= 30 V
6
50
4
25
0
V
DD
= 48 V
2
V
= 20 V
2.5
DD
0
0
100
200
300
400
500
600
0
0.5
1
1.5
2
3
Reverse di/dt − A/µs
Q
− Gate Charge − nC
g
Figure 13
Figure 14
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁ ꢂꢃ ꢄ ꢅ ꢆꢆ ꢇ
ꢅꢈ ꢃꢉꢊ ꢋ ꢋ ꢌꢇ ꢂ ꢋ ꢍ ꢌꢁ ꢌꢋ ꢍꢌ ꢋꢀ ꢇꢎ ꢏ ꢂꢃ ꢈꢇꢌ ꢐꢌ ꢇ ꢁꢎ ꢑ ꢌꢒ ꢍꢓ ꢎ ꢔ ꢊꢒꢒ ꢊꢕ
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
MAXIMUM PEAK-AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
10
5
4
T
C
= 25°C
See Figure 4
†
1 µs
3
2
†
10 ms
T
C
= 25°C
1
†
1 ms
T
C
= 125°C
†
500 µs
DC Conditions
1
0.1
0.1
1
0.01
10
100
0.1
1
10
100
V
− Drain-to-Source Voltage − V
DS
Less than 2% duty cycle
t
− Time Duration of Avalanche − ms
av
†
Figure 15
Figure 16
8
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ ꢆꢇ
ꢅ ꢈꢃꢉ ꢊꢋꢋ ꢌꢇ ꢂꢋ ꢍꢌꢁꢌ ꢋꢍꢌꢋ ꢀ ꢇ ꢎꢏ ꢂ ꢃꢈꢇ ꢌꢐꢌ ꢇ ꢁꢎ ꢑ ꢌꢒ ꢍꢓ ꢎ ꢔ ꢊ ꢒꢒ ꢊꢕ
SLIS034A − JUNE 1994 − REVISED NOVEMBER 1994
THERMAL INFORMATION
†
D PACKAGE
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
10
DC Conditions
d = 0.5
1
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
0.001
Single Pulse
t
c
t
w
I
D
0
0.0001
0.0001
0.001
0.01
0.1
− Pulse Duration − s
1
10
t
w
†
Device mounted on FR4 printed-circuit board with no heat sink
NOTES: (t) = r(t) R
Z
θA
θJA
t
w
= pulse duration
= cycle time
t
c
d = duty cycle = t /t
w c
Figure 17
9
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PACKAGE OPTION ADDENDUM
www.ti.com
8-Apr-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TPIC5322LD
OBSOLETE
SOIC
D
16
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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相关型号：
TPIC5401DWR
1.7A, 60V, 0.35ohm, 4 CHANNEL, N-CHANNEL, Si, POWER, MOSFET, MS-013AC, MS-013, 20 PIN
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