TPIC5302 [TI]
3-CHANNEL INDEPENDENT POWER DMOS ARRAY; 3通道独立功率DMOS阵列
| 型号： | TPIC5302 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-CHANNEL INDEPENDENT POWER DMOS ARRAY |
| 文件： | 总11页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPIC5302
3-CHANNEL INDEPENDENT POWER DMOS ARRAY
SLIS029B – APRIL 1994 – REVISED SEPTEMBER 1995
•
•
•
•
Low r
. . . 0.3 Ω Typ
DS(on)
D PACKAGE
(TOP VIEW)
High-Voltage Outputs . . . 60 V
Pulsed Current . . . 7 A Per Channel
Fast Commutation Speed
DRAIN1
DRAIN1
GATE1
DRAIN2
DRAIN2
GATE2
GND
SOURCE1
SOURCE1
SOURCE2
SOURCE2
SOURCE3
SOURCE3
GATE3
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
description
The TPIC5302 is a monolithic power DMOS array
that consists of three electrically isolated
independent N-channel enhancement-mode
DMOS transistors. The TPIC5302 is offered in a
standard 16-pin small-outline surface-mount (D)
package.
DRAIN3
DRAIN3
The TPIC5302 is characterized for operation over
the case temperature range of –40°C to 125°C.
schematic
DRAIN1
15, 16
GATE2
11
DRAIN2
12, 13
GATE3
8
DRAIN3
9, 10
Q1
Q2
Q3
D1
D2
D3
Z1
Z2
14
Z3
GATE1
2, 3
SOURCE1
1
GND
4, 5
SOURCE2
6, 7
SOURCE3
†
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-to-source voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 V
DS
Source-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Drain-to-GND voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 V
Gate-to-source voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 V
GS
Continuous drain current, each output, all outputs on, T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A
Continuous source-to-drain diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 A
C
Pulsed drain current, each output, T = 25°C (see Note 1 and Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 A
C
Single-pulse avalanche energy, E , T = 25°C (see Figure 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 mJ
AS
C
Continuous total power dissipation at (or below) T = 25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1087 mW
C
Operating virtual junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C
J
Operating case temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms and duty cycle = 2%
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5302
3-CHANNEL INDEPENDENT POWER DMOS ARRAY
SLIS029B – APRIL 1994 – REVISED SEPTEMBER 1995
electrical characteristics, T = 25°C (unless otherwise noted)
C
PARAMETER
TEST CONDITIONS
MIN
60
TYP
MAX
UNIT
V
V
V
Drain-to-source breakdown voltage
Gate-to-source threshold voltage
I
I
= 250 µA,
V
V
= 0
= V
(BR)DSX
D
GS
= 1 mA,
1.5
1.85
2.2
V
GS(th)
D
DS
GS
Reverse drain-to-GND breakdown voltage (across
D1, D2, and D3)
V
Drain-to-GND current = 250 µA
100
V
V
(BR)
I
= 1.4 A,
V
GS
= 10 V,
D
V
Drain-to-source on-state voltage
0.42
0.9
0.49
1.1
DS(on)
See Notes 2 and 3
I
V
= 1.4 A,
= 0 (Z1, Z2, Z3),
S
V
V
Forward on-state voltage, source-to-drain
V
F(SD)
GS
See Notes 2 and 3
Forward on-state voltage, GND-to-drain
Zero-gate-voltage drain current
I
D
= 1.4 A
4.8
0.05
0.5
V
F
T
T
= 25°C
1
10
V
V
= 48 V,
= 0
C
DS
GS
I
µA
DSS
= 125°C
C
I
I
Forward gate current, drain short circuited to source
Reverse gate current, drain short circuited to source
V
= 16 V,
= 16 V,
V
V
= 0
= 0
10
100
100
1
nA
nA
GSSF
GS
SG
DS
V
10
GSSR
DS
T
= 25°C
0.05
0.5
C
C
I
Leakage current, drain-to-GND
V
R
= 48 V
µA
lkg
T
= 125°C
10
V
= 10 V,
= 1.4 A,
GS
T
= 25°C
0.3
0.41
1.41
0.35
0.5
C
C
I
D
r
Static drain-to-source on-state resistance
Forward transconductance
Ω
DS(on)
See Notes 2 and 3
and Figures 6 and 7
T
= 125°C
V
= 10 V,
I = 0.7 A,
D
DS
See Notes 2 and 3
g
1.15
S
fs
C
C
Short-circuit input capacitance, common source
Short-circuit output capacitance, common source
135
80
170
100
iss
V
= 25 V,
V
GS
= 0,
oss
DS
f = 1 MHz
pF
Short-circuit reverse-transfer capacitance,
common source
C
30
40
rss
NOTES: 2. Technique should limit T – T to 10°C maximum and pulse duration ≤5 ms.
J
C
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain diode characteristics, T = 25°C
C
PARAMETER
TEST CONDITIONS
= 0.5 A, = 0, = 48 V,
MIN
TYP
35
MAX
UNIT
ns
t
Reverse-recovery time
Total diode charge
I
S
V
GS
V
rr(SD)
DS
See Figure 1
di/dt = 100 A/µs,
Q
0.04
µC
RR
GND-to-drain diode characteristics, T = 25°C (see schematic, D1, D2, and D3)
C
PARAMETER
Reverse-recovery time
Total diode charge
TEST CONDITIONS
MIN
TYP
130
0.4
MAX
UNIT
ns
t
I
F
= 0.5 A,
V
DS
= 48 V,
rr
di/dt = 100 A/µs,
See Figure 1
Q
µC
RR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5302
3-CHANNEL INDEPENDENT POWER DMOS ARRAY
SLIS029B – APRIL 1994 – REVISED SEPTEMBER 1995
resistive-load switching characteristics, T = 25°C
C
PARAMETER
Turn-on delay time
TEST CONDITIONS
MIN
TYP
23
25
5
MAX
46
UNIT
t
t
t
t
d(on)
d(off)
r2
Turn-off delay time
Rise time
50
V
t
= 25 V,
= 10 ns,
R
= 50 Ω,
t
r1
= 10 ns,
DD
f1
L
ns
See Figure 2
10
Fall time
17
8
34
f2
Q
Q
Q
Total gate charge
9.8
0.63
1.85
g
V
= 48 V,
I
D
= 0.5 A,
V
= 10 V,
DS
See Figure 3
GS
Threshold gate-to-source charge
Gate-to-drain charge
Internal drain inductance
Internal source inductance
Internal gate resistance
0.5
1.5
5
nC
gs(th)
gd
L
L
D
nH
5
S
R
0.25
Ω
g
thermal resistance
PARAMETER
TEST CONDITIONS
All outputs with equal power, See Note 4
MIN
TYP
115
32
MAX
UNIT
R
R
Junction-to-ambient thermal resistance
Junction-to-pin thermal resistance
θJA
θJP
°C/W
NOTE 4: Package mounted on an FR4 printed-circuit board with no heat sink
PARAMETER MEASUREMENT INFORMATION
1
T
J
= 25°C
0.5
Reverse di/dt = 100 A/µs
0
– 0.5
– 1
†
25% of I
RM
– 1.5
– 2
†
I
RM
– 2.5
– 3
t
rr(SD)
0
25
50
75 100 125 150 175 200 225 250
Time – ns
†
I
= maximum recovery current
RM
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5302
3-CHANNEL INDEPENDENT POWER DMOS ARRAY
SLIS029B – APRIL 1994 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
V
DD
= 25 V
t
f1
t
r1
R
L
V
DS
10 V
V
GS
Pulse Generator
V
GS
0 V
DUT
t
d(off)
t
d(on)
C
= 30 pF
R
50 Ω
L
t
r2
gen
t
f2
(see Note A)
V
DD
50 Ω
V
DS
V
DS(on)
VOLTAGE WAVEFORMS
TEST CIRCUIT
NOTE A: C includes probe and jig capacitance.
L
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
V
DS
Current
Regulator
Q
g
Same Type
as DUT
12-V
Battery
0.2 µF
50 kΩ
10 V
0.3 µF
Q
Q
gs(th)
gd
V
DD
V
GS
DUT
Gate Voltage
Time
I
G
= 1 µA
0 V
I
Current-
I Current-
D
Sampling Resistor
Q
= Q – Q
g gd
G
gs
Sampling Resistor
VOLTAGE WAVEFORM
TEST CIRCUIT
Figure 3. Gate-Charge Test Circuit and Voltage Waveform
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5302
3-CHANNEL INDEPENDENT POWER DMOS ARRAY
SLIS029B – APRIL 1994 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
25 V
t
av
t
w
250 µH
15 V
0 V
V
GS
V
DS
Pulse Generator
(see Note A)
I
D
I
AS
V
GS
(see Note B)
I
D
DUT
50 Ω
0 V
R
gen
V
= 60 V Min
(BR)DSX
50 Ω
V
DS
0 V
VOLTAGE AND CURRENT WAVEFORMS
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: t ≤ 10 ns, t ≤ 10 ns, Z = 50 Ω.
r
f
O
B. Input pulse duration (t ) is increased until peak current I
= 7 A, where t = avalanche time.
w
AS
av
I
V
t
av
AS
(BR)DSX
2
Energy test level is defined as E
10.5 mJ
AS
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE THRESHOLD VOLTAGE
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.5
2
1
I
D
= 1.4 A
0.8
0.6
0.4
I
= 1 mA
D
1.5
1
I
D
= 100 µA
V
GS
= 10 V
V
GS
= 15 V
0.5
0
0.2
0
–40 –20
0
20 40 60 80 100 120 140 160
–40 –20
0
20 40 60 80 100 120 140 160
T
J
– Junction Temperature – °C
T
J
– Junction Temperature – °C
Figure 5
Figure 6
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5302
3-CHANNEL INDEPENDENT POWER DMOS ARRAY
SLIS029B – APRIL 1994 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
DRAIN CURRENT
vs
vs
DRAIN CURRENT
DRAIN-TO-SOURCE VOLTAGE
1
5
4
3
2
1
0
15 V
V
GS
= 5 V
T
J
= 25°C
V
= 0.2 V
GS
T
= 25°C
J
Unless Otherwise
Noted
V
GS
= 4 V
V
GS
= 10 V
V
GS
= 15 V
V
GS
= 3 V
0.1
0.01
0.1
1
10
0
1
2
3
4
5
6
7
8
9
10
I
D
– Drain Current – A
V
DS
– Drain-to-Source Voltage – V
Figure 7
Figure 8
DRAIN CURRENT
vs
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
GATE-TO-SOURCE VOLTAGE
0.5
5
T
J
= 125°C
T
= –40°C
Total Number of Units = 819
= 25°C
J
0.45
4.5
4
T
J
T
= 25°C
J
0.4
T
= 75°C
J
3.5
3
0.35
T
J
= 150°C
0.3
0.25
2.5
2
0.2
0.15
0.1
1.5
1
0.5
0
0.05
0
0
1
2
3
4
5
6
7
8
9
10
V
GS
– Gate-to-Source Voltage – V
g
fs
– Forward Transconductance – S
Figure 9
Figure 10
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5302
3-CHANNEL INDEPENDENT POWER DMOS ARRAY
SLIS029B – APRIL 1994 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
SOURCE-TO-DRAIN DIODE CURRENT
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
vs
SOURCE-TO-DRAIN VOLTAGE
10
250
225
200
175
150
125
100
75
f = 1 MHz
= 25°C
T
J
1
C
iss
T
= 125°C
= 150°C
J
T
= –40°C
= 25°C
= 75°C
J
T
J
C
oss
T
J
0.1
T
J
50
25
0
C
rss
0.01
0
4
8
12 16 20 24 28 32 36 40
– Drain-to-Source Voltage – V
0.1
1
10
V
DS
V
SD
– Source-to-Drain Voltage – V
Figure 11
Figure 12
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
GATE CHARGE
150
125
100
75
80
16
14
12
I
T
= 0.7 A
= 25°C
I
T
= 0.7 A
= 25°C
S
J
S
J
70
60
See Figure 1
See Figure 3
V
= 20 V
DD
D1, D2, and D3
V
= 30 V
DD
50
40
30
20
10
0
10
8
6
50
Q1, Q2, and Q3
4
V
DD
= 48 V
25
0
2
V
DD
= 20 V
0
0
100
200
300
400
500
600
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Reverse di/dt – A/µs
Q
– Gate Charge – nC
g
Figure 13
Figure 14
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5302
3-CHANNEL INDEPENDENT POWER DMOS ARRAY
SLIS029B – APRIL 1994 – REVISED SEPTEMBER 1995
THERMAL INFORMATION
MAXIMUM PEAK-AVALANCHE CURRENT
MAXIMUM DRAIN CURRENT
vs
vs
DRAIN-TO-SOURCE VOLTAGE
TIME DURATION OF AVALANCHE
10
10
†
1 µs
See Figure 4
T
C
= 25°C
†
10 ms
†
1 ms
T
C
= 25°C
1
†
500 µs
T
C
= 125°C
DC Conditions
1
0.1
0.1
0.001
0.01
0.1
1
10
1
10
100
t
av
– Time Duration of Avalanche – ms
V
DS
– Drain-to-Source Voltage – V
†
Figure 16
Less than 0.1 duty cycle
Figure 15
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC5302
3-CHANNEL INDEPENDENT POWER DMOS ARRAY
SLIS029B – APRIL 1994 – REVISED SEPTEMBER 1995
THERMAL INFORMATION
†
D PACKAGE
NORMALIZED JUNCTION-TO-AMBIENT THERMAL RESISTANCE
vs
PULSE DURATION
10
DC Conditions
d = 0.5
1
d = 0.2
d = 0.1
0.1
d = 0.05
d = 0.02
d = 0.01
0.01
0.001
Single Pulse
t
c
t
w
I
D
0
0.0001
0.0001
0.001
0.01
0.1
– Pulse Duration – s
1
10
t
w
†
Device mounted on FR4 printed-circuit board with no heat sink
NOTE A: Z (t) = r(t) R
θA θJA
t
= pulse duration
w
t = cycle time
c
d = duty cycle = t /t
w c
Figure 17
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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Copyright 1998, Texas Instruments Incorporated
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