TLV5621ED [TI]
8 位、10us 四路 DAC，串行输入、简单 2 线接口、可编程 1x 或 2x 输出、断电功能 | D | 14 | -40 to 85;
| 型号： | TLV5621ED |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8 位、10us 四路 DAC，串行输入、简单 2 线接口、可编程 1x 或 2x 输出、断电功能 | D | 14 | -40 to 85 光电二极管 转换器 数模转换器 |
| 文件： | 总17页 (文件大小：240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
2.7-V to 5.5-V Single-Supply Operation
Low Power Consumption
Half-Buffered Output
Power-Down Mode
Four 8-Bit Voltage Output DACs
One-Half Power 8-Bit Voltage Output DAC
Fast Serial Interface . . . 1 MHz Max
applications
Simple Two-Wire Interface In Single
Buffered Mode
Programmable Voltage Sources
Digitally-Controlled Amplifiers/Attenuators
Cordless/Wireless Communications
Automatic Test Equipment
High-Impedance Reference Inputs For Each
DAC
Programmable for 1 or 2 Times Output
Range
Portable Test Equipment
Simultaneous-Update Facility In
Double-Buffered Mode
Process Monitoring and Control
Signal Synthesis
Internal Power-On Reset
Industry Temperature Range
D PACKAGE
(TOP VIEW)
description
The TLV5621I is a quadruple 8-bit voltage output
digital-to-analog converter (DAC) with buffered
reference inputs (high impedance). The DAC
produces an output voltage that ranges between
either one or two times the reference voltages and
GND, and the DAC is monotonic. The device is
simple to use since it operates from a single
supply of 2.7 V to 5.5 V. A power-on reset function
is incorporated to provide repeatable start-up
conditions. A global hardware shut-down terminal
and the capability to shut down each individual
DAC with software are provided to minimize
power consumption.
GND
REFA
REFB
REFC
REFD
DATA
CLK
V
1
2
3
4
5
6
7
14
13
12
11
10
9
DD
HWACT
DACA
DACB
DACC
DACD
EN
8
Digital control of the TLV5621I is over a simple 3-wire serial bus that is CMOS compatible and easily interfaced
to all popular microprocessor and microcontroller devices. A TLV5621I 11-bit command word consists of
eight bits of data, two DAC select bits, and a range bit for selection between the times one or times two output
range. The TLV5621I digital inputs feature Schmitt triggers for high noise immunity. The DAC registers are
double buffered which allows a complete set of new values to be written to the device, and then under control
of the HWACT signal, all of the DAC outputs are updated simultaneously.
The 14-terminal small-outline (D) package allows digital control of analog functions in space-critical
applications. The TLV5621I does not require external trimming. The TLV5621I is characterized for operation
from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
T
A
(D)
–40°C to 85°C
TLV5621ID
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
functional block diagram
REFA
+
–
DAC
DAC
DAC
DAC
+
–
DACA
DACB
DACC
DACD
× 2
× 2
× 2
× 2
8
8
8
8
8
Latch
Latch
Latch
Latch
Latch
Latch
Latch
Latch
REFB
+
–
+
–
8
8
REFC
REFD
+
–
+
–
+
–
+
–
8
CLK
DATA
Power-On
Reset
Serial
Interface
EN
HWACT
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
CLK
NO.
7
12
11
10
9
I
Serial interface clock, data enters on the negative edge
DAC A analog output
DACA
DACB
DACC
DACD
DATA
EN
O
O
O
O
I
DAC B analog output
DAC C analog output
DAC D analog output
6
Serial-interface digital-data input
Input enable
8
I
GND
1
Ground return and reference
Global hardware activate
HWACT
REFA
REFB
REFC
REFD
13
2
I
I
I
I
I
Reference voltage input to DACA
Reference voltage input to DACB
Reference voltage input to DACC
Reference voltage input to DACD
Positive supply voltage
3
4
5
V
DD
14
detailed description
The TLV5621 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with
256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected
to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use
of the resistor strings. Linearity depends upon the matching of the resistor elements and upon the performance
of the output buffer. Because the inputs are buffered, the DACs always present a high-impedance load to the
reference source.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times one
or times two gain.
On power-up, the DACs are reset to CODE 0.
Each output voltage is given by:
CODE
V (DACA|B|C|D)
REF
(1 RNG bit value)
O
256
where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.
Table 1. Ideal-Output Transfer
D7
0
0
•
D6
0
0
•
D5
0
0
•
D4
0
0
•
D3
0
0
•
D2
0
0
•
D1
0
0
•
D0
0
1
•
OUTPUT VOLTAGE
GND
(1/256) × REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
0
1
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
1
0
•
(127/256) × REF (1+RNG)
(128/256) × REF (1+RNG)
•
•
•
•
•
•
•
•
•
•
1
1
1
1
1
1
1
1
(255/256) × REF (1+RNG)
data interface
The data interface has two modes of operation; single and double buffered. Both modes serially clock in bits
of data using DATA and CLK whenever EN is high. When EN is low, CLK is disabled and data cannot be loaded
into the buffers.
In the single buffered mode, the DAC outputs are updated on the last/twelfth falling edge of CLK, so this mode
only requires a two-wire interface with EN tied high (see Figure 1 and Figure 2).
In the double buffered mode (startup default), the outputs of the DACs are updated on the falling edge of the
EN strobe (see Figure 3 and Figure 4). This allows multiple devices to share data and clock lines by having only
separate EN lines.
single-buffer mode (MODE = 1)
When a two wire interface is used, EN is tied high and the input to the device is always active; therefore, random
data can be clocked into the input latch. In order to regain word synchronization, twelve zeros are clocked in
as shown in Figure 1, and then a data or control word is clocked in. In Figure 1, the MODE bit is set to one, and
a control word is clocked in with the DAC outputs becoming active after the last falling edge of the control word.
Figure 2 shows valid data being written to a DAC, note that CLK is held low while the data is invalid. Data can
be written to all four DACs and then the control word is clocked in which sets the MODE bit to 1. At the end of
the control word, the data is latched to the inputs of the DACs.
Note that once the MODE bit has been set, it is not possible to clear it, i.e., it is not possible to move from single
to double-buffered mode.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLK
MODE
RNG RNG RNG RNG
RS
DATA
DAC
SIA SIB SIC SID ACT
A
B
C
D
EN
(Tied High)
NOTE A: Twelve zeros enable word synchronization and the output can change after the leading edge of CLK depending on the data in the latches.
Figure 1. Register Write Operation Following Noise or Undefined Levels on DATA or CLK (Single-Buffer Mode)
CLK
MODE
RNG RNG RNG RNG
DATA
DAC
RS
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
RS
SIA SIB SIC SID ACT
A
B
C
D
EN
(Tied High)
NOTE A: EN is held high and data is written to a DAC register. The data is latched to the output of the DAC on the falling edge of the last CLK of the control word, where the
mode is set.
Figure 2. First Nonzero Write Operation After Startup (EN = High)
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
double-buffered mode (MODE = 0)
In this mode, data is only latched to the output of the DACs on the falling edge of the EN strobe. Therefore, all
four DACs can be written to before updating their outputs.
Any number of input data blocks can be written with all having the same length. Subsequent data blocks simply
overwrite previous ones with the same address until EN goes low.
Multiple data blocks can be written in any sequence provided signal timing limits are met. The negative going
edge of EN terminates and latches all data.
Multiple Random Sequence Data Blocks
DATA
Data Latched Into DAC Control Registers and Control Word
EN
Figure 3. Data and Control Serial Control
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CLK
RNG RNG RNG RNG
MODE
RS
RS
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SIA SIB SIC SID ACT
DATA
A
B
C
D
DAC
EN
NOTE A: Data is written to the output of a DAC, and the data is latched to the output on the falling edge of EN. A control word then selects double-buffered mode. When the
range is changed, the output changes on the falling edge of EN.
Figure 4. First Nonzero Write Operation After Startup
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
control register
The control register contains ten active bits. Four bits are range select bits as on the TLC5620. The register also
contains a software shutdown bit (ACT) and four shutdown inhibit bits (SIA, SIB, SIC, SID). The shutdown inhibit
bits act on each DAC (DACA through DACD). The mode select bit is used to change between single and double
buffered modes. The bits in the control register are listed in Table 2.
Table 2. Control Register Bits
BIT
MODE
RNG A
RNG B
RNG C
RNG D
SIA
FUNCTION
Selection bit for type of interface (see data interface section)
Range select bit for DACA, 0 = 1, 1 =
Range select bit for DACB, 0 = 1, 1 =
Range select bit for DACC, 0 = 1, 1 =
Range select bit for DACD, 0 = 1, 1 =
Shutdown inhibit bit for DACA
2
2
2
2
SIB
Shutdown inhibit bit for DACB
SIC
Shutdown inhibit bit for DACC
SID
Shutdown inhibit bit for DACD
ACT
Software shutdown bit
The SIx bits inhibit the actions of the shutdown bits as shown in Table 3. When the ACT bit is 1 or the HWACT
signal is high (active), the inhibit bits act as enable bits in inverse logic terms. The ACT software shutdown bit
and HWACT (asynchronously acting hardware terminal) are logically ORed together.
This configuration allows any combination of DACs to be shut down to save power.
Table 3. Shutdown Inhibit Bits and HWACT Signal
SIx
0
ACT
HWACT
DACx STATUS
Shutdown (see Note 1)
Shutdown
0
0
1
1
0
0
1
1
L
H
L
0
0
Shutdown
0
H
L
Active (see Note 1)
Active
1
1
H
L
Active
1
Active
1
H
Active
NOTE 1: Sense of HWACT terminal and ACT bit were changed from early
versions of this specification.
The values of the input address select bits, A0 and A1, and the updated DAC are listed in Table 4.
Table 4. Serial Input Decode
INPUT ADDRESS SELECT BITS
DAC UPDATED
A1
A0
0
0
DACA
DACB
DACC
DACD
0
1
1
0
1
1
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
power-on reset
Power-on reset circuitry is available on the TLV5621I. The threshold to trigger a power-on reset is 1.95 V typical
(1.4 V min and 2.5 V max). For a power-on reset, all DACs are shut down. The control register bit values and
states after a power-on reset are listed in Table 5.
Table 5. Control Register Bit Values and States After Power-On Reset
BIT
MODE
RNG A
RNG B
RNG C
RNG D
SIA
VALUE
STATE AFTER POWER-ON RESET
0
1
1
1
1
0
0
0
0
0
Double buffer mode selected
Range
Range
Range
Range
2
2
2
2
Shutdown affects DACA according to ACT state
Shutdown affects DACB according to ACT state
Shutdown affects DACC according to ACT state
Shutdown affects DACD according to ACT state
DACs in shutdown state
SIB
SIC
SID
ACT
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
linearity, offset, and gain error using single-end supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage
may not change with the first code depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.
Output
Voltage
0 V
DAC Code
Negative
Offset
Figure 5. Effect of Negative Offset (Single Supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage. The code is
calculated from the maximum specification for the negative offset.
equivalent inputs and outputs
INPUT CIRCUIT
OUTPUT CIRCUIT
V
DD
V
DD
_
+
Input from
Decoded DAC
Register String
DAC
Voltage Output
V
ref
Input
× 1
84 kΩ
Output
Range
Select
To DAC
Resistor
String
I
× 2
SINK
60 µA
Typical
84 kΩ
GND
GND
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (V
– GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V
Reference input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V
Operating free-air temperature range, T
Storage temperature range, T
+ 0.3 V
+ 0.3 V
DD
DD
ID
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50°C to 150°C
A
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
NOM
MAX
UNIT
V
Supply voltage, V
(see Note 2)
2.7
3.3
5.5
DD
High-level digital input voltage, V
0.8 V
V
IH
DD
Low-level digital input voltage, V
0.2 V
V
IL
Reference voltage, V [A|B|C|D], x1 gain
DD
GND
V
DD
–1.5
V
ref
Load resistance, R
10
50
kΩ
ns
ns
ns
ns
L
Setup time, data input, t
su(DATA-CLK)
Hold time, data input valid after CLK↓, t
(see Figure 6)
(see Figure 6)
50
h(DATA-CLK)
(see Figure 7)
Setup time, CLK↓ to EN↓, t
Setup time, EN↑ to CLK↓, t
100
100
su(CLK-EN)
su(EN-CLK)
(see Figure 7) (see Note 3)
Pulse duration, EN low, t
(see Figure 7) (see Note 3)
200
400
ns
ns
w(EN)
Pulse duration, CLK high, t
CLK frequency
(see Figure 6) (see Note 3)
w(CLK)
1
MHz
°C
Operating free-air temperature, T
–40
85
A
NOTES: 2. The device operates over the supply voltage range of 2.7 V to 5.5 V. Over this voltage range the device responds correctly to data
input by changing the output voltage but conversion accuracy is not specified over this extended range.
3. This is specified by design but is not production tested.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
electrical characteristics over recommended operating free-air temperature range,
V
= 3 V to 3.6 V, V = 1.25 V, GND = 0 V, R = 10 kΩ, C = 100 pF, × 1 gain output range
DD
ref L L
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Maximum full-scale output
voltage
V
O
max
V
ref
= 1.5 V, open circuit output, × 2 gain
V – 100
DD
2
mV
I
I
High-level digital input current
Low-level digital input current
Output sink current, DACA
V = V
±10
±10
µA
µA
µA
IH(digital)
I
DD
V = 0 V
I
IL(digital)
DAC code 0
5
20
1
I
I
Output sink current, DACB,
DACC, DACD
O(sink)
DAC code 0
µA
Output source current
Input capacitance
Each DAC output, DAC code 255
mA
O(source)
15
15
1
C
pF
i
Reference input capacitance
A, B, C, D inputs
V
= 3.6 V
= 5 V
1.5
1.5
mA
mA
DD
DD
I
I
Supply current
DD
V
1
Supply current, one low power
DAC active
V
= 3.6 V, See Note 4
= 3.6 V, See Note 4
150
50
250
100
µA
µA
DD(active)
DD
DD
Supply current, all DACs shut
down
I
I
V
DD(shutdown)
Reference input current
Integral linearity error
Differential linearity error
Zero-scale error
A, B, C, D inputs
±10
±1
µA
LSB
LSB
mV
ref
E
E
E
V
= 1.25 V, × 2 gain, See Notes 5 and 13
= 1.25 V, × 2 gain, See Notes 6 and 13
= 1.25 V, × 2 gain, See Note 7
ref
L
ref
V
ref
±0.1
±0.9
30
D
V
0
ZS
Zero-scale error temperature
coefficient
V
= 1.25 V, × 2 gain, See Note 8
10
2
µV/°C
ref
Zero-scale error supply rejection
Full-scale error
mV/V
mV
E
FS
V
ref
= 1.25 V, × 2 gain, See Note 9
= 1.25 V, × 2 gain, See Note 10
±60
Full-scale error temperature
coefficient
V
ref
±25
µV/°C
Full-scale error supply rejection
Power-supply sensitivity
2
mV/V
mV/V
PSRR
See Notes 11 and 12
0.5
Feedback resistor network
resistance
168
kΩ
NOTES: 4. This is measured with no load (open circuit output), V = 1.25 V, range = × 2.
ref
5. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects
of zero code and full-scale errors).
6. Differentialnonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.
Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.
7. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6
8. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(T
) – ZSE(T
)]/V × 10 /(T
– T
).
min
max
min ref max
9. Full-scale error is the deviation from the ideal full-scale output (V – 1 LSB) with an output load of 10 kΩ.
ref
6
10. Full-scale temperature coefficient is given by: FSETC = [FSE(T
max
) – FSE (T
)]/V × 10 /(T
ref max
voltage from 4.5 V to 5.5 V dc and measuring the effect
– T
).
min
min
11. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the V
of this signal on the zero-code output voltage.
DD
12. Full-scale error rejection ratio (FSE-RR) is measured by varing the V
this signal on the full-scale output voltage.
voltage from 3 V to 3.6 V dc and measuring the effect of
DD
13. Linearity is only specified for DAC codes 1 through 255.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
operating characteristics over recommended operating free-air temperature range,
V
= 3 V to 3.6 V, V = 1.25 V, GND = 0 V, R = 10 kΩ, C = 100 pF, × 1 gain output range
DD
ref L L
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
0.8
0.5
1
MAX
UNIT
V/µs
V/µs
V/µs
µs
Output slew rate, rising (DACA)
Output slew rate, falling (DACA)
Output slew rate (DACB, DACC, DACD)
Output settling time, rising (DACA)
Output settling time, falling (DACA)
To 1/2 LSB,
To 1/2 LSB,
V
V
= 3 V
= 3 V
20
DD
75
µs
DD
Output settling time, rising (DACB, DACC,
DACD)
To 1/2 LSB,
To 1/2 LSB,
To 1/2 LSB,
V
V
V
= 3 V
= 3 V
= 3 V
10
75
40
µs
µs
µs
DD
DD
DD
Output settling time, falling (DACB, DACC,
DACD)
Output settling time, HWACT or ACT↑ to
output volts (DACA) (see Note 14)
†
†
120
Output settling time, HWACT or ACT↑ to
output volts (DACB, DACC, DACD)
(see Note 14)
To 1/2 LSB,
V
DD
= 3 V
25
75
µs
Large-signal bandwidth
Digital crosstalk
Measured at –3 dB point
100
–50
–60
–60
kHz
dB
CLK = 1-MHz square wave measured at DACA–DACD
A, B, C, D inputs, See Note 15
Reference feedthrough
Channel-to-channel isolation
dB
A, B, C, D inputs, See Note 16
dB
Channel-to-channel isolation when in
shutdown
A, B, C, D inputs
–40
dB
Reference bandwidth (DACA)
See Note 17
20
kHz
kHz
Reference bandwidth (DACB, DACC, DACD) See Note 17
100
†
This is specified by characterization but is not production tested.
NOTES: 14. The ACT bit is latched on EN↓.
15. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a V input = 1 V dc + 1 V
16. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex
at 10 kHz.
ref
PP
with V input = 1 V dc + 1 V
ref PP
at 10 kHz.
17. Reference bandwidth is the –3 dB bandwidth with an ideal input at V = 1.25 V dc + 2 V
and with a digital input code of full-scale
ref PP
(range set to × 1 and V
= 5 V).
DD
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
PARAMETER MEASUREMENT INFORMATION
t
w(CLK)
50%
50%
50%
CLK
t
h(DATA-CLK)
t
su(DATA-CLK)
DATA
Figure 6. Timing of DATA Relative to CLK
EN
50%
t
50%
t
w(EN)
su(EN-CLK)
t
su(CLK-EN)
50%
50%
CLK
DATA
Figure 7. Timing of CLK Relative to EN
TLV5621
DACA
DACB
DACC
10 kΩ
C
= 100 pF
L
DACD
Figure 8. Slewing Settling Time and Linearity Measurements
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
TYPICAL CHARACTERISTICS
POSITIVE RISE TIME AND SETTLING TIME
NEGATIVE FALL TIME AND SETTLING TIME
3
2.5
2
3
2.5
2
V
T
A
= 3 V
DD
= 25°C
Code FF to
00 Hex
Range = ×2
1.5
1
1.5
1
V
ref
= 1.25 V
V
= 3 V
DD
= 25°C
(see Notes
A and B)
T
A
0.5
0.5
Code 00 to
FF Hex
Range = ×2
0
0
V
ref
= 1.25 V
(see Notes
A and B)
–0.5
–0.5
–1
–1
0
2
4
6
8
10 12 14 16 18 20
0
2
4
6
8
10 12 14 16 18 20
t – Time – µs
t – Time – µs
NOTES: A. Fall time = 4.25 µs, negative slew rate = 0.46 V/µs,
settling time = 8.5 µs.
NOTES: A. Rise time = 2.05 µs, positive slew rate = 0.96 V/µs,
settling time = 4.5 µs.
B. For DACB, DACC, and DACD
B. For DACB, DACC, and DACD
Figure 9
Figure 10
DAC OUTPUT VOLTAGE
DAC OUTPUT VOLTAGE
vs
LOAD RESISTANCE
vs
LOAD RESISTANCE
1.6
3
2.8
2.6
2.4
2.2
2
1.4
1.2
1
0.8
0.6
1.8
1.6
V
= 3 V
= 1.5 V
DD
V
= 3 V
= 1.5 V
0.4
DD
V
ref
V
ref
1.4
1.2
1
Range = ×1
Range = ×2
(see Note A)
0.2
0
(see Note A)
0
10 20 30 40 50 60 70 80 90 100
0
10 20 30 40 50 60 70 80 90 100
R
– Load Resistance – kΩ
R
– Load Resistance – kΩ
L
L
NOTE A: For DACB, DACC, and DACD
NOTE A: For DACB, DACC, and DACD
Figure 11
Figure 12
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
1.2
Range = ×2
Input Code = 255
1.15
V
V
= 3 V
= 1.25 V
DD
ref
1.1
1.05
1
0.95
0.9
0.85
0.8
–50
0
50
100
T
A
– Free-Air Temperature – °C
Figure 13
APPLICATION INFORMATION
_
+
TLV5621
V
O
DACA
DACB
DACC
DACD
R
NOTE A: Resistor R
10 kΩ
Figure 14. Output Buffering Scheme
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5621I
LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER
SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/B 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Four center pins are connected to die mount pad.
E. Falls within JEDEC MS-012
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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