TLV5623CD [TI]
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN; 2.7 V至5.5 V低功耗的8位数字 - 模拟与电源降压转换器
| 型号： | TLV5623CD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN |
| 文件： | 总18页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
8-Bit Voltage Output DAC
Buffered High-Impedance Reference Input
Programmable Settling Time vs Power
Consumption
Monotonic Over Temperature
Available in MSOP Package
3 µs in Fast Mode
9 µs in Slow Mode
applications
Ultra Low Power Consumption:
900 µW Typ in Slow Mode at 3 V
2.1 mW Typ in Fast Mode at 3 V
Digital Servo Control Loops
Digital Offset and Gain Adjustment
Industrial Process Control
Differential Nonlinearity . . . <0.2 LSB Typ
Machine and Motion Control Devices
Mass Storage Devices
Compatible With TMS320 and SPI Serial
Ports
Power-Down Mode
D OR DGK PACKAGE
(TOP VIEW)
description
The TLV5623 is a 8-bit voltage output digital-to-
analog converter (DAC) with a flexible 4-wire
serial interface. The 4-wire serial interface allows
glueless interface to TMS320, SPI, QSPI, and
Microwire serial ports. The TLV5623 is pro-
grammed with a 16-bit serial string containing 4
control and 12 data bits. Developed for a wide
range of supply voltages, the TLV5623 can
operate from 2.7 V to 5.5 V.
DIN
SCLK
CS
V
DD
OUT
1
2
3
4
8
7
6
5
REFIN
AGND
FS
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow
the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within
the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need
for a low source impedance drive to the terminal.
Implemented with a CMOS process, the TLV5623 is designed for single supply operation from 2.7 V to 5.5 V.
The device is available in an 8-terminal SOIC package. The TLV5623C is characterized for operation from 0°C
to 70°C. The TLV5623I is characterized for operation from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
†
T
A
SMALL OUTLINE
(D)
MSOP
(DGK)
0°C to 70°C
TLV5623CD
TLV5623ID
TLV5623CDGK
TLV5623IDGK
–40°C to 85°C
†
Available in tape and reel as the TLV5623CDR and the TLV5623IDR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
functional block diagram
_
6
+
REFIN
DIN
10
8
Serial Input
Register
1
8-Bit
Data
Latch
8
7
x2
OUT
2
3
4
SCLK
CS
Update
16 Cycle
Timer
FS
2
Power-On
Reset
Speed/Power-Down
Logic
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
CS
5
3
1
4
7
6
2
8
Analog ground
I
I
Chip select. Digital input used to enable and disable inputs, active low.
Serial digital data input
DIN
FS
I
Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface.
OUT
REFIN
SCLK
O
I
DAC analog output
Reference analog input voltage
Serial digital clock input
Positive power supply
I
V
DD
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (V
to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to V
+ 0.3 V
+ 0.3 V
DD
DD
Operating free-air temperature range, T : TLV5623C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLV5623I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM
MAX
5.5
UNIT
V
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 5 V
4.5
2.7
2
5
3
Supply voltage, V
DD
= 3 V
3.3
V
High-level digital input voltage, V
= 2.7 V to 5.5 V
= 2.7 V to 5.5 V
= 5 V (see Note 1)
= 3 V (see Note 1)
V
IH
Low-level digital input voltage, V
0.8
V
IL
Reference voltage, V to REFIN terminal
AGND 2.048
AGND 1.024
V
–1.5
V
ref
Reference voltage, V to REFIN terminal
DD
V
–1.5
V
ref
DD
Load resistance, R
2
10
kΩ
pF
MHz
°C
°C
L
Load capacitance, C
100
L
Clock frequency, f
20
70
85
CLK
TLV5623C
TLV5623I
0
–40
Operating free-air temperature, T
A
NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ V
causes clipping of the transfer function.
DD/2
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 5 V, VREF = 2.048 V,
DD
Fast
0.9
1.35
mA
No load,
All inputs = AGND or V
DAC latch = 0x800
,
,
DD
DD
Slow
Fast
0.4
0.7
0.6
1.1
mA
mA
I
Power supply current
DD
V
= 3 V, VREF = 1.024 V
DD
No load,
All inputs = AGND or V
DAC latch = 0x800
Slow
0.3
1
0.45
mA
Power down supply current (see Figure 12)
µA
Zero scale See Note 2
–68
–68
2
PSRR
Power supply rejection ratio
dB
V
Full scale
See Note 3
Power on threshold voltage, POR
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying V
and is given by:
and is given by:
DD
PSRR = 20 log [(E (V max) – E (V min))/V max]
ZS DD ZS DD DD
3. Power supply rejection ratio at full scale is measured by varying V
DD
PSRR = 20 log [(E (V max) – E (V min))/V max]
DD DD DD
G
G
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
static DAC specifications R = 10 kΩ, C = 100 pF
L
L
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
bits
Resolution
8
INL
Integral nonlinearity
See Note 4
± 0.3
±0.5
± 0.2
±10
LSB
DNL
Differential nonlinearity
See Note 5
See Note 6
See Note 7
± 0.07
LSB
E
E
Zero-scale error (offset error at zero scale)
Zero-scale-error temperature coefficient
mV
ZS
10
ppm/°C
ZS TC
% of
FS
voltage
E
G
Gain error
See Note 8
±0.6
Gain-error temperature coefficient
See Note 9
10
ppm/°C
NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6
7. Zero-scale-error temperature coefficient is given by: E
TC = [E
(T
) – E
(T
)]/V × 10 /(T
– T
).
min
ZS
8. Gain error is the deviation from the ideal output (2V – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
ZS max
ZS min
ref max
ref
6
9. Gain temperature coefficient is given by: E TC = [E (T
) – E (T
)]/V × 10 /(T – T
max
).
min
G
G
max
G
min
ref
output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
–0.1
UNIT
V
O
Voltage output range
R
R
= 10 kΩ
0
V
V
L
L
DD
% of FS
voltage
Output load regulation accuracy
= 2 kΩ, vs 10 kΩ
±0.1
±0.25
reference input (REF)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
I
Input voltage range
Input resistance
0
V
–1.5
DD
R
C
10
5
MΩ
pF
I
I
Input capacitance
Slow
Fast
525
1.3
kHz
MHz
Reference input bandwidth
Reference feed through
REFIN = 0.2 V + 1.024 V dc
pp
REFIN = 1 V at 1 kHz + 1.024 V dc
pp
(see Note 10)
–75
dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER
High-level digital input current
Low-level digital input current
Input capacitance
TEST CONDITIONS
MIN
TYP
MAX
±1
UNIT
µA
I
I
V = V
I
IH
DD
V = 0 V
±1
µA
IL
I
C
3
pF
I
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
3
MAX
5.5
UNIT
C
= 100 pF,
Fast
Slow
Fast
Slow
Fast
Slow
R
= 10 kΩ,
L
L
t
t
Output settling time, full scale
µs
s(FS)
See Note 11
9
20
C
= 100 pF,
1
µs
µs
R
= 10 kΩ,
L
L
Output settling time, code to code
Slew rate
s(CC)
See Note 12
2
3.6
0.9
10
57
49
–50
60
R
= 10 kΩ,
See Note 13
C
= 100 pF,
L
L
SR
V/µs
Glitch energy
Code transition from 0x7F0 to 0x800
nV–s
dB
S/N
Signal to noise
fs = 400 KSPS fout = 1.1 kHz,
S/(N+D) Signal to noise + distortion
dB
R
= 10 kΩ,
BW = 20 kHz
C = 100 pF,
L
L
THD
Total harmonic distortion
dB
Spurious free dynamic range
dB
NOTES: 11. Settling time is the time for the output signal to remain within ±0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFF0 or 0xFF0 to 0x020. Not tested, ensured by design.
12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, ensured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN NOM
MAX
UNIT
ns
t
t
Setup time, CS low before FS↓
10
8
su(CS–FS)
Setup time, FS low before first negative SCLK edge
ns
su(FS–CK)
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
t
10
ns
su(C16–FS)
su(C16–CS)
Setuptime,sixteenthpositiveSCLKedge(firstpositiveafterD0issampled)beforeCSrising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
t
10
ns
t
t
t
Pulse duration, SCLK high
25
25
8
ns
ns
ns
wH
Pulse duration, SCLK low
wL
Setup time, data ready before SCLK falling edge
su(D)
t
Hold time, data held valid after SCLK falling edge
Pulse duration, FS high
5
ns
ns
h(D)
t
20
wH(FS)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
PARAMETER MEASUREMENT INFORMATION
t
t
wH
wL
SCLK
DIN
1
2
3
4
5
15
16
t
t
su(D)
h(D)
D15
D14
D13
D12
D1
D0
t
su(FS-CK)
t
su(C16-CS)
t
su(CS-FS)
CS
FS
t
wH(FS)
t
su(C16-FS)
Figure 1. Timing Diagram
6
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TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
LOAD CURRENT
LOAD CURRENT
2.004
2.002
2
4.01
3 V Slow Mode, SOURCE
3 V Fast Mode, SOURCE
V
= 3 V,
= 1 V,
V
V
ref
Full Scale
= 5 V,
= 2 V,
DD
DD
V
ref
5 V Slow Mode, SOURCE
4.005
Full Scale
4
3.995
3.99
5 V Fast Mode, SOURCE
1.998
1.996
1.994
1.992
1.990
3.985
3.98
3.975
0
0.01 0.02 0.05 0.1 0.2
Load Current – mA
0.5
1
2
0
0.02 0.04 0.1 0.2 0.4
Load Current – mA
1
2
4
Figure 2
Figure 3
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
LOAD CURRENT
LOAD CURRENT
0.2
0.35
0.3
V
= 3 V,
= 1 V,
DD
V
= 5 V,
= 2 V,
DD
0.18
V
ref
V
ref
Zero Code
Zero Code
0.16
0.14
0.12
0.1
0.25
0.2
3 V Slow Mode, SINK
5 V Slow Mode, SINK
0.15
0.08
0.06
5 V Fast Mode, SINK
3 V Fast Mode, SINK
0.1
0.05
0
0.04
0.02
0
0
0.01 0.02 0.05 0.1 0.2 0.5
Load Current – mA
1
2
0
0.02 0.04 0.1 0.2 0.4
Load Current – mA
1
2
4
Figure 4
Figure 5
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
1
V
V
= 3 V,
= 1 V,
V
V
= 5 V,
= 2 V,
DD
ref
DD
ref
Full Scale
Full Scale
Fast Mode
0.8
0.8
Fast Mode
0.6
0.4
0.2
0.6
0.4
0.2
Slow Mode
Slow Mode
25 40
–55 –40 –25
0
70
85 125
–55 –40 –25
0
25
40
70
85 125
T
A
– Free-Air Temperature – C°
T
A
– Free-Air Temperature – C°
Figure 6
Figure 7
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
0
0
V
= 1 V dc + 1 V p/p Sinewave,
ref
V
= 1 V dc + 1 V p/p Sinewave,
ref
–10
Output Full Scale
–10
Output Full Scale
–20
–30
–20
–30
––40
––40
–50
–60
–50
–60
Fast Mode
Slow Mode
–70
–80
–70
–80
0
5
10
20
30
50
100
0
5
10
20
30
50
100
f – Frequency – kHz
f – Frequency – kHz
Figure 8
Figure 9
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION AND NOISE
TOTAL HARMONIC DISTORTION AND NOISE
vs
vs
FREQUENCY
FREQUENCY
0
0
V
= 1 V dc + 1 V p/p Sinewave,
V
= 1 V dc + 1 V p/p Sinewave,
ref
ref
Output Full Scale
–10
Output Full Scale
–10
–20
–30
–20
–30
––40
––40
–50
–60
–50
–60
Fast Mode
Slow Mode
–70
–80
–70
–80
0
5
10
20
30
50
100
0
5
10
20
30
50
100
f – Frequency – kHz
f – Frequency – kHz
Figure 10
Figure 11
SUPPLY CURRENT
vs
TIME (WHEN ENTERING POWER-DOWN MODE)
900
800
700
600
500
400
300
200
100
0
0
100 200 300 400 500 600 700 800 900 1000
T – Time – ns
Figure 12
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.10
0.08
0.06
0.04
0.02
0.00
–0.02
–0.04
–0.06
–0.08
–0.10
0
255
64
128
192
Digital Output Code
Figure 13
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.5
0.4
0.3
0.2
0.1
–0.0
–0.1
–0.2
–0.3
–0.4
–0.5
0
255
64
128
192
Digital Output Code
Figure 14
10
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TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
APPLICATION INFORMATION
general function
TheTLV5623isan8-bitsinglesupplyDACbasedonaresistorstringarchitecture. Thedeviceconsistsofaserial
interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output
buffer.
The output voltage (full scale determined by external reference) is given by:
CODE
2 REF
[V]
0x1000
Where REF is the reference voltage and CODE is the digital input value within the range of 0x000 to 0xFF0.
Bits 3 to 0 must be set to zero. A power-on reset initially resets the internal latches to a defined state (all bits
zero).
serial interface
The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting
with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS
rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new
level.
The serial interface of the TLV5623 can be used in two basic modes:
Four wire (with chip select)
Three wire (without chip select)
Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows
an example with two TLV5623s connected directly to a TMS320 DSP.
TLV5623
TLV5623
CS FS DIN SCLK
CS FS DIN SCLK
TMS320
DSP
XF0
XF1
FSX
DX
CLKX
Figure 15. TMS320 Interface
11
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TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5623 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSP
TLV5623
SPI
TLV5623
Microwire
TLV5623
FSX
FS
SS
FS
I/O
FS
DIN
DIN
DIN
DX
MOSI
SCLK
SO
SK
CLKX
SCLK
CS
SCLK
CS
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5623. After the write operation(s), the DAC output is updated automatically
on the sixteenth positive clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
1
f
20 MHz
SCLKmax
t
t
wH(min)
wL(min)
The maximum update rate is:
1
f
1.25 MHz
UPDATEmax
16
t
t
wH(min)
wL(min)
The maximum update rate is a theoretical value for the serial interface, since the settling time of the TLV5623
has to be considered also.
data format
The 16-bit data word for the TLV5623 consists of two parts:
Control bits
(D15 . . . D12)
(D11 . . . D0)
New DAC value
D15
X
D14
D13
D12
X
D11
D10
D9
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
SPD
PWR
New DAC value (8 bits)
X: don’t care
SPD: Speed control bit.
1 → fast mode
0 → slow mode
PWR: Power control bit. 1 → power down
0 → normal operation
In power-down mode, all amplifiers within the TLV5623 are disabled.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
APPLICATION INFORMATION
TLV5623 interfaced to TMS320C203 DSP
hardware interfacing
Figure 17 shows an example how to connect the TLV5623 to a TMS320C203 DSP. The serial interface of the
TLV5623 is ideally suited to this configuration, using a maximum of four wires to make the necessary
connections. In applications where only one synchronous serial peripheral is used, the interface can be
simplified even further by pulling CS low all the time as shown in the figure.
TMS320C203
TLV5623
V
DD
FS
DX
FS
DIN
SCLK
OUT
REFIN
CLKX
REF
R
LOAD
CS AGND
Figure 17. TLV5623 to DSP Interface
TLV5623 interfaced to MCS51 microcontroller
hardware interfacing
Figure 18 shows an example of how to connect the TLV5623 to an MCS51 compatible microcontroller. The
serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent
on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide
the chip select and frame sync signals for the TLV5623.
MCS51 Controller
TLV5623
V
DD
RxD
TxD
SDIN
SCLK
CS
FS
P3.4
P3.5
OUT
REFIN
REF
R
LOAD
AGND
Figure 18. TLV5623 to MCS51 Controller Interface
MCS is a registered trademark of Intel Corporation
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
APPLICATION INFORMATION
linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19.
Output
Voltage
0 V
DAC Code
Negative
Offset
Figure 19. Effect of Negative Offset (single supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after
offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not
allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity
is measured between full-scale code and the lowest code that produces a positive output voltage.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well managed and there are negligible voltage drops across the ground plane.
A0.1-µFceramic-capacitorbypassshouldbeconnectedbetweenV andAGNDandmountedwithshortleads
DD
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 20 shows the ground plane layout and bypassing technique.
Analog Ground Plane
1
2
3
4
8
7
6
5
0.1 µF
Figure 20. Power-Supply Bypassing
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
APPLICATION INFORMATION
definitions of specifications and terminology
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
zero-scale error (E
)
ZS
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
gain error (E )
G
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (S/N+D)
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
spurious free dynamic range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.050 (1,27)
0.020 (0,51)
0.010 (0,25)
M
0.014 (0,35)
14
8
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
0.010 (0,25)
1
7
0°–8°
0.044 (1,12)
A
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
8
14
16
DIM
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MAX
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV5623C, TLV5623I
2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG
CONVERTERS WITH POWER DOWN
SLAS231 – JUNE 1999
MECHANICAL DATA
DGK (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
M
0,65
8
0,25
5
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–6°
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073329/B 04/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-187
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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