TLV5623CDGKG4 [TI]
8-Bit, 3 us DAC, Serial Input, Pgrmable Settling Time/ Power Consumption, Ultra Low Power 8-VSSOP 0 to 70;型号: | TLV5623CDGKG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 8-Bit, 3 us DAC, Serial Input, Pgrmable Settling Time/ Power Consumption, Ultra Low Power 8-VSSOP 0 to 70 光电二极管 转换器 |
文件: | 总23页 (文件大小:943K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SLAS231B − JUNE 1999 − REVISED APRIL 2004
D
D
8-Bit Voltage Output DAC
D
D
D
Buffered High-Impedance Reference Input
Monotonic Over Temperature
Programmable Settling Time vs Power
Consumption
Available in MSOP Package
3 µs in Fast Mode
9 µs in Slow Mode
applications
D
Ultra Low Power Consumption:
900 µW Typ in Slow Mode at 3 V
2.1 mW Typ in Fast Mode at 3 V
D
D
D
D
D
Digital Servo Control Loops
Digital Offset and Gain Adjustment
Industrial Process Control
D
D
D
Differential Nonlinearity . . . <0.2 LSB
Machine and Motion Control Devices
Mass Storage Devices
Compatible With TMS320 and SPI Serial
Ports
Power-Down Mode
D OR DGK PACKAGE
(TOP VIEW)
description
The TLV5623 is a 8-bit voltage output digital-to-
analog converter (DAC) with a flexible 4-wire
serial interface. The 4-wire serial interface allows
glueless interface to TMS320, SPI, QSPI, and
Microwire serial ports. The TLV5623 is pro-
grammed with a 16-bit serial string containing 4
control and 8 data bits. Developed for a wide
range of supply voltages, the TLV5623 can
operate from 2.7 V to 5.5 V.
DIN
SCLK
CS
V
DD
OUT
1
2
3
4
8
7
6
5
REFIN
AGND
FS
The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB
output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow
the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within
the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need
for a low source impedance drive to the terminal.
Implemented with a CMOS process, the TLV5623 is designed for single supply operation from 2.7 V to 5.5 V.
The device is available in an 8-terminal SOIC package. The TLV5623C is characterized for operation from 0°C
to 70°C. The TLV5623I is characterized for operation from −40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
†
T
A
SMALL OUTLINE
(D)
MSOP
(DGK)
0°C to 70°C
TLV5623CD
TLV5623ID
TLV5623CDGK
TLV5623IDGK
−40°C to 85°C
†
Available in tape and reel as the TLV5623CDR and the TLV5623IDR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2002 − 2004, Texas Instruments Incorporated
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1
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SLAS231B − JUNE 1999 − REVISED APRIL 2004
functional block diagram
_
6
+
REFIN
DIN
10
8
Serial Input
Register
1
8-Bit
Data
Latch
8
7
x2
OUT
2
3
4
SCLK
CS
Update
16 Cycle
Timer
FS
2
Power-On
Reset
Speed/Power-Down
Logic
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AGND
CS
5
3
1
4
7
6
2
8
Analog ground
I
I
Chip select. Digital input used to enable and disable inputs, active low.
Serial digital data input
DIN
FS
I
Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface.
OUT
REFIN
SCLK
O
I
DAC analog output
Reference analog input voltage
Serial digital clock input
Positive power supply
I
V
DD
2
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SLAS231B − JUNE 1999 − REVISED APRIL 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (V
to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V
Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . − 0.3 V to V
+ 0.3 V
+ 0.3 V
DD
DD
Operating free-air temperature range, T : TLV5623C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
TLV5623I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN NOM
MAX
5.5
UNIT
V
V
V
= 5 V
= 3 V
4.5
2.7
2
5
3
DD
Supply voltage, V
DD
3.3
V
DD
DV
DV
DV
DV
= 2.7 V
V
DD
DD
DD
DD
High-level digital input voltage, V
IH
= 5.5 V
= 2.7 V
= 5.5 V
2.4
V
0.6
1
V
Low-level digital input voltage, V
IL
V
Reference voltage, V to REFIN terminal
ref
V
V
= 5 V (see Note 1)
= 3 V (see Note 1)
AGND 2.048
AGND 1.024
V
V
−1.5
V
DD
DD
Reference voltage, V to REFIN terminal
ref
−1.5
V
DD
DD
Load resistance, R
2
10
kΩ
pF
MHz
°C
°C
L
Load capacitance, C
100
L
Clock frequency, f
20
70
85
CLK
TLV5623C
TLV5623I
0
−40
Operating free-air temperature, T
A
NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ V
DD/2
causes clipping of the transfer function.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
power supply
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
= 5 V, VREF = 2.048 V,
DD
Fast
0.9
1.35
mA
No load,
All inputs = AGND or V
DAC latch = 0x800
,
,
DD
Slow
Fast
0.4
0.7
0.6
1.1
mA
mA
I
Power supply current
DD
V
= 3 V, VREF = 1.024 V
DD
No load,
All inputs = AGND or V
DAC latch = 0x800
DD
Slow
0.3
1
0.45
mA
Power down supply current (see Figure 12)
µA
Zero scale See Note 2
−68
−68
2
PSRR
Power supply rejection ratio
dB
V
Full scale
See Note 3
Power on threshold voltage, POR
NOTES: 2. Power supply rejection ratio at zero scale is measured by varying V
and is given by:
and is given by:
DD
PSRR = 20 log [(E (V max) − E (V min))/V max]
ZS DD ZS DD DD
3. Power supply rejection ratio at full scale is measured by varying V
DD
PSRR = 20 log [(E (V max) − E (V min))/V max]
G
DD
G
DD
DD
3
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SLAS231B − JUNE 1999 − REVISED APRIL 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
static DAC specifications R = 10 kΩ, C = 100 pF
L
L
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
bits
Resolution
8
INL
Integral nonlinearity
See Note 4
0.3
0.5
0.2
10
LSB
DNL
Differential nonlinearity
See Note 5
See Note 6
See Note 7
0.07
LSB
E
E
Zero-scale error (offset error at zero scale)
Zero-scale-error temperature coefficient
mV
ZS
10
ppm/°C
ZS TC
% of
FS
voltage
E
G
Gain error
See Note 8
0.6
Gain-error temperature coefficient
See Note 9
10
ppm/°C
NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output
from the line between zero and full scale excluding the effects of zero code and full-scale errors. Tested from code 10 to code 255.
5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1
LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains
constant) as a change in the digital input code. Tested from code 10 to code 255.
6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.
6
7. Zero-scale-error temperature coefficient is given by: E
TC = [E
(T
) − E
(T
)]/V × 10 /(T
ref max
− T ).
min
ZS
ZS max
ZS min
8. Gain error is the deviation from the ideal output (2V − 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error.
ref
G
6
9. Gain temperature coefficient is given by: E TC = [E (T
) − E (T
)]/V × 10 /(T
− T ).
G
max
G
min
ref
max
min
output specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
O
Voltage output range
R
R
= 10 kΩ
0
V
DD
−0.1
V
L
L
% of FS
voltage
Output load regulation accuracy
= 2 kΩ, vs 10 kΩ
0.1
0.25
reference input (REF)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
I
Input voltage range
Input resistance
0
V
−1.5
DD
R
C
10
5
MΩ
pF
I
I
Input capacitance
Slow
Fast
525
1.3
kHz
MHz
Reference input bandwidth
Reference feed through
REFIN = 0.2 V + 1.024 V dc
pp
REFIN = 1 V at 1 kHz + 1.024 V dc
pp
(see Note 10)
−75
dB
NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000.
digital inputs
PARAMETER
High-level digital input current
Low-level digital input current
Input capacitance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
µA
I
I
V = V
DD
1
1
IH
I
V = 0 V
I
µA
IL
C
3
pF
I
4
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SLAS231B − JUNE 1999 − REVISED APRIL 2004
operating characteristics over recommended operating free-air temperature range (unless
otherwise noted)
analog output dynamic performance
PARAMETER
TEST CONDITIONS
MIN
TYP
3
MAX
5.5
UNIT
C
= 100 pF,
Fast
Slow
Fast
Slow
Fast
Slow
R
= 10 kΩ,
L
L
t
t
Output settling time, full scale
µs
s(FS)
See Note 11
9
20
C
= 100 pF,
1
µs
µs
R
= 10 kΩ,
L
L
Output settling time, code to code
Slew rate
s(CC)
See Note 12
2
3.6
0.9
10
57
49
−50
60
R
= 10 kΩ,
See Note 13
C
= 100 pF,
L
L
SR
V/µs
Glitch energy
Code transition from 0x7F0 to 0x800
nV−s
dB
S/N
Signal to noise
fs = 400 KSPS fout = 1.1 kHz,
S/(N+D) Signal to noise + distortion
dB
R
= 10 kΩ,
BW = 20 kHz
C = 100 pF,
L
L
THD
Total harmonic distortion
dB
Spurious free dynamic range
dB
NOTES: 11. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change
of 0x020 to 0xFF0 or 0xFF0 to 0x020. Not tested, ensured by design.
12. Settling time is the time for the output signal to remain within 0.5 LSB of the final measured value for a digital input code change
of one count. Not tested, ensured by design.
13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage.
digital input timing requirements
MIN NOM
MAX
UNIT
ns
t
t
Setup time, CS low before FS↓
10
8
su(CS−FS)
Setup time, FS low before first negative SCLK edge
ns
su(FS−CK)
Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising
edge of FS
t
10
ns
su(C16−FS)
su(C16−CS)
Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising
edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup
time is between the FS rising edge and CS rising edge.
t
10
ns
t
t
t
Pulse duration, SCLK high
25
25
8
ns
ns
ns
wH
Pulse duration, SCLK low
wL
Setup time, data ready before SCLK falling edge
su(D)
t
Hold time, data held valid after SCLK falling edge
Pulse duration, FS high
5
ns
ns
h(D)
t
20
wH(FS)
5
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SLAS231B − JUNE 1999 − REVISED APRIL 2004
PARAMETER MEASUREMENT INFORMATION
t
t
wH
wL
SCLK
DIN
1
2
3
4
5
15
16
t
t
su(D)
h(D)
D14
D15
D13
D12
D1
D0
t
su(FS-CK)
t
su(C16-CS)
t
su(CS-FS)
CS
FS
t
wH(FS)
t
su(C16-FS)
Figure 1. Timing Diagram
6
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SLAS231B − JUNE 1999 − REVISED APRIL 2004
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
LOAD CURRENT
LOAD CURRENT
2.004
2.002
2
4.01
3 V Slow Mode, SOURCE
3 V Fast Mode, SOURCE
V
= 3 V,
= 1 V,
V
V
ref
Full Scale
= 5 V,
= 2 V,
DD
DD
V
ref
5 V Slow Mode, SOURCE
5 V Fast Mode, SOURCE
4.005
Full Scale
4
3.995
3.99
1.998
1.996
1.994
1.992
1.990
3.985
3.98
3.975
0
0.01 0.02 0.05 0.1 0.2 0.5
Load Current − mA
1
2
0
0.02 0.04 0.1 0.2 0.4
1
2
4
Load Current − mA
Figure 2
Figure 3
OUTPUT VOLTAGE
vs
OUTPUT VOLTAGE
vs
LOAD CURRENT
LOAD CURRENT
0.2
0.35
0.3
V
= 3 V,
= 1 V,
DD
V
= 5 V,
= 2 V,
DD
0.18
V
ref
V
ref
Zero Code
Zero Code
0.16
0.14
0.12
0.1
0.25
0.2
3 V Slow Mode, SINK
5 V Slow Mode, SINK
0.15
0.08
0.06
5 V Fast Mode, SINK
3 V Fast Mode, SINK
0.1
0.05
0
0.04
0.02
0
0
0.01 0.02 0.05 0.1 0.2 0.5
Load Current − mA
1
2
0
0.02 0.04 0.1 0.2 0.4
1
2
4
Load Current − mA
Figure 4
Figure 5
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂꢃ ꢄꢅ ꢆ ꢉ
ꢅꢊ ꢋꢌꢂ ꢀꢍ ꢃ ꢊꢃ ꢌꢂ ꢁ ꢍ ꢎ ꢏ ꢍꢎ ꢐꢑ ꢒ ꢌꢓꢉ ꢀ ꢔꢉ ꢕ ꢉ ꢀꢖꢁ ꢌꢀꢍ ꢌꢖꢗꢖꢁ ꢍ ꢕ
ꢇ ꢍꢗ ꢂꢐꢑ ꢀ ꢐꢑ ꢘ ꢎ ꢉ ꢀꢙ ꢏ ꢍꢎ ꢐꢑ ꢔꢍ ꢎ ꢗ
SLAS231B − JUNE 1999 − REVISED APRIL 2004
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1
1
V
V
= 3 V,
= 1 V,
V
V
= 5 V,
= 2 V,
DD
ref
DD
ref
Full Scale
Full Scale
Fast Mode
0.8
0.8
Fast Mode
0.6
0.4
0.2
0.6
0.4
0.2
Slow Mode
Slow Mode
25 40
−55 −40 −25
0
70
85 125
−55 −40 −25
0
25 40 70
85 125
T
A
− Free-Air Temperature − C°
T
A
− Free-Air Temperature − C°
Figure 6
Figure 7
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
0
0
V
= 1 V dc + 1 V p/p Sinewave,
ref
V
= 1 V dc + 1 V p/p Sinewave,
ref
−10
Output Full Scale
−10
Output Full Scale
−20
−30
−20
−30
−−40
−−40
−50
−60
−50
−60
Fast Mode
Slow Mode
−70
−80
−70
−80
0
5
10
20
30
50
100
0
5
10
20
30
50
100
f − Frequency − kHz
f − Frequency − kHz
Figure 8
Figure 9
8
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ꢅ ꢊꢋ ꢌꢂ ꢀ ꢍ ꢃ ꢊꢃ ꢌꢂ ꢁ ꢍꢎ ꢏꢍ ꢎ ꢐꢑ ꢒ ꢌꢓꢉ ꢀ ꢔꢉ ꢕꢉ ꢀꢖꢁ ꢌꢀꢍ ꢌꢖ ꢗ ꢖꢁ ꢍꢕ
ꢇꢍ ꢗꢂꢐ ꢑꢀ ꢐꢑꢘ ꢎ ꢉꢀ ꢙ ꢏꢍ ꢎ ꢐ ꢑ ꢔ ꢍꢎ ꢗ
SLAS231B − JUNE 1999 − REVISED APRIL 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION AND NOISE
TOTAL HARMONIC DISTORTION AND NOISE
vs
vs
FREQUENCY
FREQUENCY
0
0
V
= 1 V dc + 1 V p/p Sinewave,
V
= 1 V dc + 1 V p/p Sinewave,
ref
Output Full Scale
ref
Output Full Scale
−10
−10
−20
−30
−20
−30
−−40
−−40
−50
−60
−50
−60
Fast Mode
Slow Mode
−70
−80
−70
−80
0
5
10
20
30
50
100
0
5
10
20
30
50
100
f − Frequency − kHz
f − Frequency − kHz
Figure 10
Figure 11
SUPPLY CURRENT
vs
TIME (WHEN ENTERING POWER-DOWN MODE)
900
800
700
600
500
400
300
200
100
0
0
100 200 300 400 500 600 700 800 900 1000
T − Time − ns
Figure 12
9
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ꢀ ꢁꢂ ꢃ ꢄꢅ ꢆ ꢇꢈ ꢀ ꢁꢂꢃ ꢄꢅ ꢆ ꢉ
ꢅꢊ ꢋꢌꢂ ꢀꢍ ꢃ ꢊꢃ ꢌꢂ ꢁ ꢍ ꢎ ꢏ ꢍꢎ ꢐꢑ ꢒ ꢌꢓꢉ ꢀ ꢔꢉ ꢕ ꢉ ꢀꢖꢁ ꢌꢀꢍ ꢌꢖꢗꢖꢁ ꢍ ꢕ
ꢇ
ꢍ
ꢗ
ꢂ
ꢐ
ꢑ
ꢀ
ꢐ
ꢑ
ꢘ
ꢎ
ꢉ
ꢀ
ꢙ
ꢏ
ꢍ
ꢎ
ꢐꢑ
ꢔ
ꢍ
ꢎ
ꢗ
SLAS231B − JUNE 1999 − REVISED APRIL 2004
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.10
0.08
0.06
0.04
0.02
0.00
−0.02
−0.04
−0.06
−0.08
−0.10
0
255
64
128
192
Digital Output Code
Figure 13
INTEGRAL NONLINEARITY
vs
DIGITAL OUTPUT CODE
0.5
0.4
0.3
0.2
0.1
−0.0
−0.1
−0.2
−0.3
−0.4
−0.5
0
255
64
128
192
Digital Output Code
Figure 14
10
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ꢅ ꢊꢋ ꢌꢂ ꢀ ꢍ ꢃ ꢊꢃ ꢌꢂ ꢁ ꢍꢎ ꢏꢍ ꢎ ꢐꢑ ꢒ ꢌꢓꢉ ꢀ ꢔꢉ ꢕꢉ ꢀꢖꢁ ꢌꢀꢍ ꢌꢖ ꢗ ꢖꢁ ꢍꢕ
ꢇꢍ ꢗꢂꢐ ꢑꢀ ꢐꢑꢘ ꢎ ꢉꢀ ꢙ ꢏꢍ ꢎ ꢐ ꢑ ꢔ ꢍꢎ ꢗ
SLAS231B − JUNE 1999 − REVISED APRIL 2004
APPLICATION INFORMATION
general function
The TLV5623 is an 8-bit single supply DAC based on a resistor string architecture. The device consists of a serial
interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output
buffer.
The output voltage (full scale determined by external reference) is given by:
CODE
2 REF
[V]
n
2
n−1
where REF is the reference voltage and CODE is the digital input value within the range of 0 to 2 , where
10
n = 8 (bits). The 16-bit data word, consisting of control bits and the new DAC value, is illustrated in the data format
section. A power-on reset initially resets the internal latches to a defined state (all bits zero).
serial interface
The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting
with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS
rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new
level.
The serial interface of the TLV5623 can be used in two basic modes:
D
D
Four wire (with chip select)
Three wire (without chip select)
Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of
the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows
an example with two TLV5623s connected directly to a TMS320 DSP.
TLV5623
TLV5623
CS FS DIN SCLK
CS FS DIN SCLK
TMS320
DSP
XF0
XF1
FSX
DX
CLKX
Figure 15. TMS320 Interface
11
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ꢇ ꢍꢗ ꢂꢐꢑ ꢀ ꢐꢑ ꢘ ꢎ ꢉ ꢀꢙ ꢏ ꢍꢎ ꢐꢑ ꢔꢍ ꢎ ꢗ
SLAS231B − JUNE 1999 − REVISED APRIL 2004
APPLICATION INFORMATION
serial interface (continued)
If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows
an example of how to connect the TLV5623 to a TMS320, SPI, or Microwire port using only three pins.
TMS320
DSP
TLV5623
SPI
TLV5623
Microwire
TLV5623
FSX
FS
SS
FS
I/O
FS
DIN
DIN
DIN
DX
MOSI
SCLK
SO
SK
CLKX
SCLK
CS
SCLK
CS
SCLK
CS
Figure 16. Three-Wire Interface
Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling
edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must
be performed to program the TLV5623. After the write operation(s), the DAC output is updated automatically
on the next positive clock edge following the sixteenth falling clock edge.
serial clock frequency and update rate
The maximum serial clock frequency is given by:
1
f
+
+ 20 MHz
SCLKmax
t
) t
wH(min)
wL(min)
The maximum update rate is:
1
f
+
+ 1.25 MHz
UPDATEmax
16 ǒt
Ǔ
) t
wH(min)
wL(min)
The maximum update rate is a theoretical value for the serial interface, since the settling time of the TLV5623
has to be considered also.
data format
The 16-bit data word for the TLV5623 consists of two parts:
D
D
Control bits
(D15 . . . D12)
(D11 . . . D0)
New DAC value
D15
X
D14
D13
D12
X
D11
D10
D9
D8
D7
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
SPD
PWR
New DAC value (8 bits)
X: don’t care
SPD: Speed control bit.
1 → fast mode
0 → slow mode
PWR: Power control bit. 1 → power down
0 → normal operation
In power-down mode, all amplifiers within the TLV5623 are disabled.
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ꢇꢍ ꢗꢂꢐ ꢑꢀ ꢐꢑꢘ ꢎ ꢉꢀ ꢙ ꢏꢍ ꢎ ꢐ ꢑ ꢔ ꢍꢎ ꢗ
SLAS231B − JUNE 1999 − REVISED APRIL 2004
APPLICATION INFORMATION
TLV5623 interfaced to TMS320C203 DSP
hardware interfacing
Figure 17 shows an example how to connect the TLV5623 to a TMS320C203 DSP. The serial interface of the
TLV5623 is ideally suited to this configuration, using a maximum of four wires to make the necessary
connections. In applications where only one synchronous serial peripheral is used, the interface can be
simplified even further by pulling CS low all the time as shown in the figure.
TMS320C203
TLV5623
V
DD
FS
DX
FS
DIN
SCLK
OUT
REFIN
CLKX
REF
R
LOAD
CS AGND
Figure 17. TLV5623 to DSP Interface
TLV5623 interfaced to MCS51 microcontroller
hardware interfacing
Figure 18 shows an example of how to connect the TLV5623 to an MCS51 compatible microcontroller. The
serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent
on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide
the chip select and frame sync signals for the TLV5623.
MCS51 Controller
TLV5623
V
DD
RxD
TxD
SDIN
SCLK
CS
P3.4
P3.5
FS
OUT
REFIN
REF
R
LOAD
AGND
Figure 18. TLV5623 to MCS51 Controller Interface
MCS is a registered trademark of Intel Corporation
13
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ꢇ ꢍꢗ ꢂꢐꢑ ꢀ ꢐꢑ ꢘ ꢎ ꢉ ꢀꢙ ꢏ ꢍꢎ ꢐꢑ ꢔꢍ ꢎ ꢗ
SLAS231B − JUNE 1999 − REVISED APRIL 2004
APPLICATION INFORMATION
linearity, offset, and gain error using single ended supplies
When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With
a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage
may not change with the first code, depending on the magnitude of the offset voltage.
The output amplifier attempts to drive the output to a negative voltage. However, because the most negative
supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.
The output voltage then remains at zero until the input code value produces a sufficient positive output voltage
to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19.
Output
Voltage
0 V
DAC Code
Negative
Offset
Figure 19. Effect of Negative Offset (single supply)
This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the
dotted line if the output buffer could drive below the ground rail.
For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code after offset and full
scale are adjusted out or accounted for in some way. However, single supply operation does not allow for
adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured
between full-scale code and the lowest code that produces a positive output voltage.
power-supply bypassing and ground management
Printed-circuit boards that use separate analog and digital ground planes offer the best system performance.
Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected
together at the low-impedance power-supply source. The best ground connection may be achieved by
connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground
currents are well managed and there are negligible voltage drops across the ground plane.
A 0.1-µF ceramic-capacitor bypass should be connected between V and AGND and mounted with short leads
DD
as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the
digital power supply.
Figure 20 shows the ground plane layout and bypassing technique.
Analog Ground Plane
1
2
3
4
8
7
6
5
0.1 µF
Figure 20. Power-Supply Bypassing
14
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ꢀ ꢁꢂꢃ ꢄ ꢅ ꢆ ꢇꢈ ꢀꢁꢂ ꢃꢄ ꢅꢆ ꢉ
ꢅ ꢊꢋ ꢌꢂ ꢀ ꢍ ꢃ ꢊꢃ ꢌꢂ ꢁ ꢍꢎ ꢏꢍ ꢎ ꢐꢑ ꢒ ꢌꢓꢉ ꢀ ꢔꢉ ꢕꢉ ꢀꢖꢁ ꢌꢀꢍ ꢌꢖ ꢗ ꢖꢁ ꢍꢕ
ꢇꢍ ꢗꢂꢐ ꢑꢀ ꢐꢑꢘ ꢎ ꢉꢀ ꢙ ꢏꢍ ꢎ ꢐ ꢑ ꢔ ꢍꢎ ꢗ
SLAS231B − JUNE 1999 − REVISED APRIL 2004
APPLICATION INFORMATION
definitions of specifications and terminology
integral nonlinearity (INL)
The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum
deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale
errors.
differential nonlinearity (DNL)
The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the
measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage
changes in the same direction (or remains constant) as a change in the digital input code.
zero-scale error (E
)
ZS
Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0.
gain error (E )
G
Gain error is the error in slope of the DAC transfer function.
signal-to-noise ratio + distortion (S/N+D)
S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
spurious free dynamic range (SFDR)
SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious
signal within a specified bandwidth. The value for SFDR is expressed in decibels.
total harmonic distortion (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal
and is expressed in decibels.
15
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TLV5623CD
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
TV5623
TLV5623CDG4
TLV5623CDGK
TLV5623CDGKG4
TLV5623CDGKR
TLV5623CDGKRG4
TLV5623CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
DGK
DGK
DGK
DGK
D
75
80
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
0 to 70
TV5623
ADT
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
0 to 70
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
0 to 70
ADT
2500
2500
2500
2500
75
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
0 to 70
ADT
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
0 to 70
ADT
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
TV5623
TV5623
TY5623
TY5623
ADU
TLV5623CDRG4
TLV5623ID
SOIC
D
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
D
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TLV5623IDG4
SOIC
D
75
Green (RoHS
& no Sb/Br)
TLV5623IDGK
TLV5623IDGKG4
TLV5623IDGKR
TLV5623IDGKRG4
TLV5623IDR
VSSOP
VSSOP
VSSOP
VSSOP
SOIC
DGK
DGK
DGK
DGK
D
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
80
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
ADU
2500
2500
2500
2500
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
ADU
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM
& no Sb/Br)
ADU
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TY5623
TY5623
TLV5623IDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV5623CDGKR
TLV5623IDGKR
TLV5623IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
5.3
5.3
6.4
3.4
3.4
5.2
1.4
1.4
2.1
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLV5623CDGKR
TLV5623IDGKR
TLV5623IDR
VSSOP
VSSOP
SOIC
DGK
DGK
D
8
8
8
2500
2500
2500
367.0
367.0
367.0
367.0
367.0
367.0
35.0
35.0
35.0
Pack Materials-Page 2
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