TLV5621IDRG4 [TI]

SERIAL INPUT LOADING, 75us SETTLING TIME, 8-BIT DAC, PDSO14, GREEN, PLASTIC, SOIC-14;


型号：	TLV5621IDRG4
厂家：	TEXAS INSTRUMENTS
描述：	SERIAL INPUT LOADING, 75us SETTLING TIME, 8-BIT DAC, PDSO14, GREEN, PLASTIC, SOIC-14 输入元件光电二极管转换器
文件：	总19页 (文件大小：284K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

2.7-V to 5.5-V Single-Supply Operation

Low Power Consumption

Half-Buffered Output

Power-Down Mode

Four 8-Bit Voltage Output DACs

One-Half Power 8-Bit Voltage Output DAC

Fast Serial Interface . . . 1 MHz Max

applications

Simple Two-Wire Interface In Single

Buffered Mode

Programmable Voltage Sources

Digitally-Controlled Amplifiers/Attenuators

Cordless/Wireless Communications

Automatic Test Equipment

High-Impedance Reference Inputs For Each

DAC

Programmable for 1 or 2 Times Output

Range

Portable Test Equipment

Simultaneous-Update Facility In

Double-Buffered Mode

Process Monitoring and Control

Signal Synthesis

Internal Power-On Reset

Industry Temperature Range

D PACKAGE

(TOP VIEW)

description

The TLV5621I is a quadruple 8-bit voltage output

digital-to-analog converter (DAC) with buffered

reference inputs (high impedance). The DAC

produces an output voltage that ranges between

either one or two times the reference voltages and

GND, and the DAC is monotonic. The device is

simple to use since it operates from a single

supply of 2.7 V to 5.5 V. A power-on reset function

is incorporated to provide repeatable start-up

conditions. A global hardware shut-down terminal

and the capability to shut down each individual

DAC with software are provided to minimize

power consumption.

GND

REFA

REFB

REFC

REFD

DATA

CLK

HWACT

DACA

DACB

DACC

DACD

Digital control of the TLV5621I is over a simple 3-wire serial bus that is CMOS compatible and easily interfaced

to all popular microprocessor and microcontroller devices. A TLV5621I 11-bit command word consists of

eight bits of data, two DAC select bits, and a range bit for selection between the times one or times two output

range. The TLV5621I digital inputs feature Schmitt triggers for high noise immunity. The DAC registers are

double buffered which allows a complete set of new values to be written to the device, and then under control

of the HWACT signal, all of the DAC outputs are updated simultaneously.

The 14-terminal small-outline (D) package allows digital control of analog functions in space-critical

applications. The TLV5621I does not require external trimming. The TLV5621I is characterized for operation

from –40°C to 85°C.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(D)

–40°C to 85°C

TLV5621ID

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

functional block diagram

REFA

–

DAC

–

DACA

DACB

DACC

DACD

× 2

Latch

REFB

–

REFC

REFD

–

CLK

DATA

Power-On

Reset

Serial

Interface

HWACT

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME

CLK

NO.

Serial interface clock, data enters on the negative edge

DAC A analog output

DACA

DACB

DACC

DACD

DATA

DAC B analog output

DAC C analog output

DAC D analog output

Serial-interface digital-data input

Input enable

GND

Ground return and reference

Global hardware activate

HWACT

REFA

REFB

REFC

REFD

Reference voltage input to DACA

Reference voltage input to DACB

Reference voltage input to DACC

Reference voltage input to DACD

Positive supply voltage

detailed description

The TLV5621 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with

256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected

to GND and the other end is fed from the output of the reference input buffer. Monotonicity is maintained by use

of the resistor strings. Linearity depends upon the matching of the resistor elements and upon the performance

of the output buffer. Because the inputs are buffered, the DACs always present a high-impedance load to the

reference source.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

Each DAC output is buffered by a configurable-gain output amplifier, which can be programmed to times one

or times two gain.

On power-up, the DACs are reset to CODE 0.

Each output voltage is given by:

CODE

V (DACA|B|C|D)

REF

(1 RNG bit value)

256

where CODE is in the range 0 to 255 and the range (RNG) bit is a 0 or 1 within the serial control word.

Table 1. Ideal-Output Transfer

•

OUTPUT VOLTAGE

GND

(1/256) × REF (1+RNG)

•

(127/256) × REF (1+RNG)

(128/256) × REF (1+RNG)

•

(255/256) × REF (1+RNG)

data interface

The data interface has two modes of operation; single and double buffered. Both modes serially clock in bits

of data using DATA and CLK whenever EN is high. When EN is low, CLK is disabled and data cannot be loaded

into the buffers.

In the single buffered mode, the DAC outputs are updated on the last/twelfth falling edge of CLK, so this mode

only requires a two-wire interface with EN tied high (see Figure 1 and Figure 2).

In the double buffered mode (startup default), the outputs of the DACs are updated on the falling edge of the

EN strobe (see Figure 3 and Figure 4). This allows multiple devices to share data and clock lines by having only

separate EN lines.

single-buffer mode (MODE = 1)

When a two wire interface is used, EN is tied high and the input to the device is always active; therefore, random

data can be clocked into the input latch. In order to regain word synchronization, twelve zeros are clocked in

as shown in Figure 1, and then a data or control word is clocked in. In Figure 1, the MODE bit is set to one, and

a control word is clocked in with the DAC outputs becoming active after the last falling edge of the control word.

Figure 2 shows valid data being written to a DAC, note that CLK is held low while the data is invalid. Data can

be written to all four DACs and then the control word is clocked in which sets the MODE bit to 1. At the end of

the control word, the data is latched to the inputs of the DACs.

Note that once the MODE bit has been set, it is not possible to clear it, i.e., it is not possible to move from single

to double-buffered mode.

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CLK

MODE

RNG RNG RNG RNG

DATA

DAC

SIA SIB SIC SID ACT

(Tied High)

NOTE A: Twelve zeros enable word synchronization and the output can change after the leading edge of CLK depending on the data in the latches.

Figure 1. Register Write Operation Following Noise or Undefined Levels on DATA or CLK (Single-Buffer Mode)

CLK

MODE

RNG RNG RNG RNG

DATA

DAC

SIA SIB SIC SID ACT

(Tied High)

NOTE A: EN is held high and data is written to a DAC register. The data is latched to the output of the DAC on the falling edge of the last CLK of the control word, where the

mode is set.

Figure 2. First Nonzero Write Operation After Startup (EN = High)

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

double-buffered mode (MODE = 0)

In this mode, data is only latched to the output of the DACs on the falling edge of the EN strobe. Therefore, all

four DACs can be written to before updating their outputs.

Any number of input data blocks can be written with all having the same length. Subsequent data blocks simply

overwrite previous ones with the same address until EN goes low.

Multiple data blocks can be written in any sequence provided signal timing limits are met. The negative going

edge of EN terminates and latches all data.

Multiple Random Sequence Data Blocks

DATA

Data Latched Into DAC Control Registers and Control Word

Figure 3. Data and Control Serial Control

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CLK

RNG RNG RNG RNG

MODE

SIA SIB SIC SID ACT

DATA

DAC

NOTE A: Data is written to the output of a DAC, and the data is latched to the output on the falling edge of EN. A control word then selects double-buffered mode. When the

range is changed, the output changes on the falling edge of EN.

Figure 4. First Nonzero Write Operation After Startup

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

control register

The control register contains ten active bits. Four bits are range select bits as on the TLC5620. The register also

contains a software shutdown bit (ACT) and four shutdown inhibit bits (SIA, SIB, SIC, SID). The shutdown inhibit

bits act on each DAC (DACA through DACD). The mode select bit is used to change between single and double

buffered modes. The bits in the control register are listed in Table 2.

Table 2. Control Register Bits

BIT

MODE

RNG A

RNG B

RNG C

RNG D

SIA

FUNCTION

Selection bit for type of interface (see data interface section)

Range select bit for DACA, 0 = 1, 1 =

Range select bit for DACB, 0 = 1, 1 =

Range select bit for DACC, 0 = 1, 1 =

Range select bit for DACD, 0 = 1, 1 =

Shutdown inhibit bit for DACA

SIB

Shutdown inhibit bit for DACB

SIC

Shutdown inhibit bit for DACC

SID

Shutdown inhibit bit for DACD

ACT

Software shutdown bit

The SIx bits inhibit the actions of the shutdown bits as shown in Table 3. When the ACT bit is 1 or the HWACT

signal is high (active), the inhibit bits act as enable bits in inverse logic terms. The ACT software shutdown bit

and HWACT (asynchronously acting hardware terminal) are logically ORed together.

This configuration allows any combination of DACs to be shut down to save power.

Table 3. Shutdown Inhibit Bits and HWACT Signal

SIx

ACT

HWACT

DACx STATUS

Shutdown (see Note 1)

Shutdown

Active (see Note 1)

Active

NOTE 1: Sense of HWACT terminal and ACT bit were changed from early

versions of this specification.

The values of the input address select bits, A0 and A1, and the updated DAC are listed in Table 4.

Table 4. Serial Input Decode

INPUT ADDRESS SELECT BITS

DAC UPDATED

DACA

DACB

DACC

DACD

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TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

power-on reset

Power-on reset circuitry is available on the TLV5621I. The threshold to trigger a power-on reset is 1.95 V typical

(1.4 V min and 2.5 V max). For a power-on reset, all DACs are shut down. The control register bit values and

states after a power-on reset are listed in Table 5.

Table 5. Control Register Bit Values and States After Power-On Reset

BIT

MODE

RNG A

RNG B

RNG C

RNG D

SIA

VALUE

STATE AFTER POWER-ON RESET

Double buffer mode selected

Range

Shutdown affects DACA according to ACT state

Shutdown affects DACB according to ACT state

Shutdown affects DACC according to ACT state

Shutdown affects DACD according to ACT state

DACs in shutdown state

SIB

SIC

SID

ACT

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TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

linearity, offset, and gain error using single-end supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset, the output voltage changes on the first code change. With a negative offset the output voltage

may not change with the first code depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative

supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage

to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.

Output

Voltage

0 V

DAC Code

Negative

Offset

Figure 5. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the

dotted line if the output buffer could drive below the ground rail.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after

offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not

allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity

is measured between full-scale code and the lowest code that produces a positive output voltage. The code is

calculated from the maximum specification for the negative offset.

equivalent inputs and outputs

INPUT CIRCUIT

OUTPUT CIRCUIT

Input from

Decoded DAC

DAC

Voltage Output

ref

Input

× 1

84 kΩ

Output

Range

Select

To DAC

Resistor

String

× 2

SINK

60 µA

Typical

84 kΩ

GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage (V

– GND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V

Reference input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND – 0.3 V to V

Operating free-air temperature range, T

Storage temperature range, T

+ 0.3 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

NOM

MAX

UNIT

Supply voltage, V

(see Note 2)

2.7

3.3

5.5

High-level digital input voltage, V

0.8 V

Low-level digital input voltage, V

0.2 V

Reference voltage, V [A|B|C|D], x1 gain

GND

–1.5

ref

Load resistance, R

kΩ

Setup time, data input, t

su(DATA-CLK)

Hold time, data input valid after CLK↓, t

(see Figure 6)

h(DATA-CLK)

(see Figure 7)

Setup time, CLK↓ to EN↓, t

Setup time, EN↑ to CLK↓, t

100

su(CLK-EN)

su(EN-CLK)

(see Figure 7) (see Note 3)

Pulse duration, EN low, t

(see Figure 7) (see Note 3)

200

400

w(EN)

Pulse duration, CLK high, t

CLK frequency

(see Figure 6) (see Note 3)

w(CLK)

MHz

°C

Operating free-air temperature, T

–40

NOTES: 2. The device operates over the supply voltage range of 2.7 V to 5.5 V. Over this voltage range the device responds correctly to data

input by changing the output voltage but conversion accuracy is not specified over this extended range.

3. This is specified by design but is not production tested.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

electrical characteristics over recommended operating free-air temperature range,

= 3 V to 3.6 V, V = 1.25 V, GND = 0 V, R = 10 kΩ, C = 100 pF, × 1 gain output range

ref L L

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Maximum full-scale output

voltage

max

ref

= 1.5 V, open circuit output, × 2 gain

V – 100

High-level digital input current

Low-level digital input current

Output sink current, DACA

V = V

±10

µA

IH(digital)

V = 0 V

IL(digital)

DAC code 0

Output sink current, DACB,

DACC, DACD

O(sink)

DAC code 0

µA

Output source current

Input capacitance

Each DAC output, DAC code 255

O(source)

Reference input capacitance

A, B, C, D inputs

= 3.6 V

= 5 V

1.5

Supply current

Supply current, one low power

DAC active

= 3.6 V, See Note 4

150

250

100

µA

DD(active)

Supply current, all DACs shut

down

DD(shutdown)

Reference input current

Integral linearity error

Differential linearity error

Zero-scale error

A, B, C, D inputs

±10

±1

µA

LSB

ref

= 1.25 V, × 2 gain, See Notes 5 and 13

= 1.25 V, × 2 gain, See Notes 6 and 13

= 1.25 V, × 2 gain, See Note 7

ref

±0.1

±0.9

Zero-scale error temperature

coefficient

= 1.25 V, × 2 gain, See Note 8

µV/°C

ref

Zero-scale error supply rejection

Full-scale error

mV/V

ref

= 1.25 V, × 2 gain, See Note 9

= 1.25 V, × 2 gain, See Note 10

±60

Full-scale error temperature

coefficient

ref

±25

µV/°C

Full-scale error supply rejection

Power-supply sensitivity

mV/V

PSRR

See Notes 11 and 12

0.5

Feedback resistor network

resistance

168

kΩ

NOTES: 4. This is measured with no load (open circuit output), V = 1.25 V, range = × 2.

ref

5. Integral nonlinearity (INL) is the maximum deviation of the output from the line between zero and full scale (excluding the effects

of zero code and full-scale errors).

6. Differentialnonlinearity (DNL) is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes.

Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code.

7. Zero-scale error is the deviation from zero voltage output when the digital input code is zero.

8. Zero-scale error temperature coefficient is given by: ZSETC = [ZSE(T

) – ZSE(T

)]/V × 10 /(T

– T

min

max

min ref max

9. Full-scale error is the deviation from the ideal full-scale output (V – 1 LSB) with an output load of 10 kΩ.

ref

10. Full-scale temperature coefficient is given by: FSETC = [FSE(T

max

) – FSE (T

)]/V × 10 /(T

ref max

voltage from 4.5 V to 5.5 V dc and measuring the effect

– T

min

11. Zero-scale error rejection ratio (ZSE-RR) is measured by varying the V

of this signal on the zero-code output voltage.

12. Full-scale error rejection ratio (FSE-RR) is measured by varing the V

this signal on the full-scale output voltage.

voltage from 3 V to 3.6 V dc and measuring the effect of

13. Linearity is only specified for DAC codes 1 through 255.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

operating characteristics over recommended operating free-air temperature range,

= 3 V to 3.6 V, V = 1.25 V, GND = 0 V, R = 10 kΩ, C = 100 pF, × 1 gain output range

ref L L

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

0.8

0.5

MAX

UNIT

V/µs

µs

Output slew rate, rising (DACA)

Output slew rate, falling (DACA)

Output slew rate (DACB, DACC, DACD)

Output settling time, rising (DACA)

Output settling time, falling (DACA)

To 1/2 LSB,

= 3 V

µs

Output settling time, rising (DACB, DACC,

DACD)

To 1/2 LSB,

= 3 V

µs

Output settling time, falling (DACB, DACC,

DACD)

Output settling time, HWACT or ACT↑ to

output volts (DACA) (see Note 14)

†

120

Output settling time, HWACT or ACT↑ to

output volts (DACB, DACC, DACD)

(see Note 14)

To 1/2 LSB,

= 3 V

µs

Large-signal bandwidth

Digital crosstalk

Measured at –3 dB point

100

–50

–60

kHz

CLK = 1-MHz square wave measured at DACA–DACD

A, B, C, D inputs, See Note 15

Reference feedthrough

Channel-to-channel isolation

A, B, C, D inputs, See Note 16

Channel-to-channel isolation when in

shutdown

A, B, C, D inputs

–40

Reference bandwidth (DACA)

See Note 17

kHz

Reference bandwidth (DACB, DACC, DACD) See Note 17

100

†

This is specified by characterization but is not production tested.

NOTES: 14. The ACT bit is latched on EN↓.

15. Reference feedthrough is measured at any DAC output with an input code = 00 hex with a V input = 1 V dc + 1 V

16. Channel-to-channel isolation is measured by setting the input code of one DAC to FF hex and the code of all other DACs to 00 hex

at 10 kHz.

ref

with V input = 1 V dc + 1 V

ref PP

at 10 kHz.

17. Reference bandwidth is the –3 dB bandwidth with an ideal input at V = 1.25 V dc + 2 V

and with a digital input code of full-scale

ref PP

(range set to × 1 and V

= 5 V).

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TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

PARAMETER MEASUREMENT INFORMATION

w(CLK)

50%

CLK

h(DATA-CLK)

su(DATA-CLK)

DATA

Figure 6. Timing of DATA Relative to CLK

50%

w(EN)

su(EN-CLK)

su(CLK-EN)

50%

CLK

DATA

Figure 7. Timing of CLK Relative to EN

TLV5621

DACA

DACB

DACC

10 kΩ

= 100 pF

DACD

Figure 8. Slewing Settling Time and Linearity Measurements

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TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

TYPICAL CHARACTERISTICS

POSITIVE RISE TIME AND SETTLING TIME

NEGATIVE FALL TIME AND SETTLING TIME

2.5

= 3 V

= 25°C

Code FF to

00 Hex

Range = ×2

1.5

ref

= 1.25 V

= 3 V

= 25°C

(see Notes

A and B)

0.5

Code 00 to

FF Hex

Range = ×2

ref

= 1.25 V

(see Notes

A and B)

–0.5

–1

10 12 14 16 18 20

t – Time – µs

NOTES: A. Fall time = 4.25 µs, negative slew rate = 0.46 V/µs,

settling time = 8.5 µs.

NOTES: A. Rise time = 2.05 µs, positive slew rate = 0.96 V/µs,

settling time = 4.5 µs.

B. For DACB, DACC, and DACD

Figure 9

Figure 10

DAC OUTPUT VOLTAGE

LOAD RESISTANCE

1.6

2.8

2.6

2.4

2.2

1.4

1.2

0.8

0.6

1.8

1.6

= 3 V

= 1.5 V

= 3 V

= 1.5 V

0.4

ref

1.4

1.2

Range = ×1

Range = ×2

(see Note A)

0.2

(see Note A)

10 20 30 40 50 60 70 80 90 100

– Load Resistance – kΩ

NOTE A: For DACB, DACC, and DACD

Figure 11

Figure 12

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TLV5621I

LOW-POWER QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTER

SLAS138B – APRIL 1996 – REVISED FEBRUARY 1997

TYPICAL CHARACTERISTICS

SUPPLY CURRENT

FREE-AIR TEMPERATURE

1.2

Range = ×2

Input Code = 255

1.15

= 3 V

= 1.25 V

ref

1.1

1.05

0.95

0.9

0.85

0.8

–50

100

– Free-Air Temperature – °C

Figure 13

APPLICATION INFORMATION

TLV5621

DACA

DACB

DACC

DACD

NOTE A: Resistor R

10 kΩ

Figure 14. Output Buffering Scheme

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

PACKAGING INFORMATION

Orderable Device

TLV5621ED

Status Package Type Package Pins Package

Eco Plan

Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 85

Device Marking

Samples

Drawing

Qty

(1)

(2)

(6)

(3)

(4/5)

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TLV5621E

TLV5621ID

ACTIVE

Green (RoHS

& no Sb/Br)

-40 to 85

TLV5621I

TLV5621IDG4

TLV5621IDR

Green (RoHS

& no Sb/Br)

-40 to 85

2500

Green (RoHS

& no Sb/Br)

-40 to 85

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

⁽⁶⁾Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

10-Jun-2014

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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TLV5621IDRG4 [TI]

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