TISP6NTP2AD [TI]
TELECOM, SURGE PROTECTION CIRCUIT, PLASTIC, DO08, 8 PIN;
| 型号： | TISP6NTP2AD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TELECOM, SURGE PROTECTION CIRCUIT, PLASTIC, DO08, 8 PIN 电信 电信集成电路 |
| 文件： | 总10页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
INDIVIDUAL PROGRAMMABLE OVERVOLTAGE PROTECTION FOR TWO SLICS
●
●
Independent Overvoltage Protection for Two
SLICs in Short Loop Applications:
D PACKAGE
(TOP VIEW)
- Wide 0 to -90 V Programming Range
- Low 5 mA max. Gate Triggering Current
- High 150 mA min. (85 °C) Holding Current
- Specified 1.2/50 & 0.5/700 Limiting Voltage
- Full -40 °C to 85 °C Temperature Range
1
2
3
4
8
7
6
5
K2
A
K1
G1,G2
G3,G4
K3
A
K4
MDRXAK
Rated for Common Impulse Waveforms
device symbol
VOLTAGE
IMPULSE FORM
10/1000 µs
10/700 µs
CURRENT
IMPULSE SHAPE
10/1000 µs
5/310 µs
I
TSP
A
K1
20
25
60
85
1.2/50 µs
8/20 µs
G1,G2
2/10 µs
2/10 µs
●
Small Outline Surface Mount Package
- Available Ordering Options
K2
A
CARRIER
ORDER #
Tube
TISP6NTP2AD
A
Taped and reeled TISP6NTP2ADR
K3
description
The TISPNTP2A has been designed for short
loop systems such as:
- WILL (Wireless In the Local Loop)
- FITL (Fibre In The Loop)
G3,G4
- DAML (Digital Added Main Line, Pair Gain)
- SOHO (Small Office Home Office)
- ISDN-TA (Integrated Services Digital Network -
Terminal Adaptors)
SDRXAI
K4
typical TISP6NTP2A router application
These systems often have the need to source
two POTS (Plain Old Telephone Service) lines,
one for a telephone and the other for a facsimile
machine. In a single surface mount package, the
TISPNTP2A protects the two POTS line SLICs
(Subscriber Line Interface Circuits) against
overvoltages caused by lightning, a.c. power
contact and induction.
TERMINAL ADAPTOR
SLIC 1
POTS 1
POTS 2
TISP6
PROCESSOR
NTP2A
SLIC 2
The TISP6NTP2A has an array of four buffered
P-gate forward conducting thyristors with twin
TRANSCEIVER
TRANSCEIVER
LAN
LINE
commoned gates and
a
common anode
connection. Each thyristor cathode has
a
separate terminal connection. An antiparallel anode-cathode diode is connected across each thyristor. The
buffer transistors reduce the gate supply current.
Copyright © 1998 Texas Instruments Incorporated
PRODUCTION DATA information is current as of
publication date. Products conform to specifications
per the terms of Texas Instruments standard warranty.
Production processing does not necessary include
testing of all parameters.
Designed and manufactured by Power
Innovations, Bedford, UK. under private
label for Texas Instruments.
1
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
In use, the cathodes of an TISP6NTP2A thyristors are connected to the four conductors of two POTS lines
(see applications information). Each gate is connected to the appropriate negative voltage battery feed of the
SLIC driving that line pair. By having separate gates, each SLIC can be protected at a voltage level related to
the negative supply voltage of that individual SLIC. The anode of the TISP6NTP2A is connected to the SLIC
common.
Positive overvoltages are clipped to common by forward conduction of the TISP6NTP2A antiparallel diode.
Negative overvoltages are initially clipped close to the SLIC negative supply by emitter follower action of the
TISP6NTP2A buffer transistor. If sufficient clipping current flows the TISP6NTP2A thyristor will regenerate
and switch into a low voltage on-state condition. As the overvoltage subsides the high holding current of the
TISP6NTP2A prevents d.c. latchup.
absolute maximum ratings
RATING
Repetitive peak off-state voltage, I = 0, -40 °C ≤ T ≤ 85 °C
SYMBOL
VALUE
-100
UNIT
V
V
DRM
G
J
Repetitive peak gate-cathode voltage, V = 0, -40 °C ≤ T ≤ 85 °C
V
GKRM
-90
V
KA
J
Non-repetitive peak on-state pulse current, -40 °C ≤ T ≤ 85 °C, (see Notes 1 and 2)
J
10/1000 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4)
20
0.2/310 µs (I3124, open-circuit voltage wave shape 0.5/700 µs)
25
25
60
I
A
A
TSP
5/310 µs (ITU-T K20 & K21, open-circuit voltage wave shape 10/700 µs)
8/20 µs (IEC 61000-4-5:1995, open-circuit voltage wave shape 1.2/50 µs)
2/10 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4)
85
Non-repetitive peak on-state current, 50/60 Hz, -40 °C ≤ T ≤ 85 °C, (see Notes 1 and 2)
J
100 ms
7
1 s
2.7
1.5
I
TSM
5 s
300 s
900 s
0.45
0.43
Non-repetitive peak gate current, 1/2 µs pulse, cathodes commoned (see Note 1)
Operating free-air temperature range
I
25
A
GSM
T
-40 to +85
-40 to +150
-65 to +150
°C
°C
°C
A
Junction temperature
T
J
Storage temperature range
T
stg
NOTES: 1. Initially the protector must be in thermal equilibrium with -40 °C ≤ T ≤ 85 °C. The surge may be repeated after the device returns to
J
its initial conditions.
2. These non-repetitive rated currents are peak values for either polarirty. The rated current values may be applied to any cathode-
anode terminal pair. Additionally, all cathode-anode terminal pairs may have their rated current values applied simultaneously (in
this case the anode terminal current will be four times the rated current value of an individual terminal pair). Above 85 °C, derate
linearly to zero at 150 °C lead temperature.
recommended operating conditions
MIN
TYP
MAX
UNIT
C
Gate decoupling capacitor
100
220
nF
G
Series resistor for GR-1089-CORE first-level surge survival
Series resistor for ITU-T recommendation K20
40
12
20
4
R1, R2
Ω
Series resistor for ITU-T recommendation K21
Series resistor for IEC 61000-4-5:1995, class 5, 1.2/50 or 10/700
2
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
electrical characteristics for any section, T
= 25 °C (unless otherwise noted)
amb
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
-5
UNIT
µA
T = 25 °C
J
I
Off-state current
V
= V
, I = 0
D
D
DRM G
T = 85 °C
-50
-70
µA
J
I
= -20 A, IEC 61000-4-5:1995 combination impulse generator,
T
V
Breakover voltage
V
= -50 V
V
(BO)
GG
I
I
= -18 A, I3124 impulse generator, V
= -18 A, I3124 impulse generator, V
= -50 V
-70
2
T
T
GG
t
Breakdown time
Forward voltage
< -50 V
µs
V
(BR)
(BR)
I
I
= 0.6 A, t = 500 µs, V
= -50 V
= -50 V
3
5
F
F
w
GG
V
F
= 18 A, t = 500 µs, V
w
GG
I
= 20 A, IEC 61000-4-5:1995 combination impulse generator,
15
F
Peak forward recovery
voltage
V
V
= -50 V
V
FRM
GG
I
I
= 18 A, I3124 impulse generator, V = -50 V
GG
15
F
F
= 18 A, I3124 impulse generator,
V
V
> 10 V
> 5 V
2
4
F
t
I
I
Forward recovery time
Holding current
µs
FR
V
= -50 V
GG
F
I
= -1 A, di/dt = 1A/ms, V
= -50 V, T = 85 °C
-150
mA
µA
µA
H
T
GG
J
T = 25 °C
-5
J
Gate reverse current
V
= V
, V = 0
GKS
GG
GKRM AK
T = 85 °C
-50
J
Gate reverse current,
on state
I
I
I
= -0.6 A, t = 500 µs, V = -50 V
-1
mA
mA
GAT
T
F
w
GG
Gate reverse current,
forward conducting
state
-40
I
I
= 0.6 A, t = 500 µs, V
= -50 V
GAF
w
GG
Gate trigger current
Gate trigger voltage
I
I
= -5 A, t
= -5 A, t
≥ 20 µs, V
≥ 20 µs, V
= -50 V
= -50 V
5
2.5
100
60
mA
V
GT
T
T
p(g)
p(g)
GG
V
GT
GG
V
V
= -3 V
pF
pF
Anode-cathode off-
state capacitance
D
C
f = 1 MHz, V = 1 V, I = 0, (see Note 3)
d G
AK
= -50 V
D
NOTE 3: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured
device terminals are a.c. connected to the guard terminal of the bridge.
thermal characteristics
PARAMETER
MIN
TYP
MAX
UNIT
TEST CONDITIONS
2
R
Junction to free air thermal resistance
P
= 0.52 W, T = 85°C, 5 cm , FR4 PCB
160
°C/W
θJA
tot
A
3
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
PRINCIPAL TERMINAL V-I CHARACTERISTIC
GATE TRANSFER
CHARACTERISTIC
+i
+iK
Quadrant I
IFSP (= |ITSP|)
Forward
Conduction
Characteristic
IFSM (= |ITSM|)
IF
IF
VF
VGK(BO)
IGT
VGG
VD
+v
-iG
+iG
-v
ID
IGAF
I(BO)
IH
IS
VT
IGAT
VS
V(BO)
IT
IT
ITSM
IG
Quadrant III
Switching
IK
ITSP
Characteristic
-i
-iK
PM6XAIA
Figure 1. PRINCIPAL TERMINAL AND GATE TRANSFER CHARACTERISTICS
APPLICATIONS INFORMATION
operation of gated protectors
2 and 3 show how the TISP6NTP2A limits overvoltages. The TISP6NTP2A thyristor sections limit negative
overvoltages and the diode sections limit positive overvoltages.
Negative overvoltages ( 2) are initially clipped close to the SLIC negative supply rail value (VBAT) by the
conduction of the transistor base-emitter and the thyristor gate-cathode junctions. If sufficient current is
available from the overvoltage, then the thyristor will crowbar into a low voltage ground referenced on-state
condition. As the overvoltage subsides the high holding current of the crowbar thyristor prevents d.c. latchup.
The common gate of each thyristor pair is connected the appropriate SLIC battery feed voltage (VBAT1 or
VBAT2).
The negative protection voltage, V(BO), will be the sum of the gate supply (VBAT) and the peak gate(terminal)-
cathode voltage (VGT). Under a.c. overvoltage conditions VGT will be less than 2.5 V. The integrated transistor
buffer in the TISP6NTP2A greatly reduces protectors source and sink current loading on the VBAT supply.
Without the transistor, the thyristor gate current would charge the VBAT supply. An electronic power supply is
not usually designed to be charged like a battery. As a result, the electronic supply would switch off and the
thyristor gate current would provide the SLIC supply current. Normally the SLIC current would be less than
4
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
SLIC
PROTECTOR
SLIC
PROTECTOR
R1A
R1B
R2A
R2B
R1A
R1B
R2A
R2B
SLIC 1
SLIC 1
VBAT1
VBAT1
0 V
0 V
C1
100 nF
C1
100 nF
TISP6NTP2A
TISP6NTP2A
SLIC 2
SLIC 2
IK
IF
IG
IG
VBAT2
VBAT2
0 V
0 V
C2
100 nF
C2
100 nF
AI6XBN
AI6XBO
Figure 2. NEGATIVE OVERVOLTAGE CONDITION
Figure 3. POSITIVE OVERVOLTAGE CONDITION
the gate current, which would cause the supply voltage to increase and destroy the SLIC by a supply
overvoltage. The integrated transistor buffer removes this problem.
Fast rising impulses will cause short term overshoots in gate-cathode voltage. The negative protection
voltage under impulse conditions will also be increased if there is a long connection between the gate
decoupling capacitor and the gate terminal. During the initial rise of a fast impulse, the gate current (IG) is the
same as the cathode current (IK). Rates of 60 A/µs can cause inductive voltages of 0.6 V in 2.5 cm of printed
wiring track. To minimise this inductive voltage increase of protection voltage, the length of the capacitor to
gate terminal tracking should be minimised.
Positive overvoltages ( 3) are clipped to ground by forward conduction of the diode section in the
TISP6NTP2A. Fast rising impulses will cause short term overshoots in forward voltage (VFRM).
central office application to Bellcore GR-1089-CORE issue 1
The most stressful impulse for first-level surge testing (section 4.5.7) is the 1000 V, 10/1000 impulse. To limit
the circuit current to the TISP6NTP2A rating of 20 A requires the total circuit resistance to be 1000/20 = 50 Ω.
Subtracting the generator fictive source impedance of 10 Ω gives 40 Ω as the required series resistor value
for the TISP6NTP2A (R1A, R1B, R2A and R2B). The various first level impulse current levels are shown in
table 1. The maximum 1.2/50 and 2/10 current levels of 56 A are below the TISP6NTP2A ratings of 60 A and
85 A. In table 1 the designation 2x20 means that each conductor has a simultaneous peak current of 20 A
and 2x20 = 40 A flows in the anode (ground) connection.
5
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
table 1. first-level surge currents
OPEN-CIRCUIT
VOLTAGE
V
SHORT-CIRCUIT
CURRENT
A
GENERATOR
RESISTANCE
Ω
TOTAL SERIES
RESISTANCE
Ω
IT
A
WAVE
SHAPE
WIRES
TESTED
2/10
2500
2500
500
500
5
BOTH
SINGLE
BOTH
22.5
45
2x56
56
1.2/50
8/20
2 + 3/wire
28.5
50
2x53
20
10/1000
1000
100
10
SINGLE
BOTH
25
2x20
central office application to ITU-T recommendation K.20
The test level of 1000 V 10/700 delivers a peak short-circuit current level of 25 A, which is equal to the
TISPNTP2A rated value. A series resistor (R1A, R1B, R2A and R2B) is required to ensure coordinated
operation with the primary protector at the 4000 V test level. The resistor value will be set by the sparkover
voltage of the primary protector. A sparkover voltage of 300 V will give a 300/25 = 12 Ω series resistor.
local subscribers line equipment to ITU-T recommendation K.21
The test level of 1500 V 10/700 delivers a peak short-circuit current level of 37.5 A. To limit the circuit current
to the TISP6NTP2A rating of 25 A requires the total circuit resistance to be 1500/25 = 60 Ω. Subtracting the
generator fictive source impedance of 40 Ω gives 20 Ω as the required series resistor value for the
TISPNTP2A. Even at the 1500 V test level this resistor develops 25x20 = 500 V, which should ensure the
coordination with the primary protector sparkover.
indoor POTS lines to ITU-T recommendation K.21. K.22 and IEC 61000-4-5: 1995
Internal POTS lines from WILL and ISDN-TA equipment are in a relatively unexposed environment. If these
lines are galvanically isolated (floating), the return path for any induced surges can only be through
equipment capacitance or insulation breakdown.
The most stressful condition would be when the POTs lines are not galvanically isolated. Such a case is when
an ISDN-TA has a common connection between the incoming ISDN line and the internal POTs lines. The
ISDN line is likely to be ground referenced and may have primary protection at the subscriber connection. If
the primary protection operates, it provides a direct return to ground.
ITU-T recommendation K22 for a floating 4-conductor T/S bus uses a 1 kV 1.2/50 or 2/10 impulse,
capacitively coupled via 8 nF to the bus conductors. Very little circulating current is likely to flow during K22
testing. If the T/S bus has a ground return then the testing changes to ITU-T recommendation K21. The
required series resistor values for K21 and the TISP6NTP2A have been calculated earlier.
In IEC 61000-4-5: 1995 the highest specified test level is class 5. For unshielded symmetrically operated
lines, class 5 testing uses a 4000 V combination wave (1.2/50, 8/20) generator to apply a simultaneous
impulse to all conductors. For the four conductors of the two POTs lines, the currents are equalised by the use
of specified 160 Ω feed resistors. As the generator fictive source impedance is 2 Ω the peak current in each
conductor is 4000/(2x4 + 160) = 24 A. This is less than the 60 A TISP6NTP2A rating.
If the lines are long and exit the building, testing is done with a 10/700 generator. In this case the feed
resistors are 100 Ω. and the fictive impedance is 15 Ω. The peak current in each conductor will be 4000/(15x4
+ 100) = 25 A. This value is the same as the TISP6NTP2A rating.
6
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
As the equipment connected to the POTs line may have uncoordinated protection, it is desirable to provided
the ring-tip pair current sharing to the TISP6NTP2A by series resistors (R1A, R1B, R2A and R2B). A value of
4 Ω should be sufficient to ensure sharing.
7
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
MECHANICAL DATA
D008
plastic small-outline package
This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions. Leads require no additional
cleaning or processing when used in soldered assembly.
D008
Designation per JEDEC Std 30:
PDSO-G8
5,00 (0.197)
4,80 (0.189)
8
7
6
5
6,20 (0.244)
5,80 (0.228)
4,00 (0.157)
3,81 (0.150)
1
2
3
4
7° NOM
3 Places
1,75 (0.069)
1,35 (0.053)
5,21 (0.205)
4,60 (0.181)
0,50 (0.020)
0,25 (0.010)
x 45°NOM
0,203 (0.008)
0,102 (0.004)
7° NOM
4 Places
0,51 (0.020)
0,36 (0.014)
8 Places
4° ± 4°
0,79 (0.031)
0,28 (0.011)
Pin Spacing
1,27 (0.050)
(see Note A)
6 Places
0,229 (0.0090)
0,190 (0.0075)
1,12 (0.044)
0,51 (0.020)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
MDXXAA
NOTES: A. Leads are within 0,25 (0.010) radius of true position at maximum material condition.
B. Body dimensions do not include mold flash or protrusion.
C. Mold flash or protrusion shall not exceed 0,15 (0.006).
D. Lead tips to be planar within ±0,051 (0.002).
8
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
MECHANICAL DATA
D008
tape dimensions
D008 Package (8 pin SOIC) Single-Sprocket Tape
4,10
3,90
1,60
1,50
8,05
7,95
2,05
0,40
1,95
0,8 MIN.
5,55
5,45
12,30
11,70
Cover
Tape
6,50
6,30
ø 1,5 MIN.
0 MIN.
Carrier Tape
Embossment
2,2
2,0
Direction of Feed
ALL LINEAR DIMENSIONS IN MILLIMETERS
NOTES: A. Taped devices are supplied on a reel of the following dimensions:-
MDXXAT
Reel diameter:
Reel hub diameter:
Reel axial hole:
330 +0,0/-4,0 mm
100 ±2,0 mm
13,0 ±0,2 mm
B. 2500 devices are on a reel.
9
TISP6NTP2A
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED OCTOBER 1998
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or ser-
vice without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders,
that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems neces-
sary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those man-
dated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or
environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE
FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such
applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be
directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be
provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents
or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1998, Texas Instruments Incorporated
10
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