TISP6NTP2BDR [TI]
TELECOM, SURGE PROTECTION CIRCUIT, PDSO8, PLASTIC, SO-8;
| 型号： | TISP6NTP2BDR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | TELECOM, SURGE PROTECTION CIRCUIT, PDSO8, PLASTIC, SO-8 电信 光电二极管 电信集成电路 |
| 文件： | 总9页 (文件大小：242K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TISP6NTP2B
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED MAY 1999
PROGRAMMABLE OVERVOLTAGE PROTECTION FOR ISDN DC FEEDS
●
●
Overvoltage Protection for ISDN DC Feeds:
- Supply Voltages Down to -120 V
- Low 5 mA max. Gate Triggering Current
- High 150 mA min. (25 °C) Holding Current
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
K2
A
K1
G1,G2
G3,G4
K3
Rated for Common Impulse Waveforms
A
K4
VOLTAGE
IMPULSE FORM
10/1000 µs
10/700 µs
CURRENT
IMPULSE SHAPE
10/1000 µs
5/310 µs
I
TSP
MDRXAK
A
20
25
60
70
device symbol
1.2/50 µs
8/20 µs
K1
2/10 µs
2/10 µs
●
Small Outline Surface Mount Package
- Available Ordering Options
G1,G2
CARRIER
ORDER #
Tube
TISP6NTP2BD
Taped and reeled TISP6NTP2BDR
K2
A
description
A
The TISP6NTP2B has an array of four buffered
P-gate forward conducting thyristors with twin
K3
commoned gates and
a
common anode
connection. Each thyristor cathode has a
separate terminal connection. An antiparallel
anode-cathode diode is connected across each
thyristor. The buffer transistors reduce the gate
supply current.
G3,G4
SDRXAI
K4
In use, the cathodes of an TISP6NTP2B
thyristors are connected to the four conductors to
be protected (see Figure 2 and Figure 3). Each gate is connected to the appropriate negative voltage feed.
The anode of the TISP6NTP2B is connected to the system common. The TISP6NTP2B is in an 8-pin small-
outline surface mount package.
Positive overvoltages are clipped to common by forward conduction of the TISP6NTP2B antiparallel diode. In
Figure 2, a negative overvoltage draws a current through the 6.8 Ω resistor and the voltage developed
triggers the thyristor on. In Figure 3, negative overvoltages are initially clipped close to the negative supply by
emitter follower action of the TISP6NTP2B buffer transistor. If sufficient clipping current flows, the
TISP6NTP2B thyristor will regenerate and switch into a low voltage on-state condition. As the negative
overvoltage subsides, the high holding current of the TISP6NTP2B prevents d.c. latchup.
Copyright © 1998 Texas Instruments Incorporated
PRODUCTION DATA information is current as of
publication date. Products conform to specifications
per the terms of Texas Instruments standard warranty.
Production processing does not necessary include
testing of all parameters.
Designed and manufactured by Power
Innovations, Bedford, UK. under private
label for Texas Instruments.
1
TISP6NTP2B
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED MAY 1999
absolute maximum ratings at T
= 25 °C (unless otherwise noted)
amb
RATING
SYMBOL
VALUE
-130
UNIT
V
Repetitive peak off-state voltage, I = 0
V
DRM
G
Repetitive peak gate-cathode voltage, V = 0
V
-120
V
KA
GKRM
Non-repetitive peak on-state pulse current, (see Notes 1 and 2)
10/1000 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4)
20
0.2/310 µs (I3124, open-circuit voltage wave shape 0.5/700 µs)
25
25
60
I
A
A
TSP
5/310 µs (ITU-T K20 & K21, open-circuit voltage wave shape 10/700 µs)
8/20 µs (IEC 61000-4-5:1995, open-circuit voltage wave shape 1.2/50 µs)
2/10 µs (Bellcore GR-1089-CORE, Issue 1, November 1994, Section 4)
Non-repetitive peak on-state current, 50/60 Hz, (see Notes 1 and 2)
100 ms
70
7
1 s
2.7
1.5
I
TSM
5 s
300 s
900 s
0.45
0.43
Non-repetitive peak gate current, 1/2 µs pulse, cathodes commoned (see Note 1)
Operating free-air temperature range
I
25
A
GSM
T
-40 to +85
-40 to +150
-65 to +150
°C
°C
°C
A
Junction temperature
T
J
Storage temperature range
T
stg
NOTES: 1. Initially the protector must be in thermal equilibrium. The surge may be repeated after the device returns to its initial conditions.
2. These non-repetitive rated currents are peak values for either polarirty. The rated current values may be applied to any cathode-
anode terminal pair. Additionally, all cathode-anode terminal pairs may have their rated current values applied simultaneously (in
this case the anode terminal current will be four times the rated current value of an individual terminal pair).
recommended operating conditions
MIN
TYP
MAX
UNIT
Series resistor for ITU-T recommendation K20
Seeries resistor for ITU-T recommendation K21
12
20
R1, R2
Ω
2
TISP6NTP2B
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED MAY 1999
electrical characteristics for any section, T
= 25 °C (unless otherwise noted)
amb
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
-5
UNIT
µA
T = 25 °C
J
I
Off-state current
V
= V
, I = 0
D
D
DRM G
T = 85 °C
-50
µA
J
I
I
= 0.6 A, t = 500 µs, V = -50 V
3
5
F
F
w
GG
V
Forward voltage
Holding current
V
F
= 18 A, t = 500 µs, V
= -50 V
w
GG
I
I
= -1 A, di/dt = 1A/ms, V = -50 V, T = 85 °C
-150
mA
µA
µA
H
T
GG
J
T = 25 °C
-5
J
I
Gate reverse current
V
= V
, V = 0
GKS
GG
GKRM AK
T = 85 °C
-50
J
Gate reverse current,
on state
I
I
I
= -0.6 A, t = 500 µs, V = -50 V
-1
mA
mA
GAT
T
F
w
GG
Gate reverse current,
forward conducting
state
-40
I
I
= 0.6 A, t = 500 µs, V = -50 V
GAF
w
GG
Gate trigger current
Gate trigger voltage
I = -5 A, t
≥ 20 µs, V
≥ 20 µs, V
= -50 V
= -50 V
5
2.5
100
60
mA
V
GT
T
p(g)
p(g)
GG
V
I = -5 A, t
T
GT
GG
V
V
= -3 V
pF
pF
Anode-cathode off-
state capacitance
D
C
f = 1 MHz, V = 1 V, I = 0, (see Note 3)
d G
AK
= -50 V
D
NOTE 3: These capacitance measurements employ a three terminal capacitance bridge incorporating a guard circuit. The unmeasured
device terminals are a.c. connected to the guard terminal of the bridge.
thermal characteristics
PARAMETER
MIN
TYP
MAX
UNIT
TEST CONDITIONS
2
R
Junction to free air thermal resistance
P
= 0.52 W, T = 85°C, 5 cm , FR4 PCB
160
°C/W
θJA
tot
A
3
TISP6NTP2B
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED MAY 1999
PARAMETER MEASUREMENT INFORMATION
PRINCIPAL TERMINAL V-I CHARACTERISTIC
GATE TRANSFER
CHARACTERISTIC
+i
+iK
Quadrant I
IFSP (= |ITSP|)
Forward
Conduction
Characteristic
IFSM (= |ITSM|)
IF
IF
VF
VGK(BO)
IGT
VGG
VD
+v
-iG
+iG
-v
ID
IGAF
I(BO)
IH
IS
VT
IGAT
VS
V(BO)
IT
IT
ITSM
IG
Quadrant III
Switching
IK
ITSP
Characteristic
-i
-iK
PM6XAIA
Figure 1. PRINCIPAL TERMINAL AND GATE TRANSFER CHARACTERISTICS
4
TISP6NTP2B
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED MAY 1999
APPLICATIONS INFORMATION
R1A
R1B
t°
t°
ELECTRONIC
SOURCE
6.8 Ω
"0 V"
-VE
NUMBER OF
NEGATIVE CLAMP
DIODES DEPENDS
ON "0V" POTENTIAL
ELECTRONIC
SINK
TWIN
ISDN
POWER
SUPPLY
TISP6NTP2B
NEGATIVE
SUPPLY
-VE
ELECTRONIC
SINK
6.8 Ω
"0 V"
ELECTRONIC
SOURCE
R2B
t°
R2A
t°
Figure 2. PROTECTION OF TWO ISDN POWER FEEDS
5
TISP6NTP2B
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED MAY 1999
APPLICATIONS INFORMATION
R1A
ELECTRONIC
-VE
SINK
R
t°
t°
t°
t°
t°
t°
t°
t°
0
-VE
0
R1B
R2A
R2B
ELECTRONIC
SINK
R
RESISTOR "R"
MAY BE NEEDED
IF SINK HAS
INTERNAL
CLAMP DIODE
ISDN
POWER
SUPPLY
ELECTRONIC
SINK
-VE
0
R
ELECTRONIC
SINK
-VE
0
R
NEGATIVE
SUPPLY
TISP6NTP2B
Figure 3. PROTECTION OF FOUR ISDN POWER FEEDS
6
TISP6NTP2B
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED MAY 1999
MECHANICAL DATA
D008
plastic small-outline package
This small-outline package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit performance
characteristics will remain stable when operated in high humidity conditions. Leads require no additional
cleaning or processing when used in soldered assembly.
D008
Designation per JEDEC Std 30:
PDSO-G8
5,00 (0.197)
4,80 (0.189)
8
7
6
5
6,20 (0.244)
5,80 (0.228)
4,00 (0.157)
3,81 (0.150)
1
2
3
4
7° NOM
3 Places
1,75 (0.069)
1,35 (0.053)
5,21 (0.205)
4,60 (0.181)
0,50 (0.020)
0,25 (0.010)
x 45°NOM
0,203 (0.008)
0,102 (0.004)
7° NOM
4 Places
0,51 (0.020)
0,36 (0.014)
8 Places
4° ± 4°
0,79 (0.031)
0,28 (0.011)
Pin Spacing
1,27 (0.050)
(see Note A)
6 Places
0,229 (0.0090)
0,190 (0.0075)
1,12 (0.044)
0,51 (0.020)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
MDXXAA
NOTES: A. Leads are within 0,25 (0.010) radius of true position at maximum material condition.
B. Body dimensions do not include mold flash or protrusion.
C. Mold flash or protrusion shall not exceed 0,15 (0.006).
D. Lead tips to be planar within ±0,051 (0.002).
7
TISP6NTP2B
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED MAY 1999
MECHANICAL DATA
D008
tape dimensions
D008 Package (8 pin SOIC) Single-Sprocket Tape
4,10
3,90
1,60
1,50
8,05
7,95
2,05
0,40
1,95
0,8 MIN.
5,55
5,45
12,30
11,70
Cover
Tape
6,50
6,30
ø 1,5 MIN.
0 MIN.
Carrier Tape
Embossment
2,2
2,0
Direction of Feed
ALL LINEAR DIMENSIONS IN MILLIMETERS
NOTES: A. Taped devices are supplied on a reel of the following dimensions:-
MDXXAT
Reel diameter:
Reel hub diameter:
Reel axial hole:
330 +0,0/-4,0 mm
100 ±2,0 mm
13,0 ±0,2 mm
B. 2500 devices are on a reel.
8
TISP6NTP2B
QUAD FORWARD-CONDUCTING BUFFERED P-GATE THYRISTORS
PROGRAMMABLE OVERVOLTAGE PROTECTORS
JUNE 1998 - REVISED MAY 1999
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or ser-
vice without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders,
that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in
accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems neces-
sary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those man-
dated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or
environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE
FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI products in such
applications requires the written approval of an appropriate TI officer. Questions concerning potential risk applications should be
directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating safeguards should be
provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents
or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1999, Texas Instruments Incorporated
9
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