THS4505DGNG4 [TI]
Wideband, Low-Distortion Fully Differential Amplifier 8-MSOP-PowerPAD -40 to 85;
| 型号： | THS4505DGNG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Wideband, Low-Distortion Fully Differential Amplifier 8-MSOP-PowerPAD -40 to 85 放大器 光电二极管 |
| 文件： | 总41页 (文件大小：1289K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4504
DGN-8 DGK-8
D-8
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
WIDEBAND, LOW-DISTORTION, FULLY DIFFERENTIAL AMPLIFIERS
FEATURES
APPLICATIONS
•
High Linearity Analog-to-Digital Converter
Preamplifier
•
•
•
•
•
•
•
Fully Differential Architecture
Bandwidth: 260 MHz
•
•
•
•
Wireless Communication Receiver Chains
Single-Ended to Differential Conversion
Differential Line Driver
Slew Rate: 1800 V/µs
IMD3: -73 dBc at 30 MHz
OIP3: 29 dBm at 30 MHz
Output Common-Mode Control
Active Filtering of Differential Signals
Wide Power Supply Voltage Range: 5 V, ±5 V,
1
8
V
IN+
V
IN−
12 V, 15 V
2
7
V
PD
V
OCM
•
Input Common-Mode Range Shifted to Include
the Negative Power Supply Rail
3
4
6
5
V
S+
S−
•
•
Power-Down Capability (THS4504)
Evaluation Module Available
V
OUT+
V
OUT−
RELATED DEVICES
DESCRIPTION
DEVICE(1)
THS4504/5
THS4500/1
THS4502/3
THS4120/1
THS4130/1
THS4140/1
THS4150/1
DESCRIPTION
The THS4504 and THS4505 are high-performance
fully differential amplifiers from Texas Instruments.
The THS4504, featuring power-down capability, and
the THS4505, without power-down capability, set new
performance standards for fully differential amplifiers
260 MHz, 1800 V/µs, VICR Includes VS-
370 MHz, 2800 V/µs, VICR Includes VS-
370 MHz, 2800 V/µs, Centered VICR
3.3 V, 100 MHz, 43 V/µs, 3.7 nV√Hz
±15 V, 150 MHz, 51 V/µs, 1.3 nV√Hz
±15 V, 160 MHz, 450 V/µs, 6.5 nV√Hz
±15 V, 150 MHz, 650 V/µs, 7.6 nV√Hz
with
unsurpassed
linearity,
supporting 12-bit
operation through 40 MHz. Package options include
the 8-pin SOIC and the 8-pin MSOP with
PowerPAD™ for a smaller footprint, enhanced ac
performance, and improved thermal dissipation
capability.
(1) Even numbered devices feature power-down capability
APPLICATION CIRCUIT DIAGRAM
8.2 pF
499 Ω
5 V
5 V
0.1 µF
10 µF
50 Ω
487 Ω
53.6 Ω
24.9 Ω
24.9 Ω
+
-
ADC
12 Bit/80 MSps
IN
V
OCM
V
S
IN
+
-
V
ref
1 µF
523 Ω
499 Ω
8.2 pF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRO-
Copyright © 2002–2004, Texas Instruments Incorporated
DUCTION DATA information current as of publication date. Prod-
ucts conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage, VS
16.5 V
Input voltage, VI
±VS
Output current, IO
150 mA
Differential input voltage, VID
4 V
See Dissipation Rating Table
150°C
Continuous power dissipation
Maximum junction temperature, TJ
Maximum junction temperature, continuous operation, long-term reliability, TJ
Storage temperature range, Tstg
(2)
125°C
-65°C to 150°C
300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
PACKAGE DISSIPATION RATINGS
POWER RATING(2)
PACKAGE
ΘJC (°C/W)
ΘJA(°C/W)(1)
TA≤ 25°C
1.02 W
TA = 85°C
410 mW
685 mW
154 mW
D (8 pin)
38.3
4.7
97.5
58.4
260
DGN (8 pin)
DGK (8 pin)
1.71 W
54.2
385 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long
term reliability.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX
UNIT
V
Dual supply
±5 ±7.5
Supply voltage
Single supply
4.5
-40
5
15
85
Operating free-air temperature, TA
°C
2
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
ORDERING INFORMATION
PACKAGED DEVICES
Power-down
PACKAGE TYPE
PACKAGE MARKINGS
TRANSPORT MEDIA, QUANTITY
THS4504D
Rails, 75
Tape and Reel, 2500
Rails, 100
SOIC-8
MSOP-8
—
THS4504DR
THS4504DGK
THS4504DGKR
THS4504DGN
THS4504DGNR
Non-power-down
THS4505D
ASZ
BDB
Tape and Reel, 2500
Rails, 80
MSOP-8-PP(1)
Tape and Reel, 2500
Rails, 75
Tape and Reel, 2500
Rails, 100
SOIC-8
MSOP-8
—
THS4505DR
THS4505DGK
THS4505DGKR
THS4505DGN
THS4505DGNR
ATA
BDC
Tape and Reel, 2500
Rails, 80
MSOP-8-PP(1)
Tape and Reel, 2500
(1) The PowerPAD is electrically isolated from all other pins.
PIN ASSIGNMENTS
D DGK, AND DGN
D, DGK, AND DGN
VIN+
8
THS4504
(TOP VIEW)
THS4505
(TOP VIEW)
VIN-
VOCM
VS+
VIN+
VIN-
VOCM
VS+
1
8
1
2
7
2
7
PD
NC
3
4
6
3
4
6
5
VS-
VS-
VOUT+
VOUT-
VOUT+
VOUT-
5
See Note A.
NC = No Internal Connection
Note A: The devices with the power down option defaults to the ON state if no signal is applied to the PD pin.
3
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
VS = ±5 V, Rf = Rg = 499 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted.
THS4504 AND THS4505
OVER TEMPERATURE
TYP
PARAMETER
TEST CONDITIONS
MIN/TYP
/MAX
0°C to
70°C
-40°C to
85°C
25°C
25°C
UNITS
AC PERFORMANCE
G = 1, PIN= -20 dBm, Rf = 499Ω
G = 2, PIN= -20 dBm, Rf = 499Ω
G = 5, PIN= -20 dBm, Rf = 499Ω
260
110
40
MHz
MHz
MHz
Typ
Typ
Typ
Small-signal bandwidth
G = 10, PIN= -20 dBm,
Rf = 499Ω
20
MHz
Typ
Gain-bandwidth product
Bandwidth for 0.1dB flatness
Large-signal bandwidth
Slew rate
G > +10
210
65
MHz
MHz
MHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
PIN = -20 dBm
G = 1, VP = 2 V
4 VPP Step
2 VPP Step
2 VPP Step
VO = 4 VPP
VO = 4 VPP
G = 1, VO = 2 VPP
f = 8 MHz
250
1800
0.8
1
Rise time
Fall time
ns
Settling time to 0.01%
0.1%
100
20
ns
ns
Harmonic distortion
-79
-66
-93
-65
dBc
dBc
dBc
dBc
2nd harmonic
3rd harmonic
f = 30 MHz
f = 8 MHz
f = 30 MHz
VO = 2 VPP, fc= 30 MHz,
Rf = 499Ω ,
200 kHz tone spacing
Third-order intermodulation
distortion
-73
dBc
Typ
fc = 30 MHz, Rf = 499Ω ,
Referenced to 50Ω
Third-order output intercept point
29
dBm
Typ
Input voltage noise
f > 1 MHz
8
2
nV/√Hz
pA/√Hz
ns
Typ
Typ
Typ
Input current noise
f > 100 kHz
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
Overdrive = 5.5 V
60
55
-4
52
50
-8 / 0
±10
5
50
-9 / +1
±10
5.2
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
-7 / -1
Average offset voltage drift
Input bias current
µV/°C
µA
4
4.6
1
Average bias current drift
Input offset current
±10
2
±10
2
nA/°C
µA
0.5
Average offset current drift
±40
±40
nA/°C
4
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
THS4504 AND THS4505
TYP
OVER TEMPERATURE
MIN/TYP
PARAMETER
TEST CONDITIONS
0°C to
70°C
-40°C to
85°C
/MAX
25°C
25°C
UNITS
INPUT
-5.7 /
2.6
Common-mode input range
-5.4 / 2.3
74
-5.1 / 2
70
-5.1 / 2
70
V
Min
Common-mode rejection ratio
Input impedance
80
107 || 1
dB
Min
Typ
Ω || pF
OUTPUT
Differential output voltage swing
Differential output current drive
Output balance error
RL = 1 kΩ
±8
130
-65
±7.6
±7.4
±7.4
V
Min
Min
Typ
RL = 20Ω
110
100
100
mA
dB
PIN = -20 dBm, f = 100 kHz
Closed-loop output impedance
(single-ended)
f = 1 MHz
0.1
Ω
Typ
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
RL = 400Ω
200
92
MHz
V/µs
V/V
V/V
mV
µA
Typ
Typ
Min
Max
Max
Max
Min
Typ
Max
Min
2 VPP step
Minimum gain
1
0.98
1.02
0.98
1.02
0.98
1.02
Maximum gain
1
Common-mode offset voltage
Input bias current
-0.4
100
±4
-4.6/+3.8 -6.6/+5.8
-7.6/+6.8
170
VOCM = 2.5 V
150
170
Input voltage range
±3.7
±3.4
±3.4
V
Input impedance
25 || 1
0
kΩ || pF
V
Maximum default voltage
Minimum default voltage
POWER SUPPLY
VOCM left floating
VOCM left floating
0.05
0.10
0.10
0
-0.05
-0.10
-0.10
V
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (±PSRR)
POWER-DOWN (THS4504 ONLY)
Enable voltage threshold
±5
16
16
80
±7.5
20
±7.5
23
±7.5
25
9
V
Max
Max
Min
Min
mA
mA
dB
13
11
76
73
70
Device enabled ON above -2.9 V
-2.9
-4.3
V
V
Min
Device disabled OFF below
-4.3 V
Disable voltage threshold
Max
Power-down quiescent current
Input bias current
800
200
1000
240
1200
260
1200
260
µA
µA
Max
Max
Typ
Typ
Typ
Input impedance
50 || 1
1000
800
kΩ || pF
ns
Turnon time delay
Turnoff time delay
ns
5
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
ELECTRICAL CHARACTERISTICS
VS = 5 V, Rf = Rg = 499 Ω, RL = 800 Ω, G = +1, Single-ended input unless otherwise noted
THS4504 AND THS4505
OVER TEMPERATURE
TYP
PARAMETER
TEST CONDITIONS
MIN/TY
P/MAX
0°C to
70°C
-40°C
to 85°C
25°C
25°C
UNITS
AC PERFORMANCE
G = 1, PIN = -20 dBm, Rf = 499Ω
G = 2, PIN= -20 dBm, Rf = 499Ω
G = 5, PIN= -20 dBm, Rf = 499Ω
G = 10, PIN= -20 dBm, Rf = 499Ω
G > +10
210
120
40
MHz
MHz
MHz
MHz
MHz
Typ
Typ
Typ
Typ
Typ
Small-signal bandwidth
Gain-bandwidth product
20
200
Bandwidth for 0.1 dB
flatness
PIN = -20 dBm
100
MHz
Typ
Large-signal bandwidth
Slew rate
G = 1, VP= 1 V
2 VPP Step
200
900
1.1
1
MHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Rise time
2 VPP Step
Fall time
2 VPP Step
ns
Settling time to 0.01%
0.1%
VO = 2 V Step
VO = 2 V Step
G = 1, VO = 2 VPP
f = 8 MHz,
100
20
ns
ns
Harmonic distortion
-77
-56
-74
-57
dBc
dBc
dBc
dBc
2nd harmonic
3rd harmonic
f = 30 MHz
f = 8 MHz
f = 30 MHz
Third-order intermodulation
distortion
VO = 2 VPP, fc= 30 MHz, Rf = 499 Ω,
200 kHz tone spacing
-72
28
dBc
Typ
Typ
Third-order output
intercept point
fc = 30 MHz, Rf = 499Ω ,
Referenced to 50Ω
dBm
Input voltage noise
f > 1 MHz
8
2
nV/√Hz
pA/√Hz
ns
Typ
Typ
Typ
Input current noise
f > 100 kHz
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
Overdrive = 5.5 V
60
54
-4
51
49
-8/0
±10
5
49
-9/+1
±10
5.2
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
-7/-1
Average offset voltage drift
Input bias current
µV/°C
µA
4
4.6
0.7
Average bias current drift
Input offset current
±10
1.2
±20
±10
1.2
nA/°C
µA
0.5
Average offset current drift
±20
nA/°C
6
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
THS4504 AND THS4505
TYP
OVER TEMPERATURE
MIN/TY
PARAMETER
TEST CONDITIONS
0°C to
70°C
-40°C
P/MAX
25°C
25°C
UNITS
to 85°C
INPUT
Common-mode input range
Common-mode rejection ratio
Input impedance
-0.7/2.6 -0.4/2.3
-0.1/2
70
-0.1/2
70
V
dB
Min
Min
Typ
80
74
107 || 1
Ω || pF
OUTPUT
Differential output voltage swing
Output current drive
RL = 1 kΩ, Referenced to 2.5 V
RL = 20Ω
±3.3
110
-38
±3
±2.8
±2.8
V
Min
Min
Typ
90
80
80
mA
dB
Output balance error
PIN = -20 dBm, f = 100 kHz
Closed-loop output
impedance (single-ended)
f = 1 MHz
0.1
Ω
Typ
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
RL = 400Ω
160
80
1
MHz
V/µs
V/V
Typ
Typ
Min
Max
2 VPP Step
Minimum gain
Maximum gain
0.98
1.02
0.98
1.02
0.98
1.02
1
V/V
Common-mode offset
voltage
0.4
-2.6/3.4
-4.2/5.4 -5.6/6.4
mV
Max
Input bias current
VOCM = 2.5 V
1
1/4
2
3
3
µA
Max
Min
Typ
Max
Min
Input voltage range
1.2/3.8
1.3/3.7
1.3/3.7
V
Input impedance
25 || 1
2.5
kΩ || pF
Maximum default voltage
Minimum default voltage
POWER SUPPLY
VOCM left floating
VOCM left floating
2.55
2.45
2.6
2.4
2.6
2.4
V
V
2.5
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
POWER-DOWN (THS4504 ONLY)
Enable voltage threshold
5
15
17
11
72
15
19
10
69
15
21
8
V
Max
Max
Min
Min
14
14
75
mA
mA
dB
66
Device enabled ON above 2.1 V
2.1
0.7
V
V
Min
Device disabled OFF below
0.7 V
Disable voltage threshold
Max
Power-down quiescent
current
600
800
125
1200
140
1200
140
µA
Max
Input bias current
Input impedance
Turnon time delay
Turnoff time delay
100
50 || 1
1000
800
µA
kΩ || pF
ns
Max
Typ
Typ
Typ
ns
7
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
1
Small signal unity gain frequency response
Small signal frequency response
2
0.1 dB gain flatness frequency response
Large signal frequency response
3
4
Harmonic distortion (single-ended input to differential output) vs Frequency
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
Harmonic distortion (single-ended input to differential output) vs Load resistance
Third order intermodulation distortion (single-ended input to differential output) vs Frequency
Third order output intercept point vs Frequency
Slew rate vs Differential output voltage step
5
6, 7
8
9
10
11
12, 13
14
15
16, 17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
Settling time
Large signal transient response
Small signal transient response
Overdrive recovery
Voltage and current noise vs Frequency
Rejection ratios vs Frequency
Rejection ratios vs Case temperature
Output balance error vs Frequency
Open-loop gain and phase vs Frequency
Open-loop gain vs Case temperature
Input bias offset current vs Case temperature
Quiescent current vs Supply voltage
Input offset voltage vs Case temperature
Common-mode rejection ratio vs Input common-mode range
Output voltage vs Load resistance
Closed-loop output impedance vs Frequency
Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage
Small signal frequency response at VOCM
Output offset voltage at VOCM vs Output common-mode voltage
Quiescent current vs Power-down voltage
Turnon and turnoff delay times
Single-ended output impedance in power down vs Frequency
Power-down quiescent current vs Case temperature
Power-down quiescent current vs Supply voltage
8
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
Table of Graphs (5 V)
FIGURE
38
Small signal unity gain frequency response
Small signal frequency response
39
0.1 dB gain flatness frequency response
40
Large signal frequency response
41
Harmonic distortion (single-ended input to differential output) vs Frequency
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
Harmonic distortion (single-ended input to differential output) vs Load resistance
Third-order intermodulation distortion vs Frequency
Third-order intercept point vs Frequency
42
43, 44
45
46
47
Slew rate vs Differential output voltage step
Settling time
48
49, 50
51, 52
53
Overdrive recovery
Large-signal transient response
Small-signal transient response
54
Voltage and current noise vs Frequency
55
Rejection ratios vs Frequency
56
Rejection ratios vs Case temperature
57
Output balance error vs Frequency
58
Open-loop gain and phase vs Frequency
Open-loop gain vs Case temperature
59
60
Input bias offset current vs Case temperature
Quiescent current vs Supply voltage
61
62
Input offset voltage vs Case temperature
Common-mode rejection ratio vs Input common-mode range
Output voltage vs Load resistance
63
64
65
Closed-loop output impedance vs Frequency
Harmonic distortion (single-ended and differential input) vs Output common-mode voltage
Small signal frequency response at VOCM
Output offset voltage vs Output common-mode voltage
Quiescent current vs Power-down voltage
Turnon and turnoff delay times
66
67
68
69
70
71
Single-ended output impedance in power down vs Frequency
Power-down quiescent current vs Case temperature
Power-down quiescent current vs Supply voltage
72
73
74
9
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (±5 V GRAPHS)
SMALL SIGNAL UNITY GAIN
FREQUENCY
SMALL SIGNAL FREQUENCY
RESPONSE
0.1 Db GAIN FLATNESS
FREQUENCY RESPONSE
1
22
20
18
16
14
12
10
0.05
Gain = 10
0.5
R = 499 Ω
f
0
−0.05
−0.1
0
−0.5
−1
Gain = 5
−1.5
−2
−0.15
−0.2
8
6
4
2
Gain = 2
Gain = 1
Gain = 1
−2.5
−3
R
L
= 800 Ω
R
L
= 800 Ω
R
= 800 Ω
= −20 dBm
= ±5 V
L
R = 499 Ω
f
R =499 Ω
f
P
V
IN
S
P
V
= −20 dBm
= ±5 V
−0.25
−0.3
IN
S
P
V
= −20 dBm
= ±5 V
IN
S
−3.5
−4
0
−2
0.1
0.1
1
10
100
1000
10
100
1000
1
10
100
1000
1
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 1.
Figure 2.
Figure 3.
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
LARGE SIGNAL FREQUENCY
RESPONSE
vs
FREQUENCY
25
20
15
10
0
0
R
V
V
= 800 Ω
= 2 V
PP
= ±5 V
Single-Ended Input to
Differential Output
Gain = 1
L
Single-Ended Input to
Differential Output
Gain = 1
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
Gain = 10, R = 1.8 kΩ
f
O
S
−20
−30
−40
−50
−60
−70
−80
R = 800 Ω
L
R
L
= 800 Ω
Gain = 5, R = 1.8 kΩ
R = 499 Ω
f
R = 499 Ω
f
f
f= 8 MHz
V
V
= 2 V
PP
= ±5 V
O
S
V
= ±5 V
S
Gain = 2, R = 1.8 kΩ
f
5
HD2
HD2
Gain = 1, R = 499 Ω
f
0
−90
HD3
HD3
4
−100
−5
0.1
1
10
100
0
0.5
1
1.5
2
2.5
3
3.5
4.5
5
0.1
1
10
100
1000
f − Frequency − MHz
V
− Output Voltage Swing − V
O
f − Frequency − MHz
Figure 4.
Figure 5.
Figure 6.
THIRD-ORDER INTERMODULATION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
LOAD RESISTANCE
DISTORTION
vs
FREQUENCY
0
0
−30
Single-Ended Input to
Differential Output
Single Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−40
−50
Gain = 1
R = 800 Ω
L
R = 499 Ω
f
V = ±5 V
S
−20
−30
−40
−50
V
= 2 V
PP
O
R
L
= 800 Ω
V
= 2 V
PP
O
R = 499 Ω
R = 499 Ω
f
f
f= 30 MHz
V
= ±5 V
S
−60
−70
V
= ±5 V
S
HD3, 30 MHz
HD2, 30 MHz
−60
−70
−80
HD2
HD2, 8 MHz
−80
−90
V
= 1 V
PP
O
HD3
−90
200 kHz Tone Spacing
HD3, 8 MHz
400
−100
−100
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
10
100
0
800
1200
1600
V
− Output Voltage Swing − V
f − Frequency − MHz
R
L
− Load Resistance − Ω
O
Figure 7.
Figure 8.
Figure 9.
10
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (±5 V Graphs) (continued)
THIRD-ORDER OUTPUT INTERCEPT
SLEW RATE
POINT
vs
vs
DIFFERENTIAL OUTPUT VOLTAGE
STEP
FREQUENCY
SETTLING TIME
2000
1.5
60
Fall
Gain = 1
Gain = 1
= 800 Ω
1800
1600
1400
1200
1000
800
Rising Edge
R = 499 Ω
R
L
f
50
40
30
20
1
V
V
= 2 V
PP
= ± 5 V
R = 499 Ω
O
f
Rise
V
= ±5 V
S
S
200 kHz Tone Spacing
Normalized to 50 Ω
Gain = 1
= 800 Ω
0.5
0
R
L
R = 499 Ω
f
f= 1 MHz
V
= ±5 V
S
−0.5
−1
Normalized to 200 Ω
600
Falling Edge
400
R
L
= 800 Ω
10
0
200
0
200 kHz Tone Spacing
−1.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
50
100
150
200
250
300
0
20
40 60 80 100
t − Time − ns
V
− Differential Output Voltage Step − V
O
f − Frequency − MHz
Figure 10.
Figure 11.
Figure 12.
LARGE-SIGNAL TRANSIENT
RESPONSE
SMALL-SIGNAL TRANSIENT
RESPONSE
SETTLING TIME
3
2
1
0.4
0.3
2
Rising Edge
1.5
0.2
1
Gain = 1
Gain = 1
Gain = 1
R = 800 Ω
L
R = 499 Ω
f
R
L
= 800 Ω
0.1
0.5
R
L
= 800 Ω
R = 499 Ω
f
R = 499 Ω
f
f= 1 MHz
0
0
0
−0.5
−1
t /t = 300 ps
t /t = 300 ps
r
f
r
f
V
= ±5 V
S
V
= ±5 V
V
= ±5 V
S
S
−0.1
−0.2
−0.3
−0.4
−1
Falling Edge
−2
−3
−1.5
−2
0
5
10 15 20 25 30 35 40
−100
0
100
200
300
400
500
−100
0
100
200
300
400
500
t − Time − ns
t − Time − ns
t − Time − ns
Figure 13.
Figure 14.
Figure 15.
VOLTAGE AND CURRENT NOISE
vs
OVERDRIVE RECOVERY
OVERDRIVE RECOVERY
FREQUENCY
2.5
2
3
2
1
0
100
5
4
3
6
5
4
3
2
1
Gain = 4
= 800 Ω
Gain = 4
= 800 Ω
R
L
R
L
R = 499 Ω
R = 499 Ω
1.5
f
f
Overdrive = 5.5 V
Overdrive = 4.5 V
1
2
1
V
= ±5 V
V
= ±5 V
S
S
0.5
0
V
n
0
10
0
−0.5
−1
−2
−1
−1
−2
−3
−1
−2
−3
−3
−4
−1.5
I
n
−2
−4
−5
−5
−6
−2.5
1
0.01 0.1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
1
10
100 1000 10 k
t − Time − µs
t − Time − µs
f − Frequency − kHz
Figure 16.
Figure 17.
Figure 18.
11
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THS4505
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (±5 V Graphs) (continued)
REJECTION RATIOS
vs
REJECTION RATIOS
vs
CASE TEMPERATURE
OUTPUT BALANCE ERROR
vs
FREQUENCY
FREQUENCY
10
90
80
70
60
50
40
30
20
10
0
120
100
P
= 16 dBm
PSRR+
IN
0
−10
−20
−30
−40
−50
−60
−70
−80
CMMR
R
L
= 800 Ω
R = 499 Ω
f
PSRR+
V
= ±5 V
S
80
60
40
20
0
CMMR
PSRR−
R
V
= 800 Ω
= ±5 V
R
V
= 800 Ω
= ±5 V
L
L
S
S
−10
0.1
1
10
100
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
0.1
1
10
100
f − Frequency − MHz
Case Temperature − °C
f − Frequency − MHz
Figure 19.
Figure 20.
Figure 21.
INPUT BIAS AND OFFSET
CURRENT
OPEN-LOOP GAIN AND PHASE
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
vs
vs
FREQUENCY
CASE TEMPERATURE
3.4
0
58
57
56
55
54
53
52
51
50
49
60
30
V
= ±5 V
S
Gain
I
IB−
P
R
V
= −30 dBm
= 800 Ω
= ±5 V
R
= 800 Ω
= ±5 V
−0.01
IN
L
3.3
3.2
3.1
V
L
S
50
40
30
20
0
−0.02
−0.03
−0.04
−0.05
S
I
IB+
−30
−60
−90
3
2.9
Phase
−0.06
−0.07
−0.08
−0.09
2.8
2.7
I
OS
2.6
2.5
−120
−150
10
0
−40−30−20−100 10 20 30 40 50 60 70 80 90
Case Temperature − °C
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0.01
0.1
1
10
100
1000
Case Temperature − °C
f − Frequency − MHz
Figure 22.
Figure 23.
Figure 24.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
25
20
15
10
5
110
V
= ±5 V
V
= ±5 V
S
100
90
80
70
60
50
40
30
20
10
S
T
A
= 85°C
4
T
A
= 25°C
3
2
T
A
= −40°C
1
0
5
0
0
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
−6 −5 −4 −3 −2 −1
0
1
2
3
4
5
6
Case Temperature − °C
V
− Supply Voltage − ±V
Input Common-Mode Voltage Range − V
S
Figure 25.
Figure 26.
Figure 27.
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (±5 V Graphs) (continued)
CLOSED-LOOP OUTPUT
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE
VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
IMPEDANCE
vs
FREQUENCY
5
4
3
2
1
100
10
0
Single-Ended to
Differential Output
Gain = 1
−10
Gain = 1
= 400 Ω
R
L
−20
−30
−40
−50
−60
−70
−80
−90
−100
R = 499 Ω
f
V
= 2 V
O
PP
V = −4 dBm
I
R = 499 Ω
f
V
= ±5 V
S
V
= ±5 V
S
V
T
A
= ±5 V
= −40 to 85°C
S
HD3, 30 MHz
0
HD2, 30 MHz
HD2, 8 MHz
−1
1
−2
−3
HD2, 3 MHz
−4
−5
0.1
0.1
10
100
1000
−3.5 −2.5 −1.5 −0.5 0.5
1.5
2.5
3.5
10000
1
10
100
R
L
− Load Resistance − Ω
V
− Output Common-Mode Voltage − V
OCM
f − Frequency − MHz
Figure 28.
Figure 29.
Figure 30.
OUTPUT OFFSET VOLTAGE AT
VOCM
vs
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
SMALL SIGNAL FREQUENCY
RESPONSE AT VOCM
OUTPUT COMMON-MODE
VOLTAGE
30
25
20
15
10
600
400
200
3
2
Gain = 1
R
L
= 400 Ω
R = 499 Ω
f
P
V
= −20 dBm
= ±5 V
IN
1
S
0
0
−200
−1
5
−400
−600
0
−2
−3
−5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5
0
−5 −4 −3 −2 −1
0
1
2
3
4
5
1
10
100
1000
Power-Down Voltage − V
V
− Output Common-Mode Voltage − V
OC
f − Frequency − MHz
Figure 31.
Figure 32.
Figure 33.
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TYPICAL CHARACTERISTICS (±5 V Graphs) (continued)
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER DOWN
vs
FREQUENCY
TURNON AND
TURNOFF DELAY TIME
1500
1200
0.03
0.02
0.01
Current
0
0
900
600
−1
−2
−3
−4
Gain = 1
= 800 Ω
R
L
R = 499 Ω
f
300
0
V = −1 dBm
I
V
= ±5 V
S
−5
−6
0.1
1
10
100
1000
0 0.5 1 1.5 2 2.5
3
100.5101 102
103
f − Frequency − MHz
t − Time − ms
Figure 34.
Figure 35.
POWER-DOWN QUIESCENT CURRENT
POWER-DOWN QUIESCENT CURRENT
vs
vs
CASE TEMPERATURE
SUPPLY VOLTAGE
1000
1000
R
= 800 Ω
R
= 800 Ω
= ±5 V
L
L
900
800
700
900
800
700
600
500
400
300
200
V
S
600
500
400
300
200
100
0
100
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
V
− Supply Voltage − ±V
Case Temperature − °C
S
Figure 36.
Figure 37.
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (5 V GRAPHS)
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY
RESPONSE
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
1
0
22
20
18
16
14
12
10
0.05
Gain = 10
0
−0.05
−0.1
R = 499 Ω
f
Gain = 5
−1
−2
−0.15
−0.2
8
6
4
2
Gain = 2
Gain = 1
= 800 Ω
R
L
Gain = 1
R
L
= 800 Ω
R = 499 Ω
−3
−4
f
R
= 800 Ω
= −20 dBm
= 5 V
L
R = 499 Ω
f
P
V
= −20 dBm
= 5 V
−0.25
−0.3
IN
S
P
V
IN
S
P
V
= −20 dBm
= 5 V
IN
S
0
−2
0.1
10
100
1000
0.1
1
10
100
1000
1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 38.
Figure 39.
Figure 40.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
LARGE SIGNAL FREQUENCY
RESPONSE
vs
FREQUENCY
0
25
20
15
10
5
0
Single-Ended Input to
Differential Output
Gain = 1
R
V
V
= 800 Ω
= 2 V
PP
= 5 V
Single-Ended Input to
Differential Output
Gain = 1
L
−10
−10
−20
−30
−40
−50
−60
−70
−80
Gain = 10, R = 1.8 kΩ
f
O
S
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
L
= 800 Ω
R = 800 Ω
L
R = 499 Ω
f
Gain = 5, R = 1.8 kΩ
R = 499 Ω
f
f
f= 8 MHz
V
V
= 2 V
= 5 V
O
S
PP
V
= 5 V
S
Gain = 2, R = 1.8 kΩ
f
HD3
HD3
Gain = 1, R = 1.8 kΩ
f
HD2
HD2
0
−90
−100
−5
0
0.5
1
1.5
2
2.5
3
3.5
4
0.1
1
10
100
0.1
1
10
100
1000
V
− Output Voltage Swing − V
f − Frequency − MHz
O
f − Frequency − MHz
Figure 41.
Figure 42.
Figure 43.
THIRD-ORDER INTERMODULATION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
LOAD RESISTANCE
DISTORTION
vs
FREQUENCY
0
−30
0
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Single-Ended Input to
Differential Output
Gain = 1
−10
−10
−40
−50
−20
−30
−40
−50
−60
−70
−80
−90
−100
V
= 2 V
PP
Gain = 1
O
−20
−30
−40
−50
R = 499 Ω
R
L
= 800 Ω
f
S
R
L
= 800 Ω
V
= 2 V
PP
O
V
= ±5 V
R = 499 Ω
R = 499 Ω
f
f
f= 30 MHz
V
= 5 V
S
HD2, 30 MHz
−60
−70
HD3, 30 MHz
V
= 5 V
S
HD2
−60
−70
−80
V
= 1 V
PP
O
−80
−90
HD3
1
HD3, 8 MHz
400
−90
200 kHz Tone Spacing
HD2, 8 MHz
800 1200
−100
−100
0
0.5
1.5
2
2.5
3
3.5
4
10
100
0
1600
f − Frequency − MHz
V
− Output Voltage Swing − V
R
L
− Load Resistance − Ω
O
Figure 44.
Figure 45.
Figure 46.
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (5 V Graphs) (continued)
THIRD-ORDER OUTPUT INTERCEPT
SLEW RATE
POINT
vs
vs
DIFFERENTIAL OUTPUT VOLTAGE
STEP
FREQUENCY
SETTLING TIME
1.5
60
1200
Gain = 1
= 800 Ω
Gain = 1
R = 499 Ω
f
Fall
Rising Edge
R
L
50
40
30
20
1000
800
600
400
200
0
1
R = 499 Ω
V
V
= 2 V
PP
f
O
V
= 5 V
=
5 V
S
S
Gain = 1
200 kHz Tone Spacing
0.5
Rise
R
L
= 800 Ω
Normalized to 50 Ω
R = 499 Ω
f
f= 1 MHz
0
−0.5
−1
V
= 5 V
S
Normalized to 200 Ω
Falling Edge
R
L
= 800 Ω
10
0
−1.5
0
0.5
1
1.5
2
2.5
3
3.5
4
50
100
150
200
250
300
0
0
20
40
60
80
100
t − Time − ns
V
− Differential Output Voltage Step − V
O
f − Frequency − MHz
Figure 47.
Figure 48.
Figure 49.
SETTLING TIME
OVERDRIVE RECOVERY
OVERDRIVE RECOVERY
2.5
3
2
1
0
5
4
3
6
5
4
3
2
1
3
Gain = 4
= 800 Ω
Gain = 4
= 800 Ω
2
Rising Edge
R
L
R
L
2
1
R = 499 Ω
R = 499 Ω
1.5
f
f
Overdrive = 5.5 V
Overdrive = 4.5 V
1
Gain = 1
2
1
V
= ±5 V
V
= ±5 V
S
S
R
L
= 800 Ω
0.5
0
R = 499 Ω
f
f= 1 MHz
0
0
0
V
= 5 V
S
−0.5
−1
−2
−1
−1
−2
−3
−1
−1
−2
−3
−3
−4
Falling Edge
−1.5
−2
−3
−2
−4
−5
−5
−6
−2.5
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
5
10 15 20 25 30 35 40
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
t − Time − µs
1
t − Time − µs
t − Time − ns
Figure 50.
Figure 51.
Figure 52.
VOLTAGE AND CURRENT NOISE
LARGE-SIGNAL TRANSIENT
RESPONSE
SMALL-SIGNAL TRANSIENT
RESPONSE
vs
FREQUENCY
0.4
0.3
0.2
0.1
0
100
2
1.5
1
Gain = 1
Gain = 1
R = 800 Ω
L
R = 499 Ω
f
0.5
R
L
= 800 Ω
V
n
R = 499 Ω
f
10
0
−0.5
−1
t /t = 300 ps
t /t = 300 ps
r
f
r
f
V
= ±5 V
V
= ±5 V
S
S
−0.1
−0.2
−0.3
−0.4
I
n
−1.5
−2
1
0.01 0.1
−100
0
100
200
300
400
500
−100
0
100
200
300
400
500
1
10
100 1000 10 k
t − Time − ns
t − Time − ns
f − Frequency − kHz
Figure 53.
Figure 54.
Figure 55.
16
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (5 V Graphs) (continued)
REJECTION RATIOS
vs
REJECTION RATIOS
vs
CASE TEMPERATURE
OUTPUT BALANCE ERROR
vs
FREQUENCY
FREQUENCY
90
80
70
60
50
40
30
20
10
0
120
100
0
P
R
= 16 dBm
= 800 Ω
IN
PSRR+
CMMR
−10
−20
−30
−40
−50
−60
−70
−80
L
R = 499 Ω
V
f
PSRR−
= 5 V
S
80
60
40
CMMR
PSRR+
PSRR−
20
0
R
V
= 800 Ω
= 5 V
R
V
= 800 Ω
L
L
= 5 V
S
S
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0.1
1
10
100
0.1
1
10
100
Case Temperature − °C
f − Frequency − MHz
f − Frequency − MHz
Figure 56.
Figure 57.
Figure 58.
INPUT BIAS AND OFFSET
CURRENT
OPEN-LOOP GAIN AND PHASE
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
vs
vs
FREQUENCY
CASE TEMPERATURE
3.75
0
60
57
56
55
54
53
52
51
50
49
48
47
46
30
V
= 5 V
S
R
V
= 800 Ω
= 5 V
Gain
−0.01
P
R
V
= −30 dBm
= 800 Ω
= 5 V
L
IN
3.5
I
IB+
S
L
50
40
30
20
−0.02
−0.03
−0.04
−0.05
−0.06
−0.07
−0.08
3.25
0
S
3
I
IB−
−30
−60
−90
2.75
2.5
I
OS
2.25
Phase
2
1.75
−120
−150
−0.09
−0.1
10
0
1.5
1.25
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−40−30−20−100 10 20 30 40 50 60 70 80 90
Case Temperature − °C
0.01
0.1
1
10
100
1000
Case Temperature − °C
f − Frequency − MHz
Figure 59.
Figure 60.
Figure 61.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
INPUT COMMON-MODE RANGE
25
20
15
10
5
110
V = 5 V
S
V
= 5 V
100
90
80
70
60
50
40
30
S
T
A
= 85°C
4
3
2
T
A
= 25°C
T
A
= −40°C
20
10
1
0
5
0
0
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
−1
0
1
2
3
4
5
Input Common-Mode Range − V
Case Temperature − °C
V
− Supply Voltage − ±V
S
Figure 62.
Figure 63.
Figure 64.
17
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THS4505
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (5 V Graphs) (continued)
CLOSED-LOOP OUTPUT
HARMONIC DISTORTION
vs
OUTPUT COMMON-MODE
VOLTAGE
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
IMPEDANCE
vs
FREQUENCY
5
4
3
2
1
100
10
0
−10
−20
−30
Single-Ended to
Differential Output
Gain = 1, V = 2 V
Gain = 1
= 400 Ω
R
L
O
PP
R = 499 Ω, V = 5 V
f
S
R = 499 Ω
f
V
V
= −4 dBm
= 5 V
IN
S
HD2, 30 MHz
V
= ±5 V
S
T
= −40 to 85°C
HD3, 30 MHz
A
0
−40
−50
−1
1
−2
−3
−60
−70
−80
HD3, 8 MHz
HD2,
8 MHz
−4
−5
0.1
0.1
1.5
2.5
3.5
1
2
3
4
10
100
1000
10000
1
10
100
V
− Output Common-Mode Voltage − V
R
L
− Load Resistance − Ω
OC
f − Frequency − MHz
Figure 65.
Figure 66.
Figure 67.
OUTPUT OFFSET VOLTAGE
vs
OUTPUT COMMON-MODE
VOLTAGE
SMALL SIGNAL FREQUENCY
RESPONSE
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
AT VOCM
800
600
400
200
25
20
3
2
V
= 5 V
S
Gain = 1
R
L
= 400 Ω
R = 499 Ω
f
P
V
= −20 dBm
= 5 V
IN
1
S
15
10
5
0
0
−200
−1
−400
−600
−800
−2
−3
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5
1
10
100
1000
Power-down Voltage − V
V
− Output Common-Mode Voltage − V
OC
f − Frequency − MHz
Figure 68.
Figure 69.
Figure 70.
18
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
TYPICAL CHARACTERISTICS (5 V Graphs) (continued)
SINGLE-ENDED OUTPUT
IMPEDANCE
POWER-DOWN QUIESCENT
CURRENT
IN POWER DOWN
TURNON AND TURNOFF
DELAY TIME
vs
vs
FREQUENCY
CASE TEMPERATURE
800
0.03
0.02
0.01
0
1500
1200
R
L
= 800 Ω
700
600
500
V
= 5 V
S
Current
0
900
600
−1
400
300
−2
−3
−4
Gain = 1
= 800 Ω
R
L
200
R = 499 Ω
f
300
0
P
V
= −1 dBm
= 5 V
IN
S
100
0
−5
−6
0.1
1
10
100
1000
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0 0.5 1 1.5 2 2.5
3
100.5101 102
103
f − Frequency − MHz
Case Temperature − °C
t − Time − ms
Figure 71.
Figure 72.
Figure 73.
POWER-DOWN QUIESCENT
CURRENT
vs
SUPPLY VOLTAGE
1000
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
V
− Supply Voltage − V
S
Figure 74.
19
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
APPLICATION INFORMATION
•
Additional Reference Material
FULLY DIFFERENTIAL AMPLIFIERS
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems, including immunity to external com-
mon-mode noise, suppression of even-order
nonlinearities, and increased dynamic range. Fully
differential amplifiers not only serve as the primary
means of providing gain to a differential signal chain,
but also provide a monolithic solution for converting
single-ended signals into differential signals for
easier, higher performance processing. The THS4500
family of amplifiers contains the flagship products in
Fully differential amplifiers are typically packaged in
eight-pin packages as shown in the diagram. The
device pins include two inputs (VIN+,VIN-), two outputs
(VOUT-,VOUT+), two power supplies (VS+, VS-), an
output common-mode control pin (VOCM), and an
optional power-down pin (PD).
VIN−
VOCM
VS+
VIN+
PD
1
8
Texas
Instruments'
expanding
line
of
2
7
high-performance fully differential amplifiers. Infor-
mation on fully differential amplifier fundamentals, as
well as implementation-specific information, is pres-
ented in the applications section of this data sheet to
provide a better understanding of the operation of the
THS4500 family of devices, and to simplify the design
process for designs using these amplifiers.
3
4
6
5
VS−
VOUT+
VOUT−
Fully Differential Amplifier Pin Diagram
The THS4504 and THS4505 are intended to be
low-cost alternatives to the THS4500/1/2/3 devices.
From a topology standpoint, the THS4504/5 have the
same architecture as the THS4500/1. Specifically, the
input common-mode range is designed to include the
negative power supply rail.
A standard configuration for the device is shown in
the figure. The functionality of a fully differential
amplifier can be imagined as two inverting amplifiers
that share a common noninverting terminal (though
the voltage is not necessarily fixed). For more infor-
mation on the basic theory of operation for fully
differential amplifiers, refer to the Texas Instruments
application note titled Fully Differential Ampli-
fiers(SLOA054).
Applications Section
•
•
Fully Differential Amplifier Terminal Functions
Input Common-Mode Voltage Range and the
THS4500 Family
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
•
•
•
•
Choosing the Proper Value for the Feedback and
Gain Resistors
Application Circuits Using Fully Differential Ampli-
fiers
Key Design Considerations for Interfacing to an
Analog-to-Digital Converter
Setting the Output Common-Mode Voltage With
the VOCM Input
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the
two devices. The input common-mode range of the
THS4504/5 is the same as the THS4500/1. The
THS4502 and THS4503 have an input com-
mon-mode range that is centered around midrail, and
the THS4500 and THS4501 have an input com-
mon-mode range that is shifted to include the nega-
tive power supply rail. Selection of one or the other is
determined by the nature of the application. Specifi-
cally, the THS4500 and THS4501 are designed for
use in single-supply applications where the input
signal is ground-referenced, as depicted in Figure 75.
The THS4502 and THS4503 are designed for use in
single-supply or split-supply applications where the
input signal is centered between the power supply
voltages, as depicted in Figure 76.
•
•
Saving Power with Power-Down Functionality
Linearity: Definitions, Terminology, Circuit Tech-
niques, and Design Tradeoffs
•
•
An Abbreviated Analysis of Noise in Fully Differ-
ential Amplifiers
Printed-Circuit Board Layout Techniques for Opti-
mal Performance
•
•
Power Dissipation and Thermal Considerations
Power Supply Decoupling Techniques and Rec-
ommendations
•
Evaluation Fixtures, Spice Models, and Appli-
cations Support
20
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
R
g1
R
f1
VIN)(1–β)–VIN–(1–β) ) 2VOCMβ
+
R
S
(1)
VOUT)
2β
+V
S
R
T
V
S
–VIN)(1–β) ) VIN–(1–β) ) 2VOCMβ
2β
(2)
+
−
VOUT–
+
−
+
V
OCM
VN + VIN–(1–β) ) VOUT)
β
(3)
(4)
(5)
RG
RF ) RG
Where:
β +
R
g2
R
f2
Application Circuit for the THS4500 and THS4501,
Featuring Single-Supply Operation With a
Ground-Referenced Input Signal
VP + VIN)(1–β) ) VOUT–β
NOTE:
Figure 75.
The equations denote the
device inputs as VN and
R
g1
R
f1
R
S
VP, and the circuit inputs
+V
S
as VIN+ and VIN-
.
R
T
V
S
R
g
R
f
+
−
V
IN+
−
+
V
OCM
V
p
V
V
+
−
OUT−
−
+
V
OCM
OUT+
−V
S
V
n
V
IN−
R
g2
R
f2
R
g
R
f
Diagram For Input Common-Mode Range Equations
Application Circuit for the THS4500 and THS4501,
Featuring Split-Supply Operation With an Input
Signal Referenced at the Midrail
Figure 77.
Table 1 and Table 2 show the input common-mode
range requirements for two different input scenarios,
an input referenced around the negative rail and an
input referenced around midrail. The tables highlight
the differing requirements on input common-mode
range, and illustrate reasoning for choosing either the
THS4500/1 or the THS4502/3. For signals referenced
around the negative power supply, the THS4500/1
should be chosen since its input common-mode
range includes the negative supply rail. For all other
situations, the THS4502/3 offers slightly improved
distortion and noise performance for applications with
input signals centered between the power supply
rails.
Figure 76.
Equations 1-5 allow calculation of the required input
common-mode range for a given set of input con-
ditions.
The equations allow calculation of the input common-
mode range requirements given information about the
input signal, the output voltage swing, the gain, and
the output common-mode voltage. Calculating the
maximum and minimum voltage required for VN and
VP (the amplifier's input nodes) determines whether
or not the input common-mode range is violated or
not. Four equations are required. Two calculate the
output voltages and two calculate the node voltages
at VN and VP (note that only one of these needs
calculation, as the amplifier forces a virtual short
between the two nodes).
Table 1. Negative-Rail Referenced
Gain (V/V)
VIN+ (V)
-2.0 to 2.0
-1.0 to 1.0
-0.5 to 0.5
-0.25 to 0.25
VIN- (V)
VIN (VPP
)
VOCM (V)
2.5
VOD (VPP
)
VNMIN (V)
0.75
VNMAX (V)
1.75
1
2
4
8
0
0
0
0
4
2
4
4
4
4
2.5
0.5
1.167
0.7
1
2.5
0.3
0.5
2.5
0.167
0.389
21
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
Table 2. Midrail Referenced
Gain (V/V)
VIN+ (V)
0.5 to 4.5
1.5 to 3.5
2.0 to 3.0
2.25 to 2.75
VIN- (V)
2.5
VIN (VPP
)
VOCM (V)
2.5
VOD (VPP
)
VNMIN (V)
2
VNMAX (V)
3
1
2
4
8
4
2
4
4
4
4
2.5
2.5
2.16
2.3
2.83
2.7
2.5
1
2.5
2.5
0.5
2.5
2.389
2.61
gain configurations, and smaller resistor values can
load the amplifier more heavily, resulting in a re-
duction in distortion performance. In addition,
feedback resistor values, coupled with gain require-
ments, determine the value of the gain resistors,
directly impacting the input impedance of the entire
circuit. While there are no strict rules about resistor
selection, these trends can provide qualitative design
guidance.
CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values
in this section provide the optimum high frequency
performance (lowest distortion, flat frequency re-
sponse). Since the THS4500 family of amplifiers is
developed with a voltage feedback architecture, the
choice of resistor values does not have a dominant
effect on bandwidth, unlike a current feedback ampli-
fier. However, resistor choices do have second-order
effects. For optimal performance, the following
feedback resistor values are recommended. In higher
gain configurations (gain greater than two), the
feedback resistor values have much less effect on the
high frequency performance. Example feedback and
gain resistor values are given in the section on basic
design considerations (Table 3).
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
Fully differential amplifiers provide designers with a
great deal of flexibility in a wide variety of appli-
cations. This section provides an overview of some
common circuit configurations and gives some design
guidelines. Designing the interface to an ADC, driving
lines differentially, and filtering with fully differential
amplifiers are a few of the circuits that are covered.
Amplifier loading, noise, and the flatness of the
frequency response are three design parameters that
should be considered when selecting feedback re-
sistors. Larger resistor values contribute more noise
and can induce peaking in the ac response in low
BASIC DESIGN CONSIDERATIONS
The circuits in Figures 75 through 78 are used to
highlight basic design considerations for fully differen-
tial amplifier circuit designs.
Table 3. Resistor Values for Balanced Operation in Various Gain Configurations
VOD
Gain ǒ Ǔ
VIN
R2 & R4 (Ω)
R1 (Ω)
R3 (Ω)
RT (Ω)
1
392
499
412
523
215
665
274
681
147
698
383
487
187
634
249
649
118
681
54.9
53.6
60.4
52.3
56.2
52.3
64.9
52.3
1
2
392
2
1.3k
1.3k
3.32k
1.3k
6.81k
5
5
10
10
22
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
R1
R3
R2
1
R2
R1
RT +
β1 +
K +
R2 + R4
K
1–
(6)
2(1)K)
V
n
1
RS
V
–
−
+
out+
+
−
R3
ǒ
TǓ
R3 + R1 * Rs || R
R
S
V
out−
V
P
R3 ) RT || RS
R3 ) RT || RS ) R4
R1
R1 ) R2
V
OCM
R
T
β2 +
V
S
(7)
R4
VOD
VS
1–β2
β1 ) β2
RT
RT ) RS
+ 2ǒ Ǔǒ Ǔ
(8)
(9)
Figure 78.
VOD
VIN
1–β2
+ 2ǒ Ǔ
β1 ) β2
Equations for calculating fully differential amplifier
resistor values in order to obtain balanced operation
in the presence of a 50-Ω source impedance are
given in equations 6 through 9.
For more detailed information about balance in fully
differential amplifiers, see Fully Differential Amplifiers,
referenced at the end of this data sheet.
loading can negatively impact the amplifier lin-
earity. Filtering in the feedback path does not
have this effect.
INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
•
•
AC-coupling allows easier circuit design. If
dc-coupling is required, be aware of the excess
power dissipation that can occur due to
level-shifting the output through the output com-
mon-mode voltage control.
Do not terminate the output unless required.
Many open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop
fully differential amplifiers drive a specific output
voltage regardless of the load impedance pres-
ent. Terminating the output of a fully differential
amplifier with a heavy load adversely effects the
amplifier's linearity.
The THS4500 family of amplifiers are designed
specifically
to
interface
to
today's
highest-performance analog-to-digital converters.
This section highlights the key concerns when
interfacing to an ADC and provides example
ADC/fully differential amplifier interface circuits.
Key design concerns when interfacing to an
analog-to-digital converter:
•
Terminate the input source properly. In
high-frequency receiver chains, the source feed-
ing the fully differential amplifier requires a
specific load impedance (e.g., 50Ω ).
•
Design a symmetric printed-circuit board layout.
Even-order distortion products are heavily influ-
enced by layout, and careful attention to a
symmetric layout will minimize these distortion
products.
•
Comprehend the VOCM input drive requirements.
Determine if the ADC's voltage reference can
provide the required amount of current to move
VOCM to the desired value. A buffer may be
needed.
•
Minimize inductance in power supply decoupling
traces and components. Poor power supply de-
coupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power supply
pins. Thus, decoupling capacitors should be
placed in a manner that minimizes the impedance
of the current loop.
Use separate analog and digital power supplies
and grounds. Noise (bounce) in the power
supplies (created by digital switching currents)
can couple directly into the signal path, and
power supply noise can create higher distortion
products as well.
•
•
Decouple the VOCM pin to eliminate the antenna
effect. VOCM is a high-impedance node that can
act as an antenna. A large decoupling capacitor
on this node eliminates this problem.
Be cognizant of the input common-mode range. If
the input signal is referenced around the negative
power supply rail (e.g., around ground on a single
5 V supply), then the THS4500/1 accommodates
the input signal. If the input signal is referenced
around midrail, choose the THS4502/3 for the
best operation.
Packaging makes a difference at higher fre-
quencies. If possible, choose the smaller, ther-
mally enhanced MSOP package for the best
performance. As a rule, lower junction tempera-
tures provide better performance. If possible, use
a thermally enhanced package, even if the power
•
•
•
Use care when filtering. While an RC low-pass
filter may be desirable on the output of the
amplifier to filter broadband noise, the excess
23
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THS4505
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
dissipation is relatively small compared to the
maximum power dissipation rating to achieve the
best results.
C
F
R
S
R
g
R
f
•
Comprehend the effect of the load impedance
seen by the fully differential amplifier when per-
forming system-level intercept point calculations.
Lighter loads (such as those presented by an
ADC) allow smaller intercept points to support the
same level of intermodulation distortion perform-
ance.
5 V
V
R
S
T
5 V
10 µF 0.1 µF
R
iso
+
ADS5421
−
OCM
IN
V
14 Bit/40 MSps
+
IN
−
CM
1 µF
THS4501
R
iso
R
g
R
f
EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
C
F
0.1 µF
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at
the output of the data converter. Two representative
circuits shown below highlight single-supply operation
and split supply operation. Specific feedback resistor,
gain resistor, and feedback capacitor values are not
specified, as their values depend on the frequency of
interest. Information on calculating these values can
be found in the applications material above.
Using the THS4501 With the ADS5421
Figure 80.
FULLY DIFFERENTIAL LINE DRIVERS
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers.
Their high power supply voltage rating (16.5 V
absolute maximum) allows operation on a single 12-V
or a single 15-V supply. The high supply voltage,
coupled with the ability to provide differential outputs
enables the ability to drive 26 VPP into reasonably
heavy loads (250 Ω or greater). The circuit in
Figure 81 illustrates the THS4500 family of devices
used as high speed line drivers. For line driver
applications, close attention must be paid to thermal
design constraints due to the typically high level of
power dissipation.
C
F
R
S
R
g
R
f
5 V
V
R
T
S
5 V
10 µF 0.1 µF
R
R
iso
+
V
IN
IN
−
OCM
ADS5410
12 Bit/80 MSps
+
−
CM
1 µF
THS4503
iso
10 µF 0.1 µF
−5 V
R
g
0.1 µF
C
G
R
f
R
R
f
R
g
S
15 V
C
C
R
F
S
T
R
R
iso
V
S
+
V
OCM
−
R
V
DD
L
THS4504
Using the THS4503 With the ADS5410
+
−
0.1 µF
iso
C
S
Figure 79.
R
f
V
OD
= 26 V
PP
R
g
C
G
Fully Differential Line Driver With High Output Swing
Figure 81.
24
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SLOS363C–AUGUST 2002–REVISED MARCH 2004
FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
set the default output common-mode voltage to
midrail. A voltage applied to the VOCM pin alters the
output common-mode voltage as long as the source
has the ability to provide enough current to overdrive
the two 50-kΩ resistors. This phenomenon is de-
picted in the VOCM equivalent circuit diagram. The
table contains some representative examples to aid in
determining the current drive requirement for the
VOCM voltage source. This parameter is especially
important when using the reference voltage of an
analog-to-digital converter to drive VOCM. Output cur-
rent drive capabilities differ from part to part, so a
voltage buffer may be necessary in some appli-
cations.
Similar to their single-ended counterparts, fully differ-
ential amplifiers have the ability to couple filtering
functionality with voltage gain. Numerous filter top-
ologies can be based on fully differential amplifiers.
Several of these are outlined in A Differential Circuit
Collection, (SLOA064) referenced at the end of this
data sheet. The circuit below depicts a simple
two-pole low-pass filter applicable to many different
types of systems. The first pole is set by the resistors
and capacitors in the feedback paths, and the second
pole is set by the isolation resistors and the capacitor
across the outputs of the isolation resistors.
V
S+
C
F1
R = 50 kΩ
R = 50 kΩ
2 V
− V − V
S+
R
R
R
S
OCM
S−
g1
f1
I
IN
=
V
OCM
R
R
R
iso
R
T
I
IN
V
S
+
−
−
+
V
C
O
R
g2
V
S−
iso
Equivalent Input Circuit for V
R
f2
OCM
Figure 83.
C
F2
A Two-Pole, Low-Pass Filter Design Using a Fully
Differential Amplifier With Poles Located at:
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal.
As shown in the equivalent circuit diagram, the VOCM
input has a high impedance associated with it,
dictated by the two 50-kΩ resistors. While the high
impedance allows for relaxed drive requirements, it
also allows the pin and any associated printed-circuit
board traces to act as an antenna. For this reason, a
decoupling capacitor is recommended on this node
for the sole purpose of filtering any high frequency
noise that could couple into the signal path through
the VOCM circuitry. A 0.1-µF or 1-µF capacitance is a
reasonable value for eliminating a great deal of
broadband interference, but additional, tuned decoup-
ling capacitors should be considered if a specific
source of electromagnetic or radio frequency inter-
ference is present elsewhere in the system. Infor-
mation on the ac performance (bandwidth, slew rate)
of the VOCM circuitry is included in the specification
table and graph section.
−1
−1
P1 = (2πR C ) in Hz and P2 = (4πR C) in Hz
f
F
iso
Figure 82.
Often times, filters like these are used to eliminate
broadband noise and out-of-band distortion products
in signal acquisition systems. It should be noted that
the increased load placed on the output of the
amplifier by the second low-pass filter has a detri-
mental effect on the distortion performance. The
preferred method of filtering is using the feedback
network, as the typically smaller capacitances re-
quired at these points in the circuit do not load the
amplifier nearly as heavily in the pass-band.
SETTING THE OUTPUT COMMON-MODE
VOLTAGE WITH THE VOCM INPUT
The output common-mode voltage pin provides a
critical function to the fully differential amplifier; it
accepts an input voltage and reproduces that input
voltage as the output common-mode voltage. In other
words, the VOCM input provides the ability to level-shift
the outputs to any voltage inside the output voltage
swing of the amplifier.
Since the VOCM pin provides the ability to set an
output common-mode voltage, the ability for in-
creased power dissipation exists. While this does not
pose a performance problem for the amplifier, it can
cause additional power dissipation of which the sys-
tem designer should be aware. The circuit shown in
Figure 84 demonstrates an example of this phenom-
enon. For a device operating on a single 5-V supply
with an input signal referenced around ground and an
output common-mode voltage of 2.5 V, a dc potential
exists between the outputs and the inputs of the
A description of the input circuitry of the VOCM pin is
shown below to facilitate an easier understanding of
the VOCM interface requirements. The VOCM pin has
two 50-kΩ resistors between the power supply rails to
25
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
device. The amplifier sources current into the
feedback network in order to provide the circuit with
the proper operating point. While there are no serious
effects on the circuit performance, the extra power
dissipation may need to be included in the system's
power budget.
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
V
OCM
I
1
=
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
R
f1
+ R + R || R
g1 S T
DC Current Path to Ground
R
R
f1
R
S
g1
The THS4500 family of devices features unpre-
cedented distortion performance for monolithic fully
differential amplifiers. This section focuses on the
fundamentals of distortion, circuit techniques for re-
ducing nonlinearity, and methods for equating distor-
tion of fully differential amplifiers to desired linearity
specifications in RF receiver chains.
2.5-V DC
5 V
R
T
V
S
+
−
+
R
L
V
= 2.5 V
OCM
−
2.5-V DC
DC Current Path to Ground
Amplifiers are generally thought of aslinear devices.
In other words, the output of an amplifier is a linearly
scaled version of the input signal applied to it. In
reality, however, amplifier transfer functions are
nonlinear. Minimizing amplifier nonlinearity is a pri-
mary design goal in many applications.
R
R
f2
g2
V
OCM
I
2
=
R
+ R
g2
f2
Depiction of DC Power Dissipation Caused By
Output Level-Shifting in a DC-Coupled Circuit
Intercept points are specifications that have long
been used as key design criteria in the RF communi-
cations world as a metric for the intermodulation
distortion performance of a device in the signal chain
(e.g., amplifiers, mixers, etc.). Use of the intercept
point, rather than strictly the intermodulation distor-
tion, allows for simpler system-level calculations.
Intercept points, like noise figures, can be easily
cascaded back and forth through a signal chain to
determine the overall receiver chain's intermodulation
distortion performance. The relationship between
intermodulation distortion and intercept point is de-
picted in Figure 85 and Figure 86.
Figure 84.
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
The THS4500 family of fully differential amplifiers
contains devices that come with and without the
power-down option. Even-numbered devices have
power-down capability, which is described in detail
here.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (i.e. an internal pullup resistor is present),
putting the amplifier in the power-on mode of oper-
ation. To turn off the amplifier in an effort to conserve
power, the power-down pin can be driven towards the
negative rail. The threshold voltages for power-on
and power-down are relative to the supply rails and
given in the specification tables. Above the enable
threshold voltage, the device is on. Below the disable
threshold voltage, the device is off. Behavior in
between these threshold voltages is not specified.
P
O
P
O
∆f = f − f1
c
c
∆f = f2 − f
c
c
IMD = P − P
O
3
S
P
S
P
S
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors.
f − 3∆f f1
f
f2
f + 3∆f
c
c
c
f − Frequency − MHz
Figure 85.
26
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
Ť
Ť
IMD3
2
P
ǒ Ǔwhere
(10)
(11)
OIP3 + PO )
OUT
(dBm)
1X
V2Pdiff
P + 10 logǒ Ǔ
OIP
O
3
2RL 0.001
#IMPLIED. NOTE: Po is the output power of a
single tone, RL is the differential load resist-
ance, and VP(diff) is the differential peak
voltage for a single tone.
P
O
As can be seen in the equation, when a higher
impedance is used, the same level of intermodulation
distortion performance results in a lower intercept
point. Therefore, it is important to comprehend the
impedance seen by the output of the fully differential
amplifier when selecting a minimum intercept point.
The graphic below shows the relationship between
the strict definition of an intercept point with a
normalized, or equivalent, intercept point for the
THS4502.
IMD
IIP
3
P
IN
3
(dBm)
3X
P
S
Figure 86.
60
Gain = 1
R = 499 Ω
f
Due to the intercept point's ease of use in system
level calculations for receiver chains, it has become
the specification of choice for guiding distor-
tion-related design decisions. Traditionally, these sys-
tems use primarily class-A, single-ended RF ampli-
fiers as gain blocks. These RF amplifiers are typically
designed to operate in a 50-Ω environment, just like
the rest of the receiver chain. Since intercept points
are given in dBm, this implies an associated im-
pedance (50 Ω).
50
40
30
20
V
V
= 2 V
PP
= ± 5 V
O
S
200 kHz Tone Spacing
Normalized to 50 Ω
Normalized to 200 Ω
R
L
= 800 Ω
10
0
0
20
40
60
80
100
However, with a fully differential amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to their outputs regardless of the impedance present,
it is important to comprehend this when evaluating
the intercept point of a fully differential amplifier. The
THS4500 series of devices yields optimum distortion
performance when loaded with 200 Ω to 1 kΩ, very
similar to the input impedance of an analog-to-digital
converter over its input frequency band. As a result,
terminating the input of the ADC to 50 Ω can actually
be detrimental to system performance.
f − Frequency − MHz
Figure 87.
Comparing specifications between different device
types becomes easier when a common impedance
level is assumed. For this reason, the intercept points
on the THS4500 family of devices are reported
normalized to a 50-Ω load impedance.
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
This discontinuity between open-loop, class-A ampli-
fiers and closed-loop, class-AB amplifiers becomes
apparent when comparing the intercept points of the
two types of devices. Equation 10 gives the definition
of an intercept point, relative to the intermodulation
distortion.
Noise analysis in fully differential amplifiers is anal-
ogous to noise analysis in single-ended amplifiers.
The same concepts apply. Below, a generic circuit
diagram consisting of a voltage source, a termination
resistor, two gain setting resistors, two feedback
resistors, and a fully differential amplifier is shown,
including all the relevant noise sources. From this
circuit, the noise factor (F) and noise figure (NF) are
calculated. The figures indicate the appropriate
scaling factor for each of the noise sources in two
different cases. The first case includes the termin-
ation resistor, and the second, simplified case as-
27
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
sumes that the voltage source is properly terminated
by the gain-setting resistors. With these scaling
factors, the amplifier's input noise power (NA) can be
calculated by summing each individual noise source
with its scaling factor. The noise delivered to the
amplifier by the source (NI) and input noise power are
used to calculate the noise factor and noise figure as
shown in equations 23 through 27.
2
Rg
Rg
ȡ
ȣ
(18)
)
2
R
(e )
ȧ
R ȧ
ni
f
s
Rg )
Ȣ
2
Ȥ
2
2
R
g
(i )
ni
(19)
2
R
g
2
(i )
ii
(20)
(21)
2
e
g
e
f
R
g
R
f
Rg
N
i
N
A
ǒ Ǔ
2
4kTR
f
Rf
2
S
e
i
n
Rg
ȧR )
ȡ
ȣ
(22)
N
N
i
o
2
4kTR
R
ȧ
g
s
2
g
R
s
+
S
o
R
fully-diff
amp
−
t
i
ni
Figure 90. Scaling Factors for Individual
N
o
Noise Sources Assuming No Termination
Resistance is Used (e.g., RT is open).
e
s
e
t
i
ii
2
ȡ
ȣ
e
g
e
f
2RtRg
R
g
R
f
ȧ
ȧ
Rt)2Rg
(23)
Ni + 4kTRs
ȧ
ȧ
2RtRg
R )
ȧ s R )2R ȧ
g
t
Figure 88. Noise Sources in a Fully
Differential Amplifier Circuit
Ȣ
Ȥ
Figure 91. Input Noise With a Termination Re-
sistor
2
ȡ
ȣ
ȧ
Rg
RsRt
Rg
)
ȧ
2
(12)
2
ȢR
Ȥ
(e )
ni
f
Rg )
2Rg
ǒ
Ǔ
2 Rs)Rt
(24)
ǒ Ǔ
Ni + 4kTRs
Rs ) 2Rg
2
2
Figure 92. Input Noise Assuming
No Termination Resistor
(i )
ni
R
(13)
(14)
g
2
2
(i )
ii
R
g
2
Noise Factor and Noise Figure Calculations
2RsRG
Rs)2Rg
ȡ
ȧ
ȣ
ǒ
Ǔ
NA + S Noise Source Scale Factor
4kTR
(25)
(26)
(27)
t
(15)
ȧ
2RsRg
Rt )
Ȣ
Ȥ
Rs)2Rg
NA
F + 1 )
NI
2
Rg
NF + 10 log (F)
ǒ Ǔ
2
(16)
(17)
4kTR
f
Rf
PC BOARD LAYOUT TECHNIQUES FOR
OPTIMAL PERFORMANCE
2
ȡ
Rg
RsRt
2 Rs)Rt
ȣ
ȧ
Achieving optimum performance with a high fre-
quency amplifier-like devices in the THS4500 family
requires careful attention to board layout parasitic and
external component types.
2
4kTR
g
ȧR )
g
ǒ
Ǔ
Figure 89. Scaling Factors for Individual
Noise Sources Assuming a Finite
Value Termination Resistor
Recommendations that optimize performance include:
28
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
•
•
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
Minimize the distance (< 0.25”) from the power
supply pins to high frequency 0.1-µF decoupling
capacitors. At the device pins, the ground and
power plane layout should not be in close proxim-
ity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between
the pins and the decoupling capacitors. The
power supply connections should always be
decoupled with these capacitors. Larger (6.8 µF
or more) tantalum decoupling capacitors, effec-
tive at lower frequency, should also be used on
the main supply pins. These may be placed
somewhat farther from the device and may be
shared among several devices in the same area
of the PC board. The primary goal is to minimize
the impedance seen in the differential-current
return paths.
Careful selection and placement of external
components preserve the high frequency per-
formance of the THS4500 family. Resistors
should be a very low reactance type. Sur-
face-mount resistors work best and allow a tighter
overall layout. Metal-film and carbon composition,
axially-leaded resistors can also provide good
high frequency performance. Again, keep their
leads and PC board trace length as short as
possible. Never use wirewound type resistors in a
high frequency application. Since the output pin
and inverting input pins are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed
close to the gain-setting resistors. Even with a
low parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
performance. Good axial metal-film or sur-
face-mount resistors have approximately 0.2 pF
in shunt with the resistor. For resistor values >
2.0 kΩ, this parasitic capacitance can add a pole
and/or a zero below 400 MHz that can effect
circuit operation. Keep resistor values as low as
possible, consistent with load driving consider-
ations.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an RS since the THS4500 family is nominally
compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss intrin-
sic to a doubly-terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
A 50-Ω environment is normally not necessary
onboard, and in fact, a higher impedance en-
vironment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance defined based on board
material and trace dimensions, a matching series
resistor into the trace from the output of the
THS4500 family is used as well as a terminating
shunt resistor at the input of the destination
device.
•
•
•
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device:
this total effective impedance should be set to
match the trace impedance. If the 6-dB attenu-
ation of a doubly terminated transmission line is
unacceptable,
a
long
trace
can
be
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of
the destination device is low, there is some signal
attenuation due to the voltage divider formed by
the series output into the terminating impedance.
Socketing a high speed part like the THS4500
family is not recommended. The additional lead
length and pin-to-pin capacitance introduced by
the socket can create an extremely troublesome
parasitic network which can make it almost im-
possible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS4500 family parts directly onto the board.
•
PowerPAD DESIGN CONSIDERATIONS
The THS4500 family is available in
a
ther-
mally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 93(a) and Figure 93(b)]. This arrangement
results in the lead frame being exposed as a thermal
•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
29
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
pad on the underside of the package [see Fig-
ure 93(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal per-
formance can be achieved by providing a good
thermal path away from the thermal pad.
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS4500 family IC. These additional vias
may be larger than the 13-mil diameter vias
directly under the thermal pad. They can be
larger because they are not in the thermal pad
area to be soldered so that wicking is not a
problem.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing oper-
ation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer. There-
fore, the holes under the THS4500 family
PowerPAD package should make their connec-
tion to the internal ground plane with a complete
connection around the entire circumference of the
plated-through hole.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechan-
ical methods of heatsinking.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
6. The top-side solder mask should leave the ter-
minals of the package and the thermal pad area
with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This prevents solder from
being pulled away from the thermal pad area
during the reflow process.
Figure 93. Views of Thermally Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
0.205
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
0.060
0.017
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard sur-
face-mount component. This results in a part that
is properly installed.
Pin 1
0.013
0.030
0.075
0.025 0.094
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
0.035
0.040
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer
must take care to ensure that the design does not
violate the absolute maximum junction temperature of
the device. Failure may result if the absolute maxi-
mum junction temperature of 150°C is exceeded. For
best performance, design for a maximum junction
temperature of 125°C. Between 125°C and 150°C,
damage does not occur, but the performance of the
amplifier begins to degrade.
0.010
vias
Top View
Figure 94. View of Thermally Enhanced Package
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as
shown in Figure 94. There should be etch for the
leads as well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad.
These holes should be 13 mils in diameter. Keep
30
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
The thermal characteristics of the device are dictated
by the package and the PC board. Maximum power
dissipation for a given package can be calculated
using the following formula.
3.5
3
8-Pin DGN Package
2.5
2
Tmax–TA
qJA
(28)
PDmax
+
8-Pin D Package
1.5
1
Where:
P
is the maximum power dissipation in the amplifier (W).
Dmax
T
is the absolute maximum junction temperature (°C).
max
T is the ambient temperature (°C).
A
0.5
0
θ
θ
= θ + θ
JA
JC CA
is the thermal coefficient from the silicon junctions to the
JC
−40
−20
0
20
40
60
80
case (°C/W).
is the thermal coefficient from the case to ambient air
T
− Ambient Temperature − °C
A
θ
CA
θ
θ
Τ
= 170°C/W for 8-Pin SOIC (D)
= 58.4°C/W for 8-Pin MSOP (DGN)
= 150°C, No Airflow
JA
(°C/W).
JA
J
For systems where heat dissipation is more critical,
the THS4500 family of devices is offered in an 8-pin
MSOP with PowerPAD. The thermal coefficient for
the MSOP PowerPAD package is substantially im-
proved over the traditional SOIC. Maximum power
dissipation levels are depicted in the graph for the
two packages. The data for the DGN package as-
sumes a board layout that follows the PowerPAD
layout guidelines referenced above and detailed in
the PowerPAD application notes in the Additional
Reference Materialsection at the end of the data
sheet.
Figure 95. Maximum Power Dissipation
vs Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power dissi-
pation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
31
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
DRIVING CAPACITIVE LOADS
POWER SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however,
the load capacitance should be isolated by two
isolation resistors in series with the output. The
requisite isolation resistor size depends on the value
of the capacitance, but 10 Ω to 25 Ω is a good place
to begin the optimization process. Larger isolation
resistors decrease the amount of peaking in the
frequency response induced by the capacitive load,
but this comes at the expense of larger voltage drop
across the resistors, increasing the output swing
requirements of the system.
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of per-
formance.
1. Place decoupling capacitors as close to the
power supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply.
2. Placement priority should be as follows: smaller
capacitors should be closer to the device.
R
f
3. Use of solid power and ground planes is rec-
ommended to reduce the inductance along power
supply return current paths.
V
S
R
g
R
S
R
iso
+
−
−
V
S
C
L
R
T
4. Recommended values for power supply decoup-
ling include 10-µF and 0.1-µF capacitors for each
supply. A 1000-pF capacitor can be used across
the supplies as well for extremely high frequency
return currents, but often is not required.
+
R
iso
−V
S
Riso = 10 − 25 Ω
R
f
R
g
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
Use of Isolation Resistors With a Capacitive Load.
Texas Instruments is committed to providing its cus-
tomers with the highest quality of applications sup-
port. To support this goal, an evaluation board has
been developed for the THS4500 family of fully
differential amplifiers. The evaluation board can be
obtained by ordering through the Texas Instruments
web site, www.ti.com, or through your local Texas
Instruments sales representative. The schematic for
the evaluation board is shown in Figure 97 with
default component values. Unpopulated footprints are
shown to provide insight into design flexibility.
Figure 96.
C4
C0805
Computer simulation of circuit performance using
SPICE is often useful when analyzing the perform-
ance of analog circuits and systems. This is particu-
larly true for video and RF amplifier circuits where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS4500 family of devices is available
through the Texas Instruments web site (www.ti.com).
The Product Information Center (PIC) is available for
design assistance and detailed product information.
R4
R0805
PD
V
S
U1
THS450X
4
J2
J1
C5
C0805
J2
J3
3
_
C1
C0805
R6
R2
7
1
8
R0805
R0805
R0805
C7
C0805
R0805
R1
J3
C2
R1206
C0805
+
5
R3
6
R7
2
PwrPad
C6
C0805
−V
S
V
OCM
R5 R0805
C3
C0805
These models do
a
good job of predicting
small-signal ac and transient performance under a
wide variety of operating conditions. They are not
intended to model the distortion characteristics of the
amplifier, nor do they attempt to distinguish between
the package types in their small-signal ac perform-
ance. Detailed information about what is and is not
modeled is contained in the model file itself.
J2
J4
R8
4
5
3
1
R0805
J3
R9
R11
R1206
R0805
R0805
6
R9
T1
Simplified Schematic of the Evaluation Board. Power
Supply Decoupling, V
Not Shown
and Power Down Circuitry
OCM,
Figure 97.
32
THS4504
THS4505
www.ti.com
SLOS363C–AUGUST 2002–REVISED MARCH 2004
ADDITIONAL REFERENCE MATERIAL
Instruments
February 2001.
Carter, Bruce. A Differential Op-Amp Circuit Col-
lection. application report, (SLOA064).
Carter, Bruce. Differential Op-Amp Single-Supply
Analog
Applications
Journal,
•
•
•
•
PowerPAD Made Easy, application brief,
(SLMA004).
PowerPAD Thermally Enhanced Package, techni-
cal brief, (SLMA002).
•
•
Design
(SLOA072).
Technique,
application
report,
Karki,
James.
Fully
Differential
Ampli-
fiers.application report, (SLOA054D).
•
Karki, James. Designing for Low Distortion with
High-Speed Op Amps. Texas Instruments Analog
Applications Journal, July 2001.
Karki, James. Fully Differential Amplifiers Appli-
cations: Line Termination, Driving High-Speed
ADCs, and Differential Transmission Lines. Texas
33
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
PACKAGING INFORMATION
Orderable Device
THS4504D
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4504DGK
THS4504DGKR
THS4504DGKRG4
THS4504DGN
MSOP
MSOP
MSOP
DGK
DGK
DGK
DGN
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4504DGNG4
THS4504DGNR
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4504DGNRG4
MSOP-
Power
PAD
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4504DR
THS4504DRG4
THS4505D
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
8
8
8
8
8
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4505DGK
THS4505DGKR
THS4505DGKRG4
THS4505DGN
MSOP
MSOP
MSOP
DGK
DGK
DGK
DGN
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4505DGNG4
THS4505DGNR
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4505DGNRG4
MSOP-
Power
PAD
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4505DR
ACTIVE
ACTIVE
SOIC
D
D
8
8
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4505DRG4
SOIC
Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Feb-2006
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 2
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