THS4509-Q1 [TI]
WIDEBAND LOW-NOISE LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIER; 宽带低，噪声低失真全差动放大器
| 型号： | THS4509-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | WIDEBAND LOW-NOISE LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIER |
| 文件： | 总37页 (文件大小：1687K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4509-Q1
www.ti.com ........................................................................................................................................................................................... SLOS547–NOVEMBER 2008
WIDEBAND LOW-NOISE LOW-DISTORTION FULLY DIFFERENTIAL AMPLIFIER
1
FEATURES
DESCRIPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Fully Differential Architecture
Centered Input Common-Mode Range
Minimum Gain of 2 V/V (6 dB)
Bandwidth: 1900 MHz
The THS4509 is
a
wideband, fully differential
operational
amplifier designed for 5-V
data-acquisition systems. It has very low noise at
1.9 nV/√Hz, and extremely low harmonic distortion of
–75-dBc HD2 and –80-dBc HD3 at 100 MHz with
2 Vpp, G = 10 dB, and 1-kΩ load. Slew rate is very
high at 6600 V/µs and with settling time of 2 ns to 1%
(2-V step), it is ideal for pulsed applications. It is
designed for minimum gain of 6 dB but is optimized
for gain of 10 dB.
Slew Rate: 6600 V/µs
1% Settling Time: 2 ns
HD2: –75 dBc at 100 MHz
HD3: –80 dBc at 100 MHz
OIP2: 73 dBm at 70 MHz
To allow for dc coupling to analog-to-digital
converters (ADCs), its unique output common-mode
control circuit maintains the output common-mode
voltage within 3-mV offset (typ) from the set voltage,
when set within 0.5 V of mid-supply, with less than
4-mV differential offset voltage. The common-mode
set point is set to mid-supply by internal circuitry,
which may be overdriven from an external source.
OIP3: 37 dBm at 70 MHz
Input Voltage Noise: 1.9 nV/√Hz (f > 10 MHz)
Noise Figure: 17.1 dB
Output Common-Mode Control
Power Supply:
–
–
Voltage: 3 V (±1.5 V) to 5 V (±2.5 V)
Current: 37.7 mA
The input and output are optimized for best
performance with their common-mode voltages set to
mid-supply. Along with high-performance at low
power-supply voltage, this makes for extremely
high-performance single-supply 5-V data-acquisition
systems. The combined performance of the THS4509
in a gain of 10 dB driving the ADS5500 ADC,
sampling at 125 MSPS, is 81-dBc SFDR and
69.1-dBc SNR with a –1-dBFS signal at 70 MHz.
•
Power-Down Capability: 0.65 mA
APPLICATIONS
•
5-V Data Acquisition Systems High Linearity
ADC Amplifier
Wireless Communication
Medical Imaging
Test and Measurement
•
•
•
The THS4509 is offered in a quad 16-pin leadless
QFN package (RGT) and is characterized for
operation over the full automotive temperature range
from –40°C to 125°C.
RELATED PRODUCTS
DEVICE
MINIMUM
GAIN
COMMON-MODE
RANGE OF INPUT(1)
100 Ω
348 Ω
2.5 V
V
IN
From
50 Ω
Source
THS4509
6 dB
0.75 V to 4.25 V
69.8 Ω
(1) Assumes a 5-V single-ended power supply
V
OUT
487 Ω
487 Ω
1:1
To 50 Ω
Test
Equipment
56.3 Ω
THS 4509
100 Ω
0.22 µF
49.9 Ω
CM
69.8 Ω
Open
−2.5 V
348 Ω
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008, Texas Instruments Incorporated
THS4509-Q1
SLOS547–NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
–40°C to 125°C
QFN – RGT
Reel of 3000
THS4509QRGTRQ1
OOSQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VS– to VS+
Supply voltage
6 V
VI
Input voltage
±VS
4 V
VID
IO
Differential input voltage
Output current(1)
200 mA
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature range
Storage temperature range
See Dissipation Rating Table
150°C
TJ
TA
–40°C to 125°C
–65°C to 150°C
2000 V
Tstg
Human-Body Model (HBM)
ESD ratings
Charged-Device Model (CDM)
Machine Model (MM)
1500 V
100 V
(1) The THS4509 incorporates a (QFN) exposed thermal pad on the underside of the chip. This acts as a heatsink and must be connected
to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature, which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about
utilizing the QFN thermally enhanced package.
DISSIPATION RATINGS
POWER RATING
PACKAGE
θJC
θJA
TA ≤ 25°C
TA = 85°C
RGT (16)
2.4°C/W
39.5°C/W
2.3 W
225 mW
2
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DEVICE INFORMATION
RGT PACKAGE
(TOP VIEW)
V
S–
16
15
14
13
NC
PD
V
1
2
3
4
12
11
10
9
V
IN–
OUT+
CM
IN+
V
V
OUT–
CM
6
7
5
8
V
S+
TERMINAL FUNCTIONS
TERMINAL
NO.
DESCRIPTION
NAME
NC
1
No internal connection
Inverting amplifier input
Noninverted amplifier output
VIN–
VOUT+
CM
2
3
4,9
Common-mode voltage input
Positive amplifier power-supply input
Inverted amplifier output
VS+
5, 6, 7, 8
10
VOUT–
VIN+
PD
11
Noninverting amplifier input
12
Power down, PD = logic low puts part into low-power mode, PD = logic high or open for normal operation
VS–
13, 14, 15, 16 Negative amplifier power supply input
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SPECIFICATIONS, VS+ – VS– = 5 V
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, G = 10 dB, CM = open, VO = 2 Vpp, RF = 349 Ω,
RL = 200 Ω differential, TA = 25°C, single-ended input, differential output, input and output referenced to mid-supply
TEST
PARAMETER
AC Performance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
G = 6 dB, VO = 100 mVpp
2.0
1.9
GHz
MHz
G = 10 dB, VO = 100 mVpp
G = 14 dB, VO = 100 mVpp
G = 20 dB, VO = 100 mVpp
G = 20 dB
Small-signal bandwidth
600
275
3
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
Slew rate (differential)
Rise time
GHz
MHz
GHz
V/µs
ns
G = 10 dB, VO = 2 Vpp
G = 10 dB, VO = 2 Vpp
300
1.5
6600
0.5
Fall time
2-V step
0.5
ns
Settling time to 1%
Settling time to 0.1%
2
ns
10
ns
f = 10 MHz
f = 50 MHz
f = 100 MHz
f = 10 MHz
f = 50 MHz
f = 100 MHz
–104
–80
–68
–108
–92
–81
–78
–64
–95
–78
78
Second-order harmonic distortion
Third-order harmonic distortion
dBc
dBc
C
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
200-kHz tone spacing,
RL = 499 Ω
Second-order intermodulation distortion
Third-order intermodulation distortion
dBc
dBc
200-kHz tone spacing,
RL = 499 Ω
200-kHz tone spacing,
RL = 100 Ω, referenced to
50-Ω output
Second-order output intercept point
dBm
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
58
43
38
200-kHz tone spacing,
RL = 100 Ω, referenced to
50-Ω output
Third-order output intercept point
1-dB compression point
dBm
dBm
fC = 70 MHz
12.2
10.8
17.1
1.9
fC = 140 MHz
50-Ω system, 10 MHz
f > 10 MHz
Noise figure
dB
Input voltage noise
Input current noise
DC Performance
nV/√Hz
pA/√Hz
f > 10 MHz
2.2
Open-loop voltage gain (AOL
)
68
1
dB
mV
C
A
B
A
B
A
B
TA = 25°C
4
5
Input offset voltage
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = 25°C
1
mV
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
Average offset current drift
2.6
8
V/°C
15.5
18.5
A
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = 25°C
8
20
1.6
1.6
4
nA/°C
A
3.6
7
TA = –40°C to 125°C
TA = –40°C to 125°C
nA/°C
(1) Test levels: A = 100% tested at 25°C, overtemperature limits by characterization and simulation; B = Limits set by characterization and
simulation; C = Typical value only for information.
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SPECIFICATIONS, VS+ – VS– = 5 V (continued)
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, G = 10 dB, CM = open, VO = 2 Vpp, RF = 349 Ω,
RL = 200 Ω differential, TA = 25°C, single-ended input, differential output, input and output referenced to mid-supply
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
Input
Common-mode input range high
Common-mode input range low
Common-mode rejection ratio
Differential input impedance
Common-mode input impedance
Output
1.75
–1.75
V
B
90
dB
1.35 || 1.77
1.02 || 2.26
MΩ || pF
MΩ || pF
C
C
TA = 25°C
1.2
1.1
1.4
1.4
Each output with 100 Ω to
mid-supply
Maximum output voltage high
Minimum output voltage low
Differential output voltage swing
V
V
V
TA = –40°C to 125°C
TA = 25°C
A
C
–1.4
–1.4
5.6
–1.2
–1.1
Each output with 100 Ω to
mid-supply
TA = –40°C to 125°C
4.8
4.4
TA = –40°C to 125°C
RL = 10 Ω
Differential output current drive
Output balance error
96
–49
0.3
mA
dB
Ω
VO = 100 mV, f = 1 MHz
f = 1 MHz
Closed-loop output impedance
Output Common-Mode Voltage Control
Small-signal bandwidth
Slew rate
700
110
1
MHz
V/µs
V/V
Gain
Output common-mode offset
from CM input
1.25 V < CM < 3.5 V
1.25 V < CM < 3.5 V
5
mV
C
CM input bias current
CM input voltage range
CM input impedance
CM default voltage
±40
–1.5 to 1.5
23 || 1
A
V
kΩ || pF
V
0
Power Supply
Specified operating voltage
3
5
37.7
37.7
37.7
37.7
90
5.25
40.9
41.9
V
C
A
C
TA = 25°C
Maximum quiescent current
Minimum quiescent current
mA
TA = –40°C to 125°C
TA = 25°C
34.5
33.5
mA
dB
TA = –40°C to 125°C
Power-supply rejection (PSRR)
Power Down
Referenced to Vs–
Enable voltage threshold
Disable voltage threshold
Assured on above 2.1 V + VS–
Assured off below 0.7 V + VS–
TA = 25°C
>2.1 + VS–
<0.7 + VS–
0.65
V
V
C
A
0.9
1
Powerdown quiescent current
mA
TA = –40°C to 125°C
PD = VS–
0.65
Input bias current
Input impedance
Turn-on time delay
Turn-off time delay
100
A
kΩ || pF
ns
50 || 2
55
C
Measured to output on
Measured to output off
10
s
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SPECIFICATIONS, VS+ – VS– = 3 V
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, G = 10 dB, CM = open, VO = 1 Vpp, RF = 349 Ω,
RL = 200 Ω differential, TA = 25°C, single-ended input, differential output, input and output referenced to mid-supply
TEST
PARAMETER
AC Performance
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
G = 6 dB, VO = 100 mVpp
1.9
1.6
GHz
MHz
G = 10 dB, VO = 100 mVpp
G = 14 dB, VO = 100 mVpp
G = 20 dB, VO = 100 mVpp
G = 20 dB
Small-signal bandwidth
625
260
3
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
Slew rate (differential)
Rise time
GHz
MHz
GHz
V/µs
ns
G = 10 dB, VO = 1 Vpp
G = 10 dB, VO = 1 Vpp
400
1.5
3500
0.25
0.25
1
Fall time
2-V step
ns
Settling time to 1%
Settling time to 0.1%
ns
10
ns
f = 10 MHz
f = 50 MHz
f = 100 MHz
f = 10 MHz
f = 50 MHz
f = 100 MHz
–107
–83
–60
–87
–65
–54
–77
–54
–77
–62
72
Second-order harmonic distortion
Third-order harmonic distortion
dBc
dBc
C
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
200-kHz tone spacing,
RL = 499 Ω
Second-order intermodulation distortion
Third-order intermodulation distortion
Second-order output intercept point
Third-order output intercept point
1-dB compression point
dBc
dBc
200-kHz tone spacing,
RL = 499 Ω
200-kHz tone spacing
RL = 100 Ω
dBm
dBm
dBm
52
38.5
30
200-kHz tone spacing
RL = 100 Ω
fC = 70 MHz
2.2
fC = 140 MHz
50-Ω system, 10 MHz
f > 10 MHz
0.25
17.1
1.9
Noise figure
dB
Input voltage noise
Input current noise
DC Performance
nV/√Hz
pA/√Hz
f > 10 MHz
2.2
Open-loop voltage gain (AOL
)
68
1
dB
mV
Input offset voltage
TA = 25°C
Average offset voltage drift
Input bias current
Average bias current drift
Input offset current
Average offset current drift
TA = –40°C to 125°C
TA = 25°C
2.6
6
V/°C
A
C
TA = –40°C to 125°C
TA = 25°C
20
1.6
4
nA/°C
A
TA = –40°C to 125°C
nA/°C
(1) Test levels: A = 100% tested at 25°C, overtemperature limits by characterization and simulation; B = Limits set by characterization and
simulation; C = Typical value only for information.
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SPECIFICATIONS, VS+ – VS– = 3 V (continued)
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, G = 10 dB, CM = open, VO = 1 Vpp, RF = 349 Ω,
RL = 200 Ω differential, TA = 25°C, single-ended input, differential output, input and output referenced to mid-supply
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
Input
Common-mode input range high
Common-mode input range low
Common-mode rejection ratio
Differential input impedance
Common-mode input impedance
Output
0.75
–0.75
V
V
B
80
dB
1.35 || 1.77
1.02 || 2.26
MΩ || pF
MΩ || pF
C
C
Each output with 100 Ω to
mid-supply
Maximum output voltage high
Minimum output voltage low
TA = 25°C
TA = 25°C
0.45
V
V
Each output with 100 Ω to
mid-supply
–0.45
C
Differential output voltage swing
Differential output current drive
Output balance error
1.8
50
V
mA
dB
Ω
RL = 10 Ω
VO = 100 mV, f = 1 MHz
f = 1 MHz
–49
0.3
Closed-loop output impedance
Output Common-Mode Voltage Control
Small-signal bandwidth
Slew rate
570
60
1
MHz
V/µs
V/V
Gain
Output common-mode offset
from CM input
1.25 V < CM < 3.5 V
1.25 V < CM < 3.5 V
4
mV
C
CM input bias current
CM input voltage range
CM input impedance
CM default voltage
±40
–1.5 to 1.5
20 || 1
A
V
kΩ || pF
V
0
Power Supply
Specified operating voltage
Quiescent current
3
34.8
70
V
C
A
C
TA = 25°C
mA
dB
Power-supply rejection (PSRR)
Power Down
Referenced to Vs–
Enable voltage threshold
Disable voltage threshold
Power-down quiescent current
Input bias current
Assured on above 2.1 V + VS–
Assured off below 0.7 V + VS–
>2.1 + VS–
<0.7 + VS–
0.46
V
V
mA
PD = VS–
65
A
kΩ || pF
ns
C
Input impedance
50 || 2
100
Turn-on time delay
Measured to output on
Measured to output off
Turn-off time delay
10
s
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TYPICAL CHARACTERISTICS
TYPICAL AC PERFORMANCE: VS+ – VS– = 5 V
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
differential, G = 10 dB, single-ended input, input and output referenced to midrail
Small-Signal Frequency Response
Large Signal Frequency Response
Figure 1
Figure 2
HD2, G = 6 dB, VOD = 2 VPP
HD3, G = 6 dB, VOD = 2 VPP
HD2, G = 10 dB, VOD = 2 VPP
HD3, G = 10 dB, VOD = 2 VPP
HD2, G = 14 dB, VOD = 2 VPP
HD3, G = 14 dB, VOD = 2 VPP
HD2, G = 10 dB
vs Frequency
Figure 3
vs Frequency
Figure 4
vs Frequency
Figure 5
vs Frequency
Figure 6
vs Frequency
Figure 7
Harmonic Distortion
vs Frequency
Figure 8
vs Output Voltage
vs Output Voltage
vs Common-Mode Output Voltage
vs Common-Mode Output Voltage
vs Frequency
Figure 9
HD3, G = 10 dB
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
Figure 42
Figure 43
HD2, G = 10 dB
HD3, G = 10 dB
IMD2, G = 6 dB, VOD = 2 VPP
IMD3, G = 6 dB, VOD = 2 VPP
IMD2, G = 10 dB, VOD = 2 VPP
IMD3, G = 10 dB, VOD = 2 VPP
IMD2, G = 14 dB, VOD = 2 VPP
IMD3, G = 14 dB, VOD = 2 VPP
OIP2
vs Frequency
vs Frequency
Intermodulation Distortion
Output Intercept Point
vs Frequency
vs Frequency
vs Frequency
vs Frequency
OIP3
vs Frequency
0.1-dB Flatness
S-Parameters
vs Frequency
Transition Rate
vs Output Voltage
Transient Response
Settling Time
Rejection Ratio
vs Frequency
vs Frequency
Output Impedance
Overdrive Recovery
Output Voltage Swing
Turn-Off Time
vs Load Resistance
Turn-On Time
Input Offset Voltage
Open-Loop Gain and Phase
Input Referred Noise
Noise Figure
vs Input Common-Mode Voltage
vs Frequency
vs Frequency
vs Frequency
Quiescent Current
Power-Supply Current
Output Balance Error
CM Input Impedance
vs Supply Voltage
vs Supply Voltage in Power-Down Mode
vs Frequency
vs Frequency
CM Small-Signal Frequency Response
CM Input Bias Current
vs CM Input Voltage
vs CM Input Voltage
vs CM Input Voltage
Differential Output Offset Voltage
Output Common-Mode Offset
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SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
22
22
20
G = 20 dB
V
= 100 mV
PP
V
= 2 V
PP
OD
OD
20
18
G = 20 dB
G = 14 dB
18
16
16
14
12
G = 14 dB
G = 10 dB
14
12
10
G = 10 dB
G = 6 dB
10
8
8
6
4
G = 6 dB
6
4
2
2
0
0
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
f - Frequency - MHz
f − Frequency − MHz
Figure 1.
Figure 2.
HD2 vs FREQUENCY
HD3 vs FREQUENCY
−60
−70
−60
−70
−80
G = 6 dB,
= 2 V
G = 6 dB,
= 2 V
V
V
OD
PP
OD
PP
= 100 W
R
L
−80
R
= 100 W
L
−90
−90
R
= 200 W
L
R
= 1 kW
L
−100
−100
R
= 1 kW
R
= 500 W
L
L
−110
−120
−110
−120
R
= 200 W
L
R
= 500 W
L
1000
10
100
1
10
100
1000
1
f − Frequency − MHz
f − Frequency − MHz
Figure 3.
Figure 4.
HD2 vs FREQUENCY
HD3 vs FREQUENCY
−60
−70
−60
−70
−80
G = 10 dB,
V
G = 10 dB,
= 2 V
= 2 V
PP
V
OD
OD
PP
R
= 200 W
−80
L
R
= 100 W
R
= 500 W
L
L
−90
−90
R
L
= 1 kW
−100
−100
R
= 1 kW
L
R
= 100 W
L
−110
−120
−110
−120
R
= 200 W
R
= 500 W
L
L
1000
1
10
100
f − Frequency − MHz
1
10
100
1000
f − Frequency − MHz
Figure 5.
Figure 6.
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HD2 vs FREQUENCY
HD3 vs FREQUENCY
−60
−70
−60
−70
−80
G = 14 dB,
= 2 V
G = 14 dB,
= 2 V
V
OD
PP
= 100 W
V
OD
PP
R
L
−80
R
= 200 W
L
R
= 100 W
L
R
= 500 W
L
−90
−90
R
= 1 kW
L
−100
−100
R
= 200 W
L
−110
−120
−110
−120
R
= 500 W
L
R
= 1 kW
L
10
1
100
1000
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
Figure 7.
Figure 8.
HD2 vs OUTPUT VOLTAGE
HD3 vs OUTPUT VOLTAGE
f = 64 MHz
-60
-60
-70
-80
-70
-80
f = 32 MHz
f = 64 MHz
f = 32 MHz
f = 8 MHz
-90
-90
f = 16 MHz
-100
-100
-110
-120
f = 8 MHz
-110
f = 16 MHz
-120
4
0
1
3
2
0
1
2
- V
3
4
V
- V
OD
PP
V
OD
PP
Figure 9.
HD2 vs COMMON-MODE OUTPUT VOLTAGE
Figure 10.
HD3 vs COMMON-MODE OUTPUT VOLTAGE
0
-20
-20
-30
-40
-50
-60
-70
V
V
= -1 V to 1 V
CM
V
V
= -1 V to 1 V
CM
OD
= 2 V
PP
OD
= 2 V
PP
G = 10 dB
= 200 W
G = 10 dB
= 200 W
R
L
R
L
-40
150 MHz
150 MHz
-60
100 MHz
64 MHz
100 MHz
64 MHz
32 MHz
-80
-90
-80
32 MHz
-100
-110
-120
16 MHz
-100
-120
1 MHz
4 MHz
0.2 0.4 0.6 0.8
16 MHz
1 MHz
0.2 0.4 0.6 0.8
4 MHz
-1
-0.8 -0.6 -0.4 -0.2
0
1
-1 -0.8 -0.6 -0.4 -0.2
0
1
V
− Common-Mode Output Voltage − V
V
− Common-Mode Output Voltage − V
IC
IC
Figure 11.
Figure 12.
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IMD2 vs FREQUENCY
Gain = 6 dB,
IMD3 vs FREQUENCY
−60
-30
Gain = 6 dB,
= 2 V
R = 100 Ω
L
R
= 200 W
L
V
Envelope
PP
OD
V
= 2 V Envelop
PP
−65
−70
OD
-40
-50
R = 200 Ω
L
R
= 100 W
L
R = 1 kΩ
L
−75
−80
-60
-70
R
= 500 W
−85
L
-80
-90
−90
−95
R
= 1 kW
L
R = 500 Ω
L
−100
-100
0
100
f − Frequency − MHz
150
200
50
0
50
100
150
200
f - Frequency - Mhz
Figure 13.
Figure 14.
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
-60
-65
-70
-75
-80
-85
-90
-30
-40
-50
-60
Gain = 10 dB,
V
R
= 100 W
L
Gain = 10 dB,
= 2 V Envelope
= 2 V Envelope
PP
OD
V
R = 200 W
L
OD
PP
R
L
= 200 W
R
= 100 W
L
-70
-80
R
= 500 W
L
R = 1 kW
L
R
= 1 kW
L
R
= 500 W
-90
L
-95
-100
-100
0
50
100
150
200
0
50
100
150
200
F - Frequency - MHz
f - Frequency - Mhz
Figure 15.
Figure 16.
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−30
−60
−65
−70
−75
−80
Gain = 14 dB,
= 2 V
R
= 100 W
L
Gain = 14 dB
= 2 V
V
Envelope
PP
CO
−40
−50
−60
−70
V
Envelope
PP
R
= 200 W
OD
L
R
= 100 W
R
= 200 W
L
L
R
L
= 500 W
−85
−90
−80
−90
R
= 1 kW
L
R
= 1 kW
L
−95
R
= 500 W
L
−100
−100
0
100
150
200
0
50
100
f − Frequency − MHz
150
50
200
f − Frequency − MHz
Figure 17.
Figure 18.
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OIP2 vs FREQUENCY
OIP3 vs FREQUENCY
45
43
90
85
80
Gain = 6 dB
Gain = 6 dB
Gain = 14 dB
41
39
37
35
33
75
Gain = 10 dB
70
65
Gain = 10 dB
60
55
50
31
29
27
25
Gain = 14 dB
45
40
0
50
100
150
200
0
50
100
150
200
250
f − Frequency − MHz
f − Frequency − MHz
Figure 19.
Figure 20.
0.1-dB FLATNESS
S-PARAMETERS vs FREQUENCY
10.2
0
-10
-20
-30
-40
-50
-60
-70
S21
V
= 2V
OD
PP
10.1
10
S11
S22
9.9
9.8
S12
1
10
100
1000
0.1
1
10
100
1000
f − Frequency − MHz
f - Frequency - MHz
Figure 21.
Figure 22.
TRANSITION RATE vs OUTPUT VOLTAGE
TRANSIENT RESPONSE
1.5
8000
7000
6000
5000
4000
3000
2000
1
Rise
Fall
0.5
V
= 2 V
step
OD
0
−0.5
−1
1000
0
−1.5
0
0.5
1
1.5
2
2.5
3
3.5
STEP
4
t − Time − 500 ps/div
V
- Differential Outrput Voltage - V
OD
Figure 23.
Figure 24.
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SETTLING TIME
REJECTION RATIO vs FREQUENCY
5
4
3
2
1
0
100
90
V
=2V
step
OD
PSRR−
80
PSRR+
70
60
CMRR
50
40
30
20
10
0
−1
−2
−3
−4
−5
0.01
0.1
1
10
100
1000
t − Time − 500 ps/div
f − Frequency − MHz
Figure 25.
Figure 26.
OUTPUT IMPEDANCE vs FREQUENCY
OVERDRIVE RECOVERY
5
100
1
0.8
4
0.6
0.4
3
2
1
0
Input
10
Output
0.2
0
−0.2
−1
1
−0.4
−0.6
−2
−3
−4
−5
−0.8
−1
0.1
0.1
1
10
100
1000
t − Time − 200 ns/div
f − Frequency− MHz
Figure 27.
Figure 28.
OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
TURN-OFF TIME
2
5
4
7
6
1.6
1.2
0.8
Output
5
4
3
3
2
PD
2
0.4
0
1
0
1
0
10
100
1000
t − Time − 2 ms/div
RL - Load Resistance - W
Figure 29.
Figure 30.
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INPUT OFFSET VOLTAGE vs
INPUT COMMON-MODE VOLTAGE
TURN-ON TIME
5
4
3
2
40
35
30
25
20
15
10
5
2
1.6
1.2
PD
0.8
Output
1
0
0.4
0
0
−5
2.5
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
t − Time − 50 ns/div
Input Common-Mode Voltage − V
Figure 31.
Figure 32.
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
INPUT REFERRED NOISE vs FREQUENCY
1000
90
40
80
70
60
50
40
30
20
10
0
10
-20
100
Gain
-50
Phase
In
-80
-110
-140
-170
10
Vn
-200
-230
1
1 k
10
100
10 k
10 M
100 k
1 M
1
100
10 k
1 M
100 M
10 G
f − Frequency − Hz
f − Frequency − Hz
Figure 33.
Figure 34.
NOISE FIGURE vs FREQUENCY
QUIESCENT CURRENT vs SUPPLY VOLTAGE
20
40
35
30
25
T
= 25°C
19
18
A
50 - W System
Gain = 6 dB
T
= -40°C
A
17
16
1.35 V
Gain = 10 dB
Gain = 14 dB
Gain = 20 dB
T
= 85°C
A
15
14
13
12
11
10
0
50
100
f − Frequency − MHz
150
200
1
1.5
2
2.5
V
- Supply Voltage - V
S
Figure 35.
Figure 36.
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POWER-SUPPLY CURRENT
vs SUPPLY VOLTAGE IN POWER-DOWN MODE
OUTPUT BALANCE ERROR vs FREQUENCY
800
700
10
0
°
C
T = 85
A
°
T = 25 C
A
600
500
400
300
200
100
0
−10
−20
°
C
T = −40
A
−30
−40
−50
−60
1000
0
0.5
1
1.5
2
2.5
0.1
1
10
100
f − Frequency − MHz
− Supply Voltage −
V
V
S
Figure 37.
Figure 38.
CM INPUT IMPEDANCE vs FREQUENCY
CM SMALL-SIGNAL FREQUENCY RESPONSE
1
0
100
100 mVPP
-1
-2
10
-3
-4
1
-5
-6
-7
0.1
-8
-9
0.01
-10
0.1
1
10
100
1000
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
Figure 39.
Figure 40.
DIFFERENTIAL OUTPUT OFFSET VOLTAGE vs
CM INPUT VOLTAGE
CM INPUT BIAS CURRENT vs CM INPUT VOLTAGE
5
300
200
4
3
2
1
100
0
−100
−200
−300
0
−1
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
CM Input Voltage − V
CM Input V
oltage − V
Figure 41.
Figure 42.
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OUTPUT COMMON-MODE OFFSET vs
CM INPUT VOLTAGE
50
40
30
20
10
0
−10
−20
−30
−40
−50
2
−2.5
−2 −1.5
−1
0
1
1.5
2.5
−0.5
0.5
CM Input Voltage − V
Figure 43.
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TYPICAL AC PERFORMANCE: VS+ – VS– = 3 V
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, CM = open, VOD = 1 Vpp, RF = 349 Ω,
RL = 200 Ω differential, G = 10 dB, single-ended input, input and output referenced to midrail
Small-Signal Frequency Response
Large-Signal Frequency Response
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
Figure 75
HD2, G = 6 dB, VOD = 1 VPP
HD3, G = 6 dB, VOD = 1 VPP
HD2, G = 10 dB, VOD = 1 VPP
HD3, G = 10 dB, VOD = 1 VPP
HD2, G = 14 dB, VOD = 1 VPP
HD3, G = 14 dB, VOD = 1 VPP
IMD2, G = 6 dB, VOD = 1 VPP
IMD3, G = 6 dB, VOD = 1 VPP
IMD2, G = 10 dB, VOD = 1 VPP
IMD3, G = 10 dB, VOD = 1 VPP
IMD2, G = 14 dB, VOD = 1 VPP
IMD3, G = 14 dB, VOD = 1 VPP
OIP2
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
Harmonic Distortion
Intermodulation Distortion
Output Intercept Point
OIP3
0.1-dB Flatness
S-Parameters
vs Frequency
Transition Rate
vs Output Voltage
Transient Response
Settling Time
Output Voltage Swing
Rejection Ratio
vs Load Resistance
vs Frequency
Overdrive Recovery
Output Impedance
Turn-Off Time
vs Frequency
Turn-On Time
Output Balance Error
Noise Figure
vs Frequency
vs Frequency
CM Input Impedance
Differential Output Offset Voltage
Output Common-Mode Offset
vs Frequency
vs CM Input Voltage
vs CM Input Voltage
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SMALL-SIGNAL FREQUENCY RESPONSE
LARGE-SIGNAL FREQUENCY RESPONSE
22
20
22
20
18
16
14
V
= 100 mV
PP
OD
V
= 1 V
PP
OD
G = 20 dB
G = 20 dB
G = 14 dB
18
16
14
12
10
8
G = 14 dB
G = 10 dB
12
10
8
G = 10 dB
G = 6 dB
G = 6 dB
6
4
2
0
6
4
2
0
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
f - Frequency - MHz
f− Frequency − MHz
Figure 44.
Figure 45.
HD2 vs FREQUENCY
HD3 vs FREQUENCY
G = 6 dB,
V
G = 6 dB,
= 1 V
= 1 V
PP
−40
−50
−60
−70
−80
−90
−100
−40
−50
−60
−70
−80
−90
−100
V
OD
OD
PP
R
= 100 W
L
Ω
= 100
R
L
R
= 1 k
Ω
R
= 200 W
L
L
R
Ω
= 200
L
R
= 1 kW
L
−110
R
= 500 Ω
1000
R = 500 W
L
L
−120
1
10
100
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
Figure 46.
Figure 47.
HD2 vs FREQUENCY
HD3 vs FREQUENCY
−40
−40
−50
−60
−70
−80
−90
−100
G = 10 dB,
= 1 V
G = 10 dB,
= 1 V
C
OD
PP
−50
−60
V
OD
PP
−70
−80
R
L
= 200Ω
R
L
= 1 kW
−90
R
= 500 W
L
−100
R
L
= 1 kΩ
L
R
= 200 W
L
−110
R
= 500 Ω
100
−120
1
1
100
10
f − Frequency − MHz
1000
1000
10
f − Frequency − MHz
Figure 48.
Figure 49.
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HD2 vs FREQUENCY
HD3 vs FREQUENCY
−40
−50
−40
−50
G = 14 dB,
= 1 V
G = 14 dB,
V = 1 V
OD
V
OD
PP
PP
−60
−70
−60
−70
−80
R
= 100Ω
R
= 100 W
L
L
−80
−90
R
= 200Ω
L
R
= 200 W
L
−100
R
= 500 W
L
R
Ω
= 500
L
−90
−110
−120
R
= 1 kW
R
Ω
= 1 k
L
L
−100
1
10
100
1000
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
Figure 50.
Figure 51.
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−30
−40
−50
−30
−40
−50
−60
−70
−80
Gain = 6 dB,
= 1 V
Gain = 6 dB,
V
R
= 500 W
L
V
= 1 V Envelope
OD
PP
OD PP
R
= 1 kW
L
R
= 100 W
L
−60
−70
−80
R
L
= 1 kW
= 500 W
R
= 100 W
L
R
L
R
= 200 W
L
−90
−90
R
= 200 W
L
−100
−100
0
50
100
150
200
0
50
100
150
200
f − Frequency − MHz
f − Frequency − MHz
Figure 52.
Figure 53.
IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−30
−40
−50
−60
−70
−80
−30
−40
−50
−60
Gain = 10 dB,
V
R
= 500 W
L
Gain = 10 dB,
V
= 1 V Envolope
PP
OD
= 1 V Envelope
PP
OD
R
= 100 W
L
R
= 1 kW
R
= 100 W
L
R
= 500 W
L
L
−70
−80
R
= 200 W
L
R
= 1 kW
L
−90
−90
R
= 200 W
L
−100
−100
0
50
100
150
200
0
50
100
150
200
f − Frequency − MHz
f − Frequency − MHz
Figure 54.
Figure 55.
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IMD2 vs FREQUENCY
IMD3 vs FREQUENCY
−30
−40
−30
−40
−50
−60
−70
Gain = 14 dB,
V
Gain = 14 dB,
V
R
= 500 W
L
= 1 V Envelope
PP
= 1 V Envelope
PP
OD
OD
R
= 100 W
L
−50
−60
−70
−80
R
= 1 kW
R
= 100 W
L
R
L
= 500 W
L
R
= 1 kW
L
R
= 200 W
L
−80
−90
R
= 200 W
L
−90
−100
−100
0
50
100
150
200
0
50
100
150
200
f − Frequency − MHz
f − Frequency − MHz
Figure 56.
Figure 57.
OIP2 vs FREQUENCY
OIP3 vs FREQUENCY
80
75
45
40
35
Gain = 6 dB
Gain = 6 dB
Gain = 10 dB
70
65
60
55
50
45
40
Gain = 10 dB
30
25
Gain = 14 dB
Gain = 14 dB
20
15
35
30
250
0
50
150
200
100
150
0
200
50
100
f − Frequency − MHz
f − Frequency − MHz
Figure 58.
Figure 59.
0.1-dB FLATNESS
S-PARAMETERS vs FREQUENCY
10.2
10.1
10
0
V
= 1 V
PP
S21
OD
-10
-20
-30
S11
S22
-40
-50
-60
-70
9.9
9.8
S12
10000
0.1
1
10
100
1000
1
10
100
1000
f − Frequency − MHz
f = Frequency - MHz
Figure 60.
Figure 61.
20
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TRANSITION RATE vs OUTPUT VOLTAGE
TRANSIENT RESPONSE
4000
3500
0.6
0.5
0.4
0.3
0.2
0.1
0
Rising
3000
2500
2000
V
= 1 V
step
OD
Falling
−0.1
−0.2
−0.3
−0.4
1500
1000
500
0
−0.5
−0.6
0.2
1
1.2
1.4
0
0.4
0.6
− Differential Output Voltage - V
0.8
t − Time − 500 ps/div
V
OD
STEP
Figure 62.
Figure 63.
SETTLING TIME
OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
2.5
5
4
3
2
1
0
V
= 1 V
step
OD
2
1.5
−1
−2
1
−3
−4
−5
0.5
0
1000
100
0
t − Time − 500 ps/div
R
- Load Resistance - W
L
Figure 64.
Figure 65.
REJECTION RATIO vs FREQUENCY
OVERDRIVE RECOVERY
90
80
70
3
2.5
2
0.6
0.4
0.2
0
PSRR−
CMRR
Input
1.5
1
60
50
PSRR+
0.5
Output
0
−0.5
−1
40
30
20
−0.2
−0.4
−0.6
−1.5
−2
10
0
−2.5
−3
0.01
0.1
1
10
100
1000
t − Time − 200 ns/div
f − Frequency − MHz
Figure 66.
Figure 67.
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OUTPUT IMPEDANCE vs FREQUENCY
TURN-OFF TIME
100
3
1
0.8
0.6
0.4
2.5
2
Output
PD
10
1.5
1
1
0.2
0
0.5
0
0.1
1000
0.1
1
10
100
t – Time – 2 ms/div
f − Frequency− MHz
Figure 68.
Figure 69.
TURN-ON TIME
OUTPUT BALANCE ERROR vs FREQUENCY
3
10
0
1.2
2.5
1
−10
−20
−30
PD
2
0.8
0.6
0.4
1.5
Output
1
−40
−50
−60
0.5
0
0.2
0
0.1
1
10
100
1000
t − Time − 50 ns/div
f − Frequency − MHz
Figure 70.
Figure 71.
NOISE FIGURE vs FREQUENCY
CM INPUT IMPEDANCE vs FREQUENCY
20
100
10
19
18
17
16
15
14
13
12
50 - W System
Gain = 6 dB
Gain = 10 dB
Gain = 14 dB
1
0.1
Gain = 20 dB
50
11
10
0.01
0
100
150
200
1000
100
0.1
1
10
f − Frequency − MHz
f − Frequency − MHz
Figure 72.
Figure 73.
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DIFFERENTIAL OUTPUT OFFSET VOLTAGE vs
CM INPUT VOLTAGE
OUTPUT COMMON-MODE OFFSET vs
CM INPUT VOLTAGE
50
40
30
20
5
4
3
2
1
10
0
−10
−20
−30
−40
−50
0
−1
−1.5
−1
−0.5
0
0.5
1
1.5
−1.5
−1
−0.5
0
0.5
1
1.5
CM Input Voltage - V
CM Input Voltage − V
Figure 74.
Figure 75.
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TEST CIRCUITS
of the network analyzer is 50 Ω. RIT and RG are
chosen to impedance match to 50 Ω, and to maintain
the proper gain. To balance the amplifier, a 0.22-F
capacitor and 49.9-Ω resistor to ground are inserted
across RIT on the alternate input.
The THS4509 is tested with the following test circuits
built on the EVM. For simplicity, power-supply
decoupling is not shown
– see layout in the
applications section for recommendations. Depending
on the test conditions, component values are
changed per the following tables, or as otherwise
noted. The signal generators used are ac coupled
50-Ω sources and a 0.22-µF capacitor and a 49.9-Ω
resistor to ground are inserted across RIT on the
alternate input to balance the circuit. A split power
supply is used to ease the interface to common test
equipment, but the amplifier can be operated single
supply, as described in the applications section, with
no impact on performance.
The output is probed using
a high-impedance
differential probe across the 100-Ω resistor. The gain
is referred to the amplifier output by adding back the
6-dB loss due to the voltage divider on the output.
V
IN
R
R
F
G
G
From
50 Ω
Source
V
S+
R
R
IT
49.9 Ω
49.9 Ω
Output Measured
Here With High
Impedance
100 Ω
THS4509
CM
R
Differential Probe
0.22 µF
49.9 Ω
Open
0.22 µF
IT
Table 1. Gain Component Values
V
S−
GAIN
6 dB
RF
RG
RIT
R
F
348 Ω
348 Ω
348 Ω
348 Ω
165 Ω
100 Ω
56.2 Ω
16.5 Ω
61.9 Ω
69.8 Ω
88.7 Ω
287 Ω
Figure 76. Frequency Response Test Circuit
10 dB
14 dB
20 dB
Distortion and 1-dB Compression
The circuit shown in Figure 77 is used to measure
harmonic distortion, intermodulation distortion, and
1-db compression point of the amplifier.
Note the gain setting includes 50-Ω source
impedance. Components are chosen to achieve
gain and 50-Ω input termination.
A signal generator is used as the signal source and
the output is measured with a spectrum analyzer. The
output impedance of the signal generator is 50 Ω. RIT
and RG are chosen to impedance-match to 50 Ω, and
to maintain the proper gain. To balance the amplifier,
a 0.22-F capacitor and 49.9-Ω resistor to ground are
inserted across RIT on the alternate input.
Table 2. Load Component Values
RL
RO
ROT
ATTEN
6 dB
100 Ω
200 Ω
499 Ω
1k Ω
25 Ω
open
86.6 Ω
237 Ω
487 Ω
69.8 Ω
56.2 Ω
52.3 Ω
16.8 dB
25.5 dB
31.8 dB
A low-pass filter is inserted in series with the input to
reduce harmonics generated at the signal source.
The level of the fundamental is measured, then a
high-pass filter is inserted at the output to reduce the
fundamental so that it does not generate distortion in
the input of the spectrum analyzer.
Note the total load includes 50-Ω termination by
the test equipment. Components are chosen to
achieve load and 50-Ω line termination through a
1:1 transformer.
Due to the voltage divider on the output formed by
the load component values, the amplifier's output is
attenuated. The column ATTEN in Table 2 shows the
attenuation expected from the resistor divider. When
using a transformer at the output, as shown in
Figure 77, the signal sees slightly more loss, and
these numbers are approximate.
The transformer used in the output to convert the
signal from differential to single ended is an
ADT1-1WT. It limits the frequency response of the
circuit so that measurements cannot be made below
approximately 1 MHz.
V
IN
R
R
F
G
From
50 Ω
Source
Frequency Response
V
S+
R
R
IT
V
OUT
R
R
O
To 50 Ω
Test
Equipment
1:1
The circuit shown in Figure 76 is used to measure the
frequency response of the circuit.
R
OT
THS 4509
CM
R
IT
G
O
A network analyzer is used as the signal source and
as the measurement device. The output impedance
0.22 µF
49.9 Ω
Open
0.22 µF
V
S−
R
F
Figure 77. Distortion Test Circuit
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CM Input
The 1-dB compression point is measured with a
spectrum analyzer with 50-Ω double termination or
100-Ω termination as shown in Table 2. The input
power is increased until the output is 1 dB lower than
expected. The number reported in the table data is
the power delivered to the spectrum analyzer input.
Add 3 dB to refer to the amplifier output.
The circuit shown in Figure 79 is used to measure the
frequency response and input impedance of the CM
input. Frequency response is measured single ended
at VOUT+ or VOUT– with the input injected at VIN, RCM
=
0 Ω, and RCMT = 49.9 Ω. The input impedance is
measured with RCM = 49.9 Ω with RCMT = open, and
calculated by measuring the voltage drop across RCM
to determine the input current.
S-Parameter, Slew Rate, Transient Response,
Settling Time, Output Impedance, Overdrive,
Output Voltage, and Turn-On/Turn-Off Time
RG
RF
The circuit shown in Figure 78 is used to measure
s-parameters, slew rate, transient response, settling
time, output impedance, overdrive recovery, output
voltage swing, and turn-on/turn-off times of the
amplifier. For output impedance, the signal is injected
at VOUT with VIN left open and the drop across the
49.9-Ω resistor is used to calculate the impedance
seen looking into the amplifier’s output.
VS+
0.22 mF
49.9 W
RIT
49.9 W
To
VOUT–
50-ohm
Test
Equipment
THS4509
CM
RG
RIT
49.9 W
VOUT+
0.22 mF
49.9 W
RCM
VIN From
50-ohm
source
VS–
RF
RCMT
Because S21 is measured single ended at the load
with 50-Ω double termination, add 12 dB to refer to
the amplifier’s output as a differential signal.
Figure 79. CM Input Test Circuit
CMRR and PSRR
V
IN
From
50 Ω
R
R
F
G
G
Source
V
The circuit shown in Figure 80 is used to measure the
CMRR and PSRR of VS+ and VS–. The input is
switched appropriately to match the test being
performed.
S+
R
R
IT
49.9 Ω
49.9 Ω
V
V
OUT+
To 50 Ω
Test
Equipment
THS 4509
CM
R
OUT−
348 Ω
0.22 µF
49.9 Ω
V
S+
Open
0.22 µF
IT
V
V
S+
S−
PSRR+
V
IN
49.9 Ω
49.9 Ω
Output
From
50 Ω
Source
R
100 Ω
100 Ω
F
Measured
Here
CMRR
PSRR−
THS4509
CM
100 Ω
With High
Impedance
Differential
Probe
Figure 78. S-Parameter, SR, Transient Response,
Settling Time, ZO, Overdrive Recovery, VOUT
Swing, and Turn-On/Turn-Off Test Circuit
Open
0.22 µF
V
S−
69.8 Ω
V
S−
348 Ω
Figure 80. CMRR and PSRR Test Circuit
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APPLICATION INFORMATION
R
R
F
G
Single-Ended
Input
APPLICATIONS
V
Differential
Output
S
The following circuits show application information for
the THS4509. For simplicity, power supply decoupling
capacitors are not shown in these diagrams. See
section THS4509 EVM for recommendations. For
more detail on the use and operation of fully
differential op amps see the application report
Fully-Differential Amplifiers (SLOA054) .
V
+
–
OUT–
THS
4509
R
G
+
–
V
OUT+
V
S
Differential Input to Differential Output Amplifier
R
F
The THS4509 is a fully differential op amp, and can
be used to amplify differential input signals to
differential output signals. A basic block diagram of
the circuit is shown in Figure 81 (CM input not
shown). The gain of the circuit is set by RF divided by
RG.
Figure 82. Single-Ended Input to Differential
Output Amplifier
Input Common-Mode Voltage Range
R
F
The input common-model voltage of a fully differential
op amp is the voltage at the '+' and '–' input pins of
the op amp.
Differential
Output
Differential
Input
V
S+
It is important to not violate the input common-mode
voltage range (VICR) of the op amp. Assuming the op
amp is in linear operation the voltage across the input
pins is only a few millivolts at most. So finding the
voltage at one input pin will determine the input
common-mode voltage of the op amp.
R
G
G
V
V
V
IN+
OUT–
+
THS4509
–
R
+
–
V
IN–
OUT+
Treating the negative input as a summing node, the
voltage is given by Equation 1:
V
S–
æ
ö
÷
÷
ø
æ
ö
÷
÷
ø
RG
RF
ç
ç
VIC = VOUT+
´
+ VIN-
´
R
F
ç
ç
RG + RF
RG + RF
è
è
(1)
Figure 81. Differential Input to Differential Output
Amplifier
To determine the VICR of the op amp, the voltage at
the negative input is evaluated at the extremes of
VOUT+
.
Depending on the source and load, input and output
termination can be accomplished by adding RIT and
RO.
As the gain of the op amp increases, the input
common-mode voltage becomes closer and closer to
the input common-mode voltage of the source.
Single-Ended Input to Differential Output
Amplifier
Setting the Output Common-Mode Voltage
The THS4509 can be used to amplify and convert
single-ended input signals to differential output
signals. A basic block diagram of the circuit is shown
in Figure 82 (CM input not shown). The gain of the
circuit is again set by RF divided by RG.
The output common-mode voltage is set by the
voltage at the CM pin(s). The internal common-mode
control circuit maintains the output common-mode
voltage within 3-mV offset (typ) from the set voltage,
when set within 0.5 V of mid-supply, with less than
4-mV differential offset voltage. If left unconnected,
the common-mode set point is set to mid-supply by
internal circuitry, which may be overdriven from an
external source. Figure 83 is representative of the
CM input. The internal CM circuit has about 700 MHz
of –3-dB bandwidth, which is required for best
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performance, but it is intended to be a dc bias input
RS
RG
RT
RF
pin. Bypass capacitors are recommended on this pin
to reduce noise at the output. The external current
required to overdrive the internal resistor divider is
given by Equation 2:
VS+
VSignal
VBias= VCM
RS
RO
RO
VCM
VOUT-
VOUT+
2VCM - (VS+ - VS- )
50 kW
THS4509
CM
RG
RT
IEXT
=
(2)
VS–
where VCM is the voltage applied to the CM pin.
VCM
VCM VCM
RF
V
S+
Figure 84. THS4509 DC-Coupled Single Supply
With Input Biased to VCM
50 kW
I
EXT
In Figure 85 the source is referenced to ground and
so is the input termination resistor. RPU is added to
the circuit to avoid violating the VICR of the op amp.
The proper value of resistor to add can be calculated
from Equation 3:
to internal
CM circuit
CM
50 kW
V
(VIC - VS+ )
S–
RPU
=
æ
ö
æ
ö
1
1
1
Figure 83. CM Input Circuit
ç
ç
÷
÷
ç
ç
÷
÷
VCM
- VIC
+
RF
RIN RF
è
ø
è
ø
(3)
Single-Supply Operation (3 V to 5 V)
VIC is the desire input common-mode voltage, VCM
=
CM, and RIN = RG + RS||RT. To set to mid-supply,
make the value of RPU = RG+ RS||RT.
To facilitate testing with common lab equipment, the
THS4509 EVM allows split-supply operation, and the
characterization data presented in this data sheet
was taken with split-supply power inputs. The device
can easily be used with a single-supply power input
without degrading the performance. Figure 84,
Figure 85, and Figure 86 show dc and ac-coupled
single-supply circuits with single-ended inputs. These
configurations all allow the input and output
common-mode voltage to be set to mid-supply
allowing for optimum performance. The information
presented here can also be applied to differential
input sources.
Table 3 is a modification of Table 1 to add the proper
values with RPU assuming a 50 Ω source impedance
and setting the input and output common-mode
voltage to mid-supply.
There are two drawbacks to this configuration. One is
it requires additional current from the power supply.
Using the values shown for a gain of 10 dB requires
37 mA more current with 5-V supply, and 22 mA
more current with 3-V supply.
The other drawback is this configuration also
increases the noise gain of the circuit. In the 10-dB
gain case, noise gain increases by a factor of 1.5.
In Figure 84, the source is referenced to the same
voltage as the CM pin (VCM). VCM is set by the
internal circuit to mid-supply. RT along with the input
impedance of the amplifier circuit provides input
Table 3. RPU Values for Various Gains
termination, which is also referenced to VCM
.
Gain
6 dB
RF
RG
RIT
RPU
348 Ω
348 Ω
348 Ω
348 Ω
169 Ω
102 Ω
61.9 Ω
40.2 Ω
64.9 Ω
78.7 Ω
115 Ω
221 Ω
200 Ω
133 Ω
97.6 Ω
80.6 Ω
Note RS and RT are added to the alternate input from
the signal input to balance the amplifier. Alternately,
one resistor can be used equal to the combined value
RG+ RS||RT on this input. This is also true of the
circuits shown in Figure 85 and Figure 86.
10 dB
14 dB
20 dB
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input capacitance of the ADS5500 limit the bandwidth
VS+
of the signal to 115 MHz (–3 dB). For testing, a signal
generator is used for the signal source. The
RPU
RS
RG
RF
generator is an ac-coupled 50-Ω source. A band-pass
filter is inserted in series with the input to reduce
harmonics and noise from the signal source. Input
termination is accomplished via the 69.8-Ω resistor
and 0.22-µF capacitor to ground in conjunction with
the input impedance of the amplifier circuit. A 0.22-µF
capacitor and 49.9-Ω resistor are inserted to ground
across the 69.8-Ω resistor and 0.22-µF capacitor on
the alternate input to balance the circuit. Gain is a
function of the source impedance, termination, and
348-Ω feedback resistor. See Table 3 for component
values to set proper 50-Ω termination for other
common gains. A split power supply of +4 V and –1 V
is used to set the input and output common-mode
voltages to approximately mid-supply while setting
the input common-mode of the ADS5500 to the
recommended +1.55 V. This maintains maximum
headroom on the internal transistors of the THS4509
to ensure optimum performance.
VS+
RT
VS+
VSignal
RO
RO
VOUT-
VOUT+
RPU
RG
THS 4509
CM
RS
RT
VS-
RF
Figure 85. THS4509 DC-Coupled Single Supply
With RPU Used to Set VIC
Figure 86 shows ac coupling to the source. Using
capacitors in series with the termination resistors
allows the amplifier to self bias both input and output
to mid-supply.
C
RS
RG
RF
VIN
From
50-W
source
100 W
348 W
VS+=3V to 5V
RT
VSignal
4 V
69.3 W
14-bit,
125 MSPS
RO
RO
C
100 W
VOUT-
0.22 mF
100 W
AIN +
THS 4509
CM
RG
ADS5500
AIN -
THS 4509
CM
2.7 pF
100 W
VOUT+
CM
RS
C
RT
C
VS-
49.9 W
49.9 W
0.22 mF
69.8 W
0.22 mF
V
-1
0.1 mF
0.1 mF
RF
348 W
Figure 87. THS4509 + ADS5500 Circuit
Figure 86. THS4509 AC-Coupled Single Supply
THS4509 + ADS5500 Combined Performance
90
85
80
75
70
65
SFDR (dBc)
The THS4509 is designed to be a high performance
drive amplifier for high performance data converters
like the ADS5500 14-bit 125-MSPS ADC. Figure 87
shows a circuit combining the two devices, and
Figure 88 shows the combined SNR and SFDR
performance versus frequency with –1-dBFS input
signal level sampling at 125 MSPS. The THS4509
amplifier circuit provides 10 dB of gain, converts the
single-ended input to differential, and sets the proper
input common-mode voltage to the ADS5500. The
100-Ω resistors and 2.7-pF capacitor between the
THS4509 outputs and ADS5500 inputs along with the
SNR (dBFS)
10
20
30
40
50
60
70
80
90
100 110
Input Frequency - MHz
Figure 88. THS4509 + ADS5500 SFDR and SNR
Performance versus Frequency
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Figure 89 shows the two-tone FFT of the THS4509 +
ADS5500 circuit with 65-MHz and 70-MHz input
frequencies. The SFDR is 90 dBc.
VIN
100 W
348 W
From
50-W
source
5 V
69.8 W
14-bit,
105 MSPS
225 W
225 W
0.22 mF
AIN+
THS4509
CM
2.7pF
ADS5424
AIN–
100
VBG
49.9 W
0.22 mF
69.8 W
0.22 mF
49.9 W
0.1 mF
0.1 mF
348 W
Figure 90. THS4509 + ADS5424 Circuit
95
90
85
80
75
70
SFDR (dBc)
Figure 89. THS4509 + ADS5500 Two-Tone FFT
with 65-MHz and 70-MHz Input
SNR (dBFS)
THS4509 + ADS5424 Combined Performance
Figure 90 shows the THS4509 driving the ADS5424
ADC, and Figure 91 shows their combined SNR and
SFDR performance versus frequency with –1-dBFS
input signal level and sampling at 80 MSPS.
10
20
30
40
50
60
70
Input Frequency - MHz
Figure 91. THS4509 + ADS5424 SFDR and
SNR Performance vs Frequency
As before, the THS4509 amplifier provides 10 dB of
gain, converts the single-ended input to differential,
and sets the proper input common-mode voltage to
the ADS5424. Input termination and circuit testing is
the same as previously described for the THS4509 +
ADS5500 circuit.
The 225-Ω resistors and 2.7-pF capacitor between
the THS4509 outputs and ADS5424 inputs (along
with the input capacitance of the ADC) limit the
bandwidth of the signal to about 100 MHz (–3 dB).
Since
the
ADS5424's
recommended
input
common-mode voltage is 2.4 V, the THS4509 is
operated from a single power-supply input with
VS+ = 5 V and VS– = 0 V (ground).
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Layout Recommendations
8. A single-point connection to ground on L2 is
recommended for the input termination resistors
R1 and R2. This should be applied to the input
gain resistors if termination is not used.
It is recommended to follow the layout of the external
components near the amplifier, ground plane
construction, and power routing of the EVM as
closely as possible. General guidelines are:
9. The THS4509 recommended PCB footprint is
shown in Figure 92.
1. Signal routing should be direct and as short as
possible into and out of the op amp circuit.
0.144
0.049
2. The feedback path should be short and direct
avoiding vias.
3. Ground or power planes should be removed from
directly under the amplifier’s input and output
pins.
0.012
Pin 1
0.0095
4. An output resistor is recommended on each
output, as near to the output pin as possible.
0.015
0.144
0.0705
0.0195
5. Two 10-µF and two 0.1-µF power-supply
decoupling capacitors should be placed as near
to the power-supply pins as possible.
0.010
vias
0.032
6. Two 0.1-µF capacitors should be placed between
the CM input pins and ground. This limits noise
coupled into the pins. One each should be placed
to ground near pin 4 and pin 9.
0.030
0.0245
Top View
7. It is recommended to split the ground pane on
layer 2 (L2) and to use a solid ground on layer 3
(L3). A single-point connection should be used
between each split section on L2 and L3.
Figure 92. QFN Etch and Via Pattern
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THS4509 EVM
Figure 93 is the THS4509 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown in Figure 94, and
Table 4 is the bill of material for the EVM as supplied from TI.
GND
J5
V
V
S−
S+
J4
J6
VEE
VCC
0.1 µF
C10
0.1 µF
C4
10 µF
10 µF
10 µF
10 µF
0.1 µF
0.1 µF
C12
TP1
C9
C6
C3
C5
C13
J8
R5
348 Ω
R1
69.8 Ω
VCC
VCC
8
R9
open
6
5
J1
7
R3
12
PD
J3
C15
3
100 Ω
R12
R7
C1
open
T1
2
V
V
−
O+
6
1
R11
69.8 Ω
86.6 Ω
R8
49.9 Ω
U1
0.22 µF
11
C8
open
C7
open
+
5
4
O−
PwrPad10
J2
R4
4
3
86.6 Ω
Vocm
9
XFMR_ADT1−1WT
C2
open
100 Ω
R2
69.8 Ω
15 13
14 16
R10
open
VEE
R6
J7
348 Ω
TP3
VEE
TP2
C14
0.1 µF
C11
0.1 µF
Figure 93. THS4509 EVAL1 EVM Schematic
Figure 94. THS4509 EVAL1 EVM Layer 1 Through 4
Copyright © 2008, Texas Instruments Incorporated
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Product Folder Link(s): THS4509-Q1
THS4509-Q1
SLOS547–NOVEMBER 2008........................................................................................................................................................................................... www.ti.com
Table 4. THS4509 EVAL1 EVM Bill of Materials
ITEM
DESCRIPTION
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER
1
2
CAP, 10.0 F, Ceramic, X5R, 6.3 V
CAP, 0.1 F, Ceramic, X5R, 10 V
CAP, 0.22 F, Ceramic, X5R, 6.3 V
OPEN
0805 C3, C4, C5, C6
0402 C9, C10, C11, C12, C13, C14
0402 C15
4
6
1
4
2
1
3
2
2
2
1
3
(AVX) 08056D106KAT2A
(AVX) 0402ZD104KAT2A
(AVX) 04026D224KAT2A
3
4
0402 C1, C2, C7, C8
0402 R9, R10
0402 R12
5
OPEN
6
Resistor, 49.9 Ω, 1/16 W, 1%
Resistor, 69.8 Ω, 1/16 W, 1%
Resistor, 86.6 Ω, 1/16 W, 1%
Resistor, 100 Ω, 1/16 W, 1%
Resistor, 348 Ω, 1/16 W, 1%
Transformer, RF
(KOA) RK73H1ETTP49R9F
(KOA) RK73H1ETTP69R8F
(KOA) RK73H1ETTP86R6F
(KOA) RK73H1ETTP1000F
(KOA) RK73H1ETTP3480F
(MINI-CIRCUITS) ADT1-1WT
(HH SMITH) 101
8
0402 R1, R2, R11
0402 R7, R8
9
10
11
12
13
0402 R3, R4
0402 R5, R6
T1
Jack, banana receptacle, 0.25" diameter
hole
J4, J5, J6
14
15
16
17
18
19
20
OPEN
J1, J7, J8
J2, J3
3
2
3
1
4
4
1
Connector, edge, SMA PCB Jack
Test point, Red
(JOHNSON) 142-0701-801
(KEYSTONE) 5000
(TI) THS4509RGT
TP1, TP2, TP3
U1
IC, THS4509
Standoff, 4-40 HEX, 0.625" length
Screw, Phillips, 4-40, 0.250"
Printed circuit board
(KEYSTONE) 1808
SHR-0440-016-SN
(TI) EDGE# 6468901
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input and output voltage ranges as specified in the following table.
Input Range, VS+ to VS–
Input range, VI
3.0 V to 6.0 V
3.0 V to 6.0 V not to exceed VS+ or VS-
3.0 V to 6.0 V not to exceed VS+ or VS-
Output range, VO
Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If
there are questions concerning the input range, please contact a TI field representative prior to connecting the
input power.
Applying loads outside of the specified output range may result in unintended operation and/or possible
permanent damage to the EVM. Please consult the product data sheet or EVM user's guide (if user's guide is
available) prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,
please contact a TI field representative.
During normal operation, some circuit components may have case temperatures greater than 30°C. The EVM is
designed to operate properly with certain components above 50°C as long as the input and output ranges are
maintained. These components include but are not limited to linear regulators, switching transistors, pass
transistors, and current sense resistors. These types of devices can be identified using the EVM schematic
located in the material provided. When placing measurement probes near these devices during operation, please
be aware that these devices may be very warm to the touch.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jun-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
THS4509QRGTRQ1
ACTIVE
QFN
RGT
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4509-Q1 :
Catalog: THS4509
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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