THS4509 [TI]
WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIER; 宽带,低噪声,低失真全差动放大器型号: | THS4509 |
厂家: | TEXAS INSTRUMENTS |
描述: | WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIER |
文件: | 总30页 (文件大小:2105K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
THS4509
www.ti.com
SLOS454–JANUARY 2005
WIDEBAND, LOW NOISE, LOW DISTORTION FULLY DIFFERENTIAL AMPLIFIER
To allow for dc coupling to ADCs, its unique output
common-mode control circuit maintains the output
common-mode voltage within 3 mV offset (typ) from
the set voltage, when set within 0.5 V of mid-supply,
with less than 4 mV differential offset voltage. The
common-mode set point is set to mid-supply by
internal circuitry, which may be over-driven from an
external source.
FEATURES
•
•
•
•
Fully Differential Architecture
Centered Input Common-mode Range
Minimum Gain of 2V/V (6 dB)
Bandwidth: 1900 MHz (100 mVpp, G = 10 dB,
RL = 200 Ω)
•
•
•
Slew Rate: 6600 V/µs (2V step, G = 10 dB)
1% Settling Time: 2 ns (2 V step, G = 10 dB)
The input and output are optimized for best perform-
ance with their common-mode voltages set to
mid-supply. Along with high performance at low
power supply voltage, this makes for extremely high
performance single supply 5 V data acquisition sys-
tems. The combined performance of the THS4509 in
a gain of 10 dB driving the ADS5500 ADC, sampling
at 125 MSPS, is 81 dBc SFDR and 69.1 dBc SNR
with a –1 dBFS signal at 70 MHz.
HD2: –75 dBc at 100 MHz (2 Vpp, G = 10 dB,
RL = 1 kΩ)
•
•
•
HD3: –80 dBc at 100 MHz (2 Vpp, G = 10 dB,
RL = 1 kΩ)
OIP2: 79 dBm at 70 MHz (2 Vpp envelope,
G = 10 dB)
OIP3: 43 dBm at 70 MHz (2 Vpp envelope,
G = 10 dB)
The THS4509 is offered in a Quad 16-pin leadless
QFN package (RGT), and is characterized for oper-
ation over the full industrial temperature range from
–40°C to 85°C.
•
•
Input Voltage Noise: 1.9 nV/√Hz (f >10 MHz)
Noise Figure: 17.1 dB (50 Ω System, G = 10
dB)
V
IN
100 Ω
348 Ω
2.5 V
From
50 Ω
Source
•
•
Output Common-Mode Control
Power Supply:
69.8 Ω
V
OUT
487 Ω
487 Ω
1:1
To 50 Ω
– Voltage: 3 V (±1.5 V) to 5 V (±2.5 V)
– Current: 37.7 mA
Test
Equipment
56.3 Ω
THS 4509
100 Ω
0.22 µF
49.9 Ω
CM
69.8 Ω
Open
•
Power-Down Capability: 0.65 mA
−2.5 V
APPLICATIONS
348 Ω
•
5 V Data Acquisition Systems High
Linearity ADC Amplifier
Wireless Communication
Medical Imaging
Test and Measurement
-75
-80
-85
-90
-95
G = 10 dB,
V
= 2 V
,
•
•
•
O
PP
R
L
= 1 kW
DESCRIPTION
HD
3
The THS4509 is a wideband, fully differential op amp
designed for 5 V data acquisition systems. It has very
low noise at 1.9 nV/√Hz, and extremely low harmonic
distortion of –75 dBc HD2 and –80 dBc HD3 at 100
MHz with 2 Vpp, G = 10 dB, and 1 kΩ load. Slew rate
is very high at 6600 Vµs and with settling time of 2 ns
to 1% (2 V step) it is ideal for pulsed applications. It is
designed for minimum gain of 6 dB, but is optimized
for gain of 10 dB.
-100
-105
-110
HD
2
10
100
1
f - Frequency - MHz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS4509
www.ti.com
SLOS454–JANUARY 2005
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated
circuits be handled with appropriate precautions. Failure to observe proper handling and installation
procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision
integrated circuits may be more susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
PACKAGING/ORDERING INFORMATION
PACKAGED DEVICES
QUAD QFN(1)(2)
(RGT-16)
TEMPERATURE
SYMBOL
THS4509RGTT
THS4509RGTR
–40°C to 85°C
–
(1) This package is available taped and reeled. The R suffix standard quantity is 3000. The T suffix standard quantity is 250.
(2) The exposed thermal pad is electrically isolated from all other pins.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
UNIT
VS– to VS+
Supply voltage
6 V
VI
Input voltage
±VS
VID
IO
Differential input voltage
Output current(1)
4 V
200 mA
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature range
Storage temperature range
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
HBM
See Dissipation Rating Table
TJ
150°C
–40°C to 85°C
–65°C to 150°C
300°C
TA
Tstg
2000
ESD ratings
CDM
MM
1500
100
(1) The THS4509 incorporates a (QFN) exposed thermal pad on the underside of the chip. This acts as a heatsink and must be connected
to a thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the
QFN thermally enhanced package.
DISSIPATION RATINGS TABLE PER PACKAGE
POWER RATING
PACKAGE
θJC
θJA
TA≤ 25°C
TA = 85°C
RGT (16)
2.4°C/W
39.5°C/W
2.3 W
225 mW
2
THS4509
www.ti.com
SLOS454–JANUARY 2005
SPECIFICATIONS; VS+– VS– = 5 V:
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Differential Output, Input and Output Referenced to Mid-supply
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
–40°C to
85°C
MIN/
MAX
TEST
LEVEL(1)
25°C
25°C
UNITS
AC PERFORMANCE
G = 6 dB, VO = 100 mVpp
2.0
1.9
GHz
GHz
MHz
MHz
GHz
MHz
GHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
G = 10 dB, VO = 100 mVpp
G = 14 dB, VO = 100 mVpp
G = 20 dB, VO = 100 mVpp
G = 20 dB
Small-Signal Bandwidth
600
275
3
Gain-Bandwidth Product
Bandwidth for 0.1dB flatness
Large-Signal Bandwidth
Slew Rate (Differential)
Rise Time
G = 10 dB, VO = 2 Vpp
G = 10 dB, VO = 2 Vpp
2V Step
300
1.5
6600
0.5
2V Step
Fall Time
2V Step
0.5
ns
Settling Time to 1%
Settling Time to 0.1%
VO = 2 V Step
VO = 2 V Step
f = 10 MHz
2
ns
10
ns
–104
–80
–68
–108
–92
–81
–78
–64
–95
–78
78
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
2nd Order Harmonic Distortion
(Single-ended input)
f = 50 MHz
f = 100 MHz
f = 10 MHz
C
3rd Order Harmonic Distortion
(Single-ended input)
f = 50 MHz
f = 100 MHz
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
2nd Order Intermodulation Distortion
(Single-ended input)
VO = 2 Vpp envelope,
200 kHz Tone Spacing,
RL = 499 Ω
3rd Order Intermodulation Distortion
(Single-ended input)
2nd Order Output Intercept Point
(Single-ended input)
58
200 kHz Tone Spacing
43
3rd Order Output Intercept Point
(Single-ended input)
38
fC = 70 MHz
12.2
10.8
17.1
1.9
1-dB Compression Point(2)
dBm
Typ
fC = 140 MHz
50 Ω System, 10 MHz
f > 10 MHz
Noise Figure
dB
Typ
Typ
Typ
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
nV/√Hz
pA/√Hz
f > 10 MHz
2.2
Open-Loop Voltage Gain (AOL
)
68
dB
mV
Typ
Max
Typ
Max
Typ
Max
Typ
C
B
Input Offset Voltage
0.5
0.8
8
1
Average Offset Voltage Drift
Input Bias Current
2.6
13
20
4.5
4
µV/°C
µA
6
A
B
A
B
Average Bias Current Drift
Input Offset Current
nA/°C
µA
1.6
3.6
Average Offset Current Drift
INPUT
nA/°C
Common-Mode Input Range High
Common-Mode Input Range Low
Common-Mode Rejection Ratio
1.75
–1.75
90
V
V
Max
Min
Min
A
B
dB
(1) Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(2) The 1-dB compression point is measured at the load with 50-Ω double termination. Add 3 dB to refer to amplifier output.
3
THS4509
www.ti.com
SLOS454–JANUARY 2005
SPECIFICATIONS; VS+– VS– = 5 V: (continued)
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5 V, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Differential Output, Input and Output Referenced to Mid-supply
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
–40°C to
85°C
MIN/
MAX
TEST
LEVEL(1)
25°C
25°C
UNITS
OUTPUT
Maximum Output Voltage High
Minimum Output Voltage Low
Differential Output Voltage Swing
Differential Output Current Drive
Output Balance Error
1.4
–1.4
5.6
1.35
–1.35
5.4
1.13
–1.13
4.5
V
V
Min
Max
Min
Typ
Typ
Typ
Each output with 100 Ω to mid-supply
A
C
V
RL = 10 Ω
96
mA
dB
Ω
VO = 100 mV, f = 1 MHz
f = 1 MHz
–49
0.3
Closed-Loop Output Impedance
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-Signal Bandwidth
700
110
1
MHz
V/µs
V/V
mV
Typ
Typ
Typ
Typ
Typ
Slew Rate
Gain
Output Common-Mode Offset from CM input
CM Input Bias Current
–1 V < CM < 1 V
–1 V < CM < 1 V
5
C
±40
µA
–1.5 to
1.5
CM Input Voltage Range
V
Typ
CM Input Impedance
23
1
kΩ pF
Typ
Typ
CM Default Voltage
0
5
V
POWER SUPPLY
Specified Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection (±PSRR)
POWERDOWN
5.5
5.5
38.7
36
V
Max
Max
Min
Min
C
A
C
37.7
37.7
90
38.6
36.4
mA
mA
dB
Referenced to Vs–
Device Assured on above 2.1 V
,
Enable Voltage Threshold
Disable Voltage Threshold
1.6
1.6
V
V
Min
C
A
Referenced to Vs–
,
Max
Device Assured off below 0.7 V
Powerdown Quiescent Current
Input Bias Current
0.65
100
0.76
0.89
mA
µA
Max
Typ
Typ
Typ
Typ
PD = VS–
Input Impedance
50
2
kΩ pF
ns
C
Turn-on Time Delay
Turn-off Time Delay
Measured to output on
Measured to output off
55
10
µs
4
THS4509
www.ti.com
SLOS454–JANUARY 2005
SPECIFICATIONS; VS+– VS– = 3 V:
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, CM = open, VO = 1 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Differential Output, Input and Output Referenced to Mid-supply
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
–40°C to
85°C
MIN/
MAX
TEST
LEVEL(1)
25°C
25°C
UNITS
AC PERFORMANCE
G = 6 dB, VO = 100 mVpp
1.9
1.6
GHz
GHz
MHz
MHz
GHz
MHz
GHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
G = 10 dB, VO = 100 mVpp
G = 14 dB, VO = 100 mVpp
G = 20 dB, VO = 100 mVpp
G = 20 dB
Small-Signal Bandwidth
625
260
3
Gain-Bandwidth Product
Bandwidth for 0.1dB flatness
Large-Signal Bandwidth
Slew Rate (Differential)
Rise Time
G = 10 dB, VO = 1 Vpp
G = 10 dB, VO = 1 Vpp
1V Step
400
1.5
3500
0.25
0.25
1
1V Step
Fall Time
1V Step
ns
Settling Time to 1%
VO = 1 V Step
f = 10 MHz
ns
–107
–83
–60
–87
–65
–54
–77
–54
–77
–62
72
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
dBm
dBm
dBm
2nd Order Harmonic Distortion
(Single-ended input)
f = 50 MHz
f = 100 MHz
f = 10 MHz
C
3rd Order Harmonic Distortion
(Single-ended input)
f = 50 MHz
f = 100 MHz
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
fC = 70 MHz
fC = 140 MHz
2nd Order Intermodulation Distortion
(Single-ended input)
VO = 1 Vpp envelope,
200 kHz Tone Spacing,
RL = 200 Ω
3rd Order Intermodulation Distortion
(Single-ended input)
2nd Order Output Intercept Point
(Single-ended input)
52
200 kHz Tone Spacing
38.5
30
3rd Order Output Intercept Point
(Single-ended input)
fc = 70 MHz
2.2
1-dB Compression Point(2)
dBm
Typ
fc = 140 MHz
50 Ω System, 10 MHz
f > 10 MHz
0.25
17.1
1.9
Noise Figure
dB
Typ
Typ
Typ
Input Voltage Noise
Input Current Noise
DC PERFORMANCE
nV/√Hz
pA/√Hz
f > 10 MHz
2.2
Open-Loop Voltage Gain (AOL
)
68
dB
mV
Typ
Max
Typ
Max
Typ
Max
Typ
C
B
Input Offset Voltage
0.5
0.8
8
1
Average Offset Voltage Drift
Input Bias Current
2.6
13
20
4.5
4
µV/°C
µA
6
A
B
A
B
Average Bias Current Drift
Input Offset Current
nA/°C
µA
1.6
3.6
Average Offset Current Drift
INPUT
nA/°C
Common-Mode Input Range High
Common-Mode Input Range Low
Common-Mode Rejection Ratio
0.75
–0.75
80
V
V
Max
Min
Min
A
B
dB
(1) Test levels: (A) 100% tested at 25°C. Overtemperature limits by characterization and simulation. (B) Limits set by characterization and
simulation. (C) Typical value only for information.
(2) The 1-dB compression point is measured at the load with 50-Ω double termination. Add 3 dB to refer to amplifier output.
5
THS4509
www.ti.com
SLOS454–JANUARY 2005
SPECIFICATIONS; VS+– VS– = 3 V: (continued)
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5 V, CM = open, VO = 1 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Differential Output, Input and Output Referenced to Mid-supply
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
–40°C to
85°C
MIN/
MAX
TEST
LEVEL(1)
25°C
25°C
UNITS
OUTPUT
Maximum Output Voltage High
Minimum Output Voltage Low
Differential Output Voltage Swing
Differential Output Current Drive
Output Balance Error
0.45
–0.45
1.8
0.43
–0.43
1.65
18
0.2
–0.2
0.8
18
V
V
Min
Max
Min
Min
Typ
Typ
Each output with 100Ω to mid-supply
A
C
V
RL = 20 Ω
20
mA
dB
Ω
VO = 100 mV, f = 1 MHz
f = 1 MHz
–49
0.3
Closed-Loop Output Impedance
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-Signal Bandwidth
Slew Rate
570
60
1
MHz
V/µs
V/V
mV
Typ
Typ
Typ
Typ
Typ
Gain
Output Common-Mode Offset from CM input
CM Input Bias Current
–0.5 V < CM < 0.5 V
4
C
–0.5 V < CM < 0.5 V
±40
µA
–1.5 to
1.5
CM Input Voltage Range
V
Typ
CM Input Impedance
20
1
kΩ pF
Typ
Typ
CM Default Voltage
0
3
V
POWER SUPPLY
Specified Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
Power Supply Rejection (±PSRR)
POWERDOWN
5.5
5.5
36
33
V
Max
Max
Min
Min
34.8
34.8
78
35.8
33.8
mA
mA
dB
A
C
Referenced to Vs–
Device Assured on above 2.1 V
Enable Voltage Threshold
Disable Voltage Threshold
V
V
Min
C
A
Referenced to Vs–
Device Assured off below 0.7 V
Max
Powerdown Quiescent Current
Input Bias Current
0.46
65
0.53
0.67
mA
µA
Max
Typ
Typ
Typ
Typ
PD = VS–
Input Impedance
50
2
kΩ pF
ns
C
Turn-on Time Delay
Turn-off Time Delay
Measured to output on
Measured to output off
100
10
µs
6
THS4509
www.ti.com
SLOS454–JANUARY 2005
DEVICE INFORMATION
TOP VIEW
RGT Package
THS4509
V
S−
16
15
14
13
NC
PD
V
1
2
3
4
12
11
10
9
V
IN−
IN+
V
V
OUT−
OUT+
CM
CM
6
7
5
8
V
S+
TERMINAL FUNCTIONS
TERMINAL
(RGT PACKAGE)
DESCRIPTION
NO.
NAME
NC
1
No internal connection
2
VIN–
Inverting amplifier input
3
VOUT+
CM
Non-inverted amplifier output
Common-mode voltage input
Positive amplifier power supply input
Inverted amplifier output
4,9
5,6,7,8
10
VS+
VOUT–
VIN+
PD
11
Non-inverting amplifier input
12
Powerdown, PD = logic low puts part into low power mode, PD = logic high or open for normal operation
Negative amplifier power supply input
13,14,15,16 VS–
7
THS4509
www.ti.com
SLOS454–JANUARY 2005
TYPICAL CHARACTERISTICS
TYPICAL AC PERFORMANCE: VS+– VS– = 5 V
Test conditions unless otherwise noted: VS+ = +2.5 V, VS– = –2.5V, CM = open, VO = 2 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Input and Output Referenced to Midrail
Small-Signal Frequnecy Response
Large Signal Frequnecy Response
0.1 dB Flatness
Figure 1
Figure 2
Figure 3
HD2, G = 6 dB, VOD = 2 VPP
HD3, G = 6 dB, VOD = 2 VPP
HD2, G = 10 dB, VOD = 2 VPP
HD3, G = 10 dB, VOD = 2 VPP
HD2, G = 14 dB, VOD = 2 VPP
HD3, G = 14 dB, VOD = 2 VPP
HD2, G = 10 dB
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Output voltage
vs Output voltage
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Output Voltage
Figure 4
Figure 5
Figure 6
Figure 7
Harmonic
Distortion
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
Figure 32
Figure 33
Figure 34
Figure 35
Figure 36
Figure 37
Figure 38
Figure 39
Figure 40
Figure 41
HD3, G = 10 dB
IMD2, G = 6 dB, VOD = 2 VPP
IMD3, G = 6 dB, VOD = 2 VPP
IMD2, G = 10 dB, VOD = 2 VPP
IMD3, G = 10 dB, VOD = 2 VPP
IMD2, G = 14 dB, VOD = 2 VPP
IMD3, G = 14 dB, VOD = 2 VPP
OIP2
Intermodulation
Distortion
Output Intercept Point
OIP3
S-Parameters
Slew Rate
Transient Response
Settling Time
Rejection Ratio
vs Frequency
vs Frequency
Output Impedance
Overdrive Recovery
Output Voltage Swing
Turn-Off Time
vs Load Resistance
Turn-On Time
Input Offset Voltage
Open Loop Gain
Input Referred Noise
Noise Figure
vs Input Common-Mode Voltage
vs Frequency
vs Frequency
vs Frequency
Quiescent Current
Power Supply Current
Output Balance Error
CM Input Impedence
vs Supply Voltage
vs Supply Voltage in Powerdown Mode
vs Frequency
vs Frequency
CM Small-Signal Frequency Response
CM Input Bias Current
vs CM Input Voltage
vs CM Input Voltage
vs CM Input Voltage
Differential Output Offset Voltage
Output Common-Mode Offset
8
THS4509
www.ti.com
SLOS454–JANUARY 2005
SMALL-SIGNAL
FREQUNECY RESPONSE
LARGE-SIGNAL
FREQUNECY RESPONSE
0.1-dB FLATNESS
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
10.2
10.1
10
G = 20 dB
mV
= 100
V
PP
OD
V
= 2 V
PP
OD
V
= 2 V
PP
OD
G = 20 dB
G = 14 dB
G = 14 dB
G = 10 dB
G = 10 dB
G = 6 dB
G = 6 dB
6
6
9.9
4
4
2
2
0
0
9.8
0.1
1
10
100
1000
10000
0.1
1
10
100
1000 10000
0.1
1
10
100
1000
f - Frequency - MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 1.
Figure 2.
Figure 3.
HD2
vs
FREQUENCY
HD3
vs
FREQUENCY
HD2
vs
FREQUENCY
−60
−70
−60
−70
−60
−70
G = 10 dB,
G = 6 dB,
= 2 V
G = 6 dB,
= 2 V
V
= 2 V
V
OD
PP
OD
PP
V
OD
PP
R
L
= 100 Ω
−80
−80
−80
−90
R
= 200 Ω
L
R
L
= 100 Ω
R
L
= 100 Ω
−90
−90
R
L
= 200 Ω
R
L
= 1 kΩ
−100
−100
−110
−120
−100
−110
−120
R
L
= 1 kΩ
R
= 1 kΩ
R
= 500 Ω
L
L
−110
−120
R
L
= 200 Ω
R
L
= 500 Ω
R
L
= 500 Ω
10
100
1000
1
1
10
100
1000
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 4.
Figure 5.
Figure 6.
HD3
vs
FREQUENCY
HD2
vs
FREQUENCY
HD3
vs
FREQUENCY
−60
−70
−60
−60
−70
G = 14 dB,
G = 14 dB,
= 2 V
G = 10 dB,
= 2 V
V
= 2 V
OD
PP
V
V
OD
PP
OD
PP
−70
−80
R
L
= 100 Ω
−80
−80
R
L
= 200 Ω
R
L
= 100 Ω
R
L
= 500 Ω
R
L
= 500 Ω
−90
−90
−90
R
L
= 1 kΩ
R
L
= 1 kΩ
−100
−110
−120
R
= 200 Ω
−100
−110
−120
L
−100
R
= 100 Ω
L
R
L
= 500 Ω
−110
−120
R
= 200 Ω
R
L
= 1 kΩ
L
1
10
100
1000
1
10
100
1000
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 7.
Figure 8.
Figure 9.
9
THS4509
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HD2
vs
HD3
vs
IMD2
vs
FREQUENCY
OUTPUT VOLTAGE
OUTPUT VOLTAGE
-60
−30
−40
−50
-60
f = 64 MHz
Gain = 6 dB,
= 2 V Envelope
R
L
= 200 Ω
V
OD
PP
-70
-70
R
L
= 100 Ω
f = 32 MHz
f = 64 MHz
-80
-80
f = 32 MHz
−60
−70
f = 8 MHz
-90
-90
f = 16 MHz
R
= 500 Ω
L
-100
-110
-120
-100
-110
-120
−80
R
= 1 kΩ
L
−90
f = 8 MHz
f = 16 MHz
−100
0
50
100
150
200
4
0
1
3
2
0
1
2
3
4
f − Frequency − MHz
V
OD
- V
PP
V
OD
- V
PP
Figure 10.
Figure 11.
Figure 12.
IMD3
vs
FREQUENCY
IMD2
vs
FREQUENCY
IMD3
vs
FREQUENCY
−30
−40
−50
−60
−70
−80
−90
−60
−65
−70
−75
−80
−85
−90
−95
−100
−60
−65
−70
−75
−80
−85
−90
−95
−100
R
= 100 Ω
Gain = 6 dB,
= 2 V Envelope
Gain = 10 dB,
= 2 V Envelope
L
R
= 100 Ω
L
Gain = 10 dB,
= 2 V Envelope
V
V
OD
PP
OD
PP
V
OD
PP
R
= 200 Ω
L
R
L
= 200 Ω
R
L
= 200 Ω
R
L
= 100 Ω
R
L
= 1 kΩ
R
= 500 Ω
L
R
= 1 kΩ
L
R
L
= 1 kΩ
R
= 500 Ω
L
R
= 500 Ω
L
−100
0
50
100
150
200
0
50
100
150
200
0
50
100
150
200
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 13.
Figure 14.
Figure 15.
IMD2
vs
FREQUENCY
IMD3
vs
FREQUENCY
OIP2
vs
FREQUENCY
−30
−40
−50
−60
−70
−80
−90
−60
−65
−70
−75
−80
−85
−90
90
85
80
75
70
65
60
55
50
45
40
Gain = 6 dB
Gain = 14 dB,
= 2 V Envelope
R
= 100 Ω
L
V
Gain = 14 dB,
= 2 V Envelope
OD
PP
Gain = 14 dB
V
OD
PP
R
= 200 Ω
L
R
L
= 200 Ω
R
L
= 100 Ω
Gain = 10 dB
R
L
= 500 Ω
R
= 1 kΩ
L
R
L
= 1 kΩ
−95
R
L
= 500 Ω
−100
−100
0
50
100
150
200
0
50
100
150
200
0
50
100
150
200
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 16.
Figure 17.
Figure 18.
10
THS4509
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SLOS454–JANUARY 2005
OIP3
vs
FREQUENCY
S-PARAMETERS
vs
FREQUENCY
SLEW RATE
vs
OUTPUT VOLTAGE
50
48
46
44
42
40
0
-10
-20
-30
-40
-50
-60
-70
8000
7000
6000
5000
4000
3000
2000
1000
0
S21
Gain = 6 dB
Rise
Fall
S11
Gain = 14 dB
Gain = 10 dB
38
36
34
32
30
S22
S12
0
50
100
150
200
0
0.5
1
1.5
2
2.5
3
3.5
4
1
10
100
1000
f − Frequency − MHz
V
− Differential Output Voltage − V
STEP
f = Frequency - MHz
OD
Figure 19.
Figure 20.
Figure 21.
REJECTION RATIO
vs
TRANSIENT RESPONSE
SETTLING TIME
FREQUENCY
1.5
5
4
3
2
1
0
100
90
80
70
60
50
40
30
20
10
0
V
= 2 V step
OD
PSRR−
1
PSRR+
CMRR
0.5
V
= 2 V step
OD
0
−0.5
−1
−1
−2
−3
−4
−5
−1.5
−0.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
0
0.5
1
1.5
2
2.5
3
0.01
0.1
1
10
100
1000
t − Time − ns
t − Time − ns
f − Frequency − MHz
Figure 22.
Figure 23.
Figure 24.
OUTPUT IMPEDANCE
vs
OUTPUT VOLTAGE SWING
vs
FREQUENCY
OVERDRIVE RECOVERY
LOAD RESISTANCE
7
6
5
4
3
2
1
0
100
10
1
5
4
3
2
1
0
1
Input
0.8
0.6
0.4
0.2
Output
0
−1
−2
−3
−0.2
−0.4
−0.6
−0.8
−1
−4
−5
0.1
0
0.2
0.4
0.6
0.8
1
0.1
1
10
100
1000
0
500
1000
1500
2000
t − Time − µs
f − Frequency− MHz
R
- Load Resistance - W
L
Figure 25.
Figure 26.
Figure 27.
11
THS4509
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SLOS454–JANUARY 2005
INPUT OFFSET VOLTAGE
vs
INPUT COMMON-MODE VOLTAGE
TURN-OFF TIME
TURN-ON TIME
5
40
5
4
3
2
1
0
2
1.6
1.2
0.8
0.4
0
2
1.6
1.2
0.8
0.4
0
35
30
25
20
15
10
5
4
3
PD
Output
Output
PD
2
1
0
0
−5
−2
0
2
4
6
8
10 12 14
−50
0
50
100
150
200
250
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
t − Time − µs
t − Time − ns
Input Common-Mode Voltage − V
Figure 28.
Figure 29.
Figure 30.
OPEN LOOP GAIN AND PHASE
INPUT REFERRED NOISE
NOISE FIGURE
vs
FREQUENCY
vs
vs
FREQUENCY
FREQUENCY
90
80
70
60
50
40
30
20
10
1000
100
10
20
50
19
18
17
16
15
14
13
12
11
10
Gain = 6 dB
50−Ω System
0
Phase
Gain
−50
Gain = 10 dB
Gain = 14 dB
In
−100
−150
−200
−250
Vn
0
Gain = 20 dB
−10
1
1
100
10 k
1 M
100 M 10 G
10
100
1 k
10 k 100 k 1 M
10 M
0
50
100
150
200
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − MHz
Figure 31.
Figure 32.
Figure 33.
POWER SUPPLY CURRENT
vs
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
OUTPUT BALANCE ERROR
SUPPLY VOLTAGE IN
POWERDOWN MODE
vs
FREQUENCY
800
700
600
500
400
300
200
100
40
10
T
= 85°C
A
T
= 25°C
= 85°C
A
0
−10
−20
−30
−40
−50
−60
T
= 25°C
T
A
= −40°C
A
±1.35
V
35
30
25
T
A
T
A
= −40°C
0
1
1.5
2
2.5
0.1
1
10
100
1000
0
0.5
1
1.5
2
2.5
V
− Supply Voltage − + V
S
V
− Supply Voltage − + V
f − Frequency − MHz
S
Figure 34.
Figure 35.
Figure 36.
12
THS4509
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SLOS454–JANUARY 2005
CM INPUT IMPEDANCE
CM INPUT BIAS CURRENT
vs
CM SMALL SIGNAL
FREQUENCY RESPONSE
vs
FREQUENCY
CM INPUT VOLTAGE
9
8
7
6
5
4
3
2
1
300
100
10
200
100
100 mV
PP
1
0.1
0
0
−1
−100
−2
−3
−4
−5
−6
−200
−300
0.01
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
0.1
1
10
100
1000
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
CM Input Voltage − V
Figure 37.
Figure 38.
Figure 39.
DIFFERENTIAL OUTPUT
OFFSET VOLTAGE
vs
OUTPUT COMMON-MODE OFFSET
vs
CM INPUT VOLTAGE
CM INPUT VOLTAGE
5
4
3
2
1
50
40
30
20
10
0
−10
−20
−30
−40
−50
0
−1
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
−2.5 −2 −1.5 −1 −0.5
0
0.5
1
1.5
2
2.5
CM Input Voltage − V
CM Input Voltage − V
Figure 40.
Figure 41.
13
THS4509
www.ti.com
SLOS454–JANUARY 2005
TYPICAL AC PERFORMANCE: VS+– VS– = 3 V
Test conditions unless otherwise noted: VS+ = +1.5 V, VS– = –1.5V, CM = open, VOD = 1 Vpp, RF = 349 Ω, RL = 200 Ω
Differential, G = 10 dB, Single-Ended Input, Input and Output Referenced to Midrail
Small-Signal Frequnecy Response
Large Signal Frequnecy Response
0.1 dB Flatness
Figure 42
Figure 43
Figure 44
Figure 45
Figure 46
Figure 47
Figure 48
Figure 49
Figure 50
Figure 51
Figure 52
Figure 53
Figure 54
Figure 55
Figure 56
Figure 57
Figure 58
Figure 59
Figure 60
Figure 61
Figure 62
Figure 63
Figure 64
Figure 65
Figure 66
Figure 67
Figure 68
Figure 69
Figure 70
Figure 71
Figure 72
Figure 73
Figure 74
HD2, G = 6 dB, VOD = 1 VPP
HD3, G = 6 dB, VOD = 1 VPP
HD2, G = 10 dB, VOD = 1 VPP
HD3, G = 10 dB, VOD = 1 VPP
HD2, G = 14 dB, VOD = 1 VPP
HD3, G = 14 dB, VOD = 1 VPP
IMD2, G = 6 dB, VOD = 1 VPP
IMD3, G = 6 dB, VOD = 1 VPP
IMD2, G = 10 dB, VOD = 1 VPP
IMD3, G = 10 dB, VOD = 1 VPP
IMD2, G = 14 dB, VOD = 1 VPP
IMD3, G = 14 dB, VOD = 1 VPP
OIP2
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Frequency
vs Output Voltage
Harmonic
Distortion
Intermodulation
Distortion
Ouput Intercept Point
OIP3
S-Parameters
Slew Rate
Transient Response
Settling Time
Output Voltage Swing
Rejection Ratio
vs Load Resistance
vs Frequency
Overdrive Recovery
Output Impedance
Turn-Off Time
vs Frequency
Turn-On Time
Ouput Balance Error
Noise Figure
vs Frequency
vs Frequency
CM Small-Signal Frequency Response
CM Input Impedance
Differential Output Offset Voltage
Output Common-Mode Offset
vs Frequency
vs CM Input Voltage
vs CM Input Voltage
14
THS4509
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SLOS454–JANUARY 2005
SMALL-SIGNAL
FREQUNECY RESPONSE
LARGE-SIGNAL
FREQUNECY RESPONSE
0.1 dB FLATNESS
10.2
10.1
10
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
G = 20 dB
V
= 1 V
PP
V
= 100 mV
PP
OD
OD
V
= 1 V
PP
OD
G = 20 dB
G = 14 dB
G = 14 dB
G = 10 dB
G = 6 dB
G = 10 dB
G = 6 dB
6
6
9.9
4
4
2
2
9.8
0
0
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
0.1
1
10
100
1000
10000
f − Frequency − MHz
f − Frequency − MHz
f− Frequency − MHz
Figure 42.
Figure 43.
Figure 44.
HD2
vs
FREQUENCY
HD3
vs
FREQUENCY
HD2
vs
FREQUENCY
−40
−50
−40
−50
−60
−70
−80
−90
−100
−40
−50
−60
−70
−80
−90
−100
G = 10 dB,
= 1 V
PP
G = 6 dB,
G = 6 dB,
= 1 V
V
V
= 1 V
OD
V
OD
PP
OD
PP
−60
−70
−80
R
L
= 200 Ω
R
L
= 100 Ω
R
L
= 100 Ω
−90
R
= 1 kΩ
L
R
L
= 200 Ω
R = 200 Ω
L
−100
−110
−120
R
L
= 1 kΩ
R
L
= 1 kΩ
−110
−120
R
L
= 500 Ω
R
L
= 500 Ω
R
L
= 500 Ω
1
10
100
1000
10
100
1000
1
10
100
1000
1
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 45.
Figure 46.
Figure 47.
HD3
vs
FREQUENCY
HD2
vs
FREQUENCY
HD3
vs
FREQUENCY
−40
−50
−40
−50
−60
−70
−80
−90
−100
−40
−50
−60
−70
−80
−90
−100
G = 10 dB,
= 1 V
G = 14 dB,
= 1 V
G = 14 dB,
V
OD
PP
V
OD
PP
V
= 1 V
OD
PP
−60
R
= 100 Ω
−70
R
L
= 100 Ω
L
−80
R
L
= 200 Ω
R
L
= 200 Ω
R
= 1 kΩ
L
−90
R
L
= 500 Ω
−100
−110
−120
R
= 500 Ω
R
L
= 500 Ω
L
L
R
L
= 200 Ω
R
= 1 kΩ
L
R
= 1 kΩ
10
100
1000
1
1
10
100
1000
10
100
1000
1
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 48.
Figure 49.
Figure 50.
15
THS4509
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SLOS454–JANUARY 2005
IMD2
IMD3
vs
FREQUENCY
IMD2
vs
FREQUENCY
vs
FREQUENCY
−30
−40
−50
−60
−70
−80
−90
−100
−30
−40
−50
−60
−70
−80
−90
−100
−30
−40
−50
−60
−70
R
= 500 Ω
Gain = 6 dB,
OD
Gain = 6 dB,
= 1 V Envelope
R
= 500 Ω
Gain = 10 dB,
OD
L
L
V
= 1 V Envelope
PP
V
V
= 1 V Envelope
PP
OD
PP
R
L
= 1 kΩ
R
= 100 Ω
L
R
L
= 1 kΩ
R = 1 kΩ
L
R
L
= 100 Ω
R
L
= 100 Ω
R
L
= 500 Ω
R
= 200 Ω
L
R
L
= 200 Ω
−80
−90
R
L
= 200 Ω
−100
0
50
100
150
200
0
0
0
50
100
150
200
200
150
0
50
100
150
200
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 51.
Figure 52.
Figure 53.
IMD3
vs
IMD2
vs
IMD3
vs
FREQUENCY
FREQUENCY
FREQUENCY
−30
−40
−50
−60
−70
−80
−30
−40
−50
−60
−70
−80
−90
−100
−30
−40
−50
−60
−70
−80
−90
Gain = 10 dB,
= 1 V Envelope
Gain = 14 dB,
= 1 V Envelope
R
L
= 500 Ω
Gain = 14 dB,
= 1 V Envelope
V
OD
PP
V
V
OD
PP
OD
PP
R
= 100 Ω
L
R
L
= 100 Ω
R
L
= 1 kΩ
R
L
= 100 Ω
R
L
= 500 Ω
R
L
= 500 Ω
R
L
= 1 kΩ
R
L
= 200 Ω
R
L
= 1 kΩ
R
L
= 200 Ω
−90
R
L
= 200 Ω
−100
−100
0
50
100
150
200
50
100
150
0
50
100
150
200
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 54.
Figure 55.
Figure 56.
OIP2, dBm
vs
FREQUENCY
OIP3, dBm
vs
S-PARAMETERS
vs
FREQUENCY
FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
90
85
80
75
70
65
60
55
50
45
40
50
48
46
44
42
40
38
36
34
32
30
Gain = 6 dB
S21
Gain = 6 dB
Gain = 10 dB
S11
Gain = 10 dB
S22
Gain = 14 dB
Gain = 14 dB
50
S12
100
0
50
100
150
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f = Frequency - MHz
Figure 57.
Figure 58.
Figure 59.
16
THS4509
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SLOS454–JANUARY 2005
SLEW RATE
vs
OUTPUT VOLTAGE
TRANSIENT RESPONSE
SETTLING TIME
4000
3500
3000
2500
2000
1500
1000
500
0.6
0.5
0.4
0.3
0.2
0.1
5
4
V
= 1 V step
OD
3
V
= 1 V step
OD
Rising
2
1
Falling
0
0
−0.1
−0.2
−1
−2
−3
−4
−5
−0.3
−0.4
−0.5
−0.6
0
0
0.2 0.4 0.6 0.8
1
1.2 1.4
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
−0.5
0
0.5
1
1.5
2
2.5
3
V
− Differential Output Voltage −V
OD
STEP
t − Time − ns
t − Time − ns
Figure 60.
Figure 61.
Figure 62.
OUTPUT VOLTAGE SWING
vs
REJECTION RATIO
vs
LOAD RESISTANCE
FREQUENCY
OVERDRIVE RECOVERY
2.5
0.6
0.4
0.2
3
2.5
2
90
80
70
60
50
40
30
20
10
0
Input
PSRR−
CMRR
2
1.5
1
PSRR+
1.5
0.5
Output
0
−0.5
−1
0
1
−0.2
−0.4
−0.6
−1.5
−2
0.5
−2.5
−3
0
0
0.2
0.4
0.6
0.8
1
0.01
0.1
1
10
100
1000
0
500
1000
1500
2000
t − Time − µs
f − Frequency − MHz
W
R
- Load Resistance -
L
Figure 63.
Figure 64.
Figure 65.
OUTPUT IMPEDANCE
vs
FREQUENCY
TURN-OFF TIME
TURN-ON TIME
1
0.8
0.6
1.2
1
3
100
10
1
3
2.5
2
2.5
2
PD
Output
0.8
0.6
0.4
0.2
0
1.5
1
1.5
1
Output
0.4
0.2
0
PD
0.5
0
0.5
0
0.1
0
50
100
150
200
250
−2
0
2
4
6
8
10 12 14
0.1
1
10
100
1000
t − Time − µs
t − Time − ns
f − Frequency− MHz
Figure 66.
Figure 67.
Figure 68.
17
THS4509
www.ti.com
SLOS454–JANUARY 2005
OUTPUT BALANCE ERROR
NOISE FIGURE
vs
FREQUENCY
vs
CM SMALL SIGNAL
FREQUENCY RESPONSE
FREQUENCY
5
4
3
2
1
10
20
19
18
17
16
15
14
13
12
100 mV
PP
Gain = 6 dB
50−Ω System
0
−10
Gain = 10 dB
Gain = 14 dB
−20
−30
−40
−50
−60
0
−1
−2
−3
−4
−5
−6
Gain = 20 dB
50
11
10
0
100
150
200
0.1
1
10
100
1000
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 69.
Figure 70.
Figure 71.
DIFFERENTIAL OUTPUT OFFSET
CM INPUT IMPEDANCE
VOLTAGE
vs
OUTPUT COMMON-MODE OFFSET
vs
vs
FREQUENCY
CM INPUT VOLTAGE
CM INPUT VOLTAGE
50
100
10
5
4
3
2
1
0
40
30
20
10
1
0
−10
−20
0.1
0.01
−30
−40
−50
−1
−1.5
−1.5
−1
−0.5
0
0.5
1
1.5
−1
−0.5
0
0.5
1
1.5
0.1
1
10
100
1000
f − Frequency − MHz
CM Input Voltage − V
CM Input Voltage − V
Figure 72.
Figure 73.
Figure 74.
18
THS4509
www.ti.com
SLOS454–JANUARY 2005
TEST CIRCUITS
The output is probed using a high-impedance differ-
ential probe across the 100-Ω resistor. The gain is
referred to the amplifier output by adding back the
6-dB loss due to the voltage divider on the output.
The THS4509 is tested with the following test circuits
built on the EVM. For simplicity, power supply de-
coupling is not shown – see layout in the applications
section for recommendations. Depending on the test
conditions, component values are changed per the
following tables, or as otherwise noted. The signal
generators used are ac coupled 50-Ω sources and a
0.22-µF capacitor and a 49.9-Ω resistor to ground are
inserted across RIT on the alternate input to balance
the circuit. A split power supply is used to ease the
interface to common test equipment, but the amplifier
can be operated single-supply as described in the
applications section with no impact on performance.
V
IN
R
R
F
G
From
50 Ω
Source
V
S+
R
R
IT
49.9 Ω
49.9 Ω
Output Measured
Here With High
Impedance
100 Ω
THS4509
CM
R
G
Differential Probe
0.22 µF
49.9 Ω
Open
0.22 µF
IT
V
S−
R
F
Figure 75. Frequency Response Test Circuit
Table 1. Gain Component Values
GAIN
6 dB
RF
RG
RIT
Distortion and 1dB Compression
348 Ω
348 Ω
348 Ω
348 Ω
165 Ω
100 Ω
56.2 Ω
16.5 Ω
61.9 Ω
69.8 Ω
88.7 Ω
287 Ω
The circuit shown in Figure 76 is used to measure
harmonic distortion, intermodulation distortion, and
1-db compression point of the amplifier.
10 dB
14 dB
20 dB
A signal generator is used as the signal source and
the output is measured with a spectrum analyzer. The
output impedance of the signal generator is 50 Ω. RIT
and RG are chosen to impedance-match to 50 Ω, and
to maintain the proper gain. To balance the amplifier,
a 0.22-µF capacitor and 49.9-Ω resistor to ground are
inserted across RIT on the alternate input.
Note the gain setting includes 50-Ω source im-
pedance. Components are chosen to achieve gain
and 50-Ω input termination.
Table 2. Load Component Values
RL
RO
ROT
Atten.
6 dB
A low-pass filter is inserted in series with the input to
reduce harmonics generated at the signal source.
The level of the fundamental is measured, then a
high-pass filter is inserted at the output to reduce the
fundamental so that it does not generate distortion in
the input of the spectrum analyzer.
100 Ω
200 Ω
499 Ω
1k Ω
25 Ω
open
86.6 Ω
237 Ω
487 Ω
69.8 Ω
56.2 Ω
52.3 Ω
16.8 dB
25.5 dB
31.8 dB
Note the total load includes 50-Ω termination by
the test equipment. Components are chosen to
achieve load and 50-Ω line termination through a
1:1 transformer.
The transformer used in the output to convert the
signal from differential to single ended is an
ADT1-1WT. It limits the frequency response of the
circuit so that measurements cannot be made below
approximately 1MHz.
Due to the voltage divider on the output formed by
the load component values, the amplifier's output is
attenuated. The column Atten in Table 2 shows the
attenuation expected from the resistor divider. When
using a transformer at the output as shown in
Figure 76, the signal will see slightly more loss, and
these numbers will be approximate.
V
IN
R
R
F
G
From
50 Ω
Source
V
S+
R
R
IT
V
OUT
R
R
O
To 50 Ω
Test
Equipment
1:1
R
OT
THS 4509
CM
R
IT
G
O
0.22 µF
49.9 Ω
Frequency Response
Open
0.22 µF
V
S−
The circuit shown in Figure 75 is used to measure the
frequency response of the circuit.
R
F
Figure 76. Distortion Test Circuit
A network analyzer is used as the signal source and
as the measurement device. The output impedance
of the network analyzer is 50 Ω. RIT and RG are
chosen to impedance match to 50 Ω, and to maintain
the proper gain. To balance the amplifier, a 0.22-µF
capacitor and 49.9-Ω resistor to ground are inserted
across RIT on the alternate input.
The 1-dB compression point is measured with a
spectrum analyzer with 50-Ω double termination or
19
THS4509
www.ti.com
SLOS454–JANUARY 2005
100-Ω termination as shown in Table 2. The input
power is increased until the output is 1 dB lower than
expected. The number reported in the table data is
the power delivered to the spectrum analyzer input.
Add 3 dB to refer to the amplifier output.
at VOUT+ or VOUT– with the input injected at VIN, RCM =
0 Ω and RCMT = 49.9 Ω. The input impedance is
measured with RCM = 49.9 Ω with RCMT = open, and
calculated by measuring the voltage drop across RCM
to determine the input current.
RG
RF
S-Parameter, Slew Rate, Transient Response, Set-
tling Time, Output Impedance, Overdrive, Output
Voltage, and Turn-On/Off Time
VS+
0.22 mF
RIT
49.9 W
To
49.9 W
VOUT–
The circuit shown in Figure 77 is used to measure
s-parameters, slew rate, transient response, settling
time, output impedance, overdrive recovery, output
voltage swing, and turn-on/turn-off times of the ampli-
fier. For output impedance, the signal is injected at
VOUT with VIN left open and the drop across the 49.9
Ω resistor is used to calculate the impedance seen
looking into the amplifier’s output.
50-ohm
Test
THS4509
RG
49.9 W
VOUT+
Equipment
0.22 mF
CM
RCM
RIT
VIN From
50-ohm
source
VS–
RF
49.9 W
RCMT
Figure 78. CM Input Test Circuit
CMRR and PSRR
Because S21 is measured single-ended at the load
with 50-Ω double termination, add 12 dB to refer to
the amplifier’s output as a differential signal.
The circuit shown in Figure 79 is used to measure the
CMRR and PSRR of VS+ and VS–. The input is
switched appropriately to match the test being per-
formed.
V
IN
From
50 Ω
R
R
F
G
G
Source
V
S+
R
R
IT
49.9 Ω
49.9 Ω
V
V
348 Ω
OUT+
V
To 50 Ω
Test
Equipment
S+
THS 4509
CM
R
V
S+
PSRR+
OUT−
V
IN
0.22 µF
49.9 Ω
49.9 Ω
49.9 Ω
Output
Measured
Here
With High
Impedance
Differential
Probe
From
50 Ω
Source
100 Ω
100 Ω
Open
0.22 µF
IT
CMRR
PSRR−
V
THS4509
CM
100 Ω
S−
R
F
Open
0.22 µF
V
S−
69.8 Ω
V
S−
Figure 77. S-Parameter, SR, Transient Response,
Settling Time, ZO, Overdrive Recovery, VOUT
Swing, and Turn-on/off Test Circuit
348 Ω
Figure 79. CMRR and PSRR Test Circuit
CM Input
The circuit shown in Figure 78 is used to measure the
frequency response and input impedance of the CM
input. Frequency response is measured single-ended
20
THS4509
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SLOS454–JANUARY 2005
APPLICATION INFORMATION
R
R
G
F
Single-Ended
APPLICATIONS
Input
V
Differential
S
The following circuits show application information for
the THS4509. For simplicity, power supply decoupling
capacitors are not shown in these diagrams. Please
see the Subsection 1 section for recommendations.
For more detail on the use and operation of fully
differential op amps refer to application report
Fully-Differential Amplifiers (SLOA054) .
Output
V
OUT–
+
–
THS
4509
R
G
+
–
V
OUT+
V
S
Differential Input to Differential Output Amplifier
R
F
The THS4509 is a fully differential op amp, and can
be used to amplify differential input signals to differ-
ential output signals. A basic block diagram of the
circuit is shown in Figure 80 (CM input not shown).
The gain of the circuit is set by RF divided by RG.
Figure 81. Single-Ended Input to Differential
Output Amplifier
Input Common-Mode Voltage Range
R
F
The input common-model voltage of a fully differential
op amp is the voltage at the '+' and '–' input pins of
the op amp.
Differential
Differential
V
S+
Input
Output
It is important to not violate the input common-mode
voltage range (VICR) of the op amp. Assuming the op
amp is in linear operation the voltage across the input
pins is only a few millivolts at most. So finding the
voltage at one input pin will determine the input
common-mode voltage of the op amp.
R
G
V
V
IN+
OUT–
+
–
THS4509
R
G
V
IN–
+
V
OUT+
–
V
S–
Treating the negative input as a summing node, the
voltage is given by Equation 1:
R
F
æ
ö
æ
ö
R
R
G
F
ç
= V
ç
÷
ç
+ V
IN-
ç
÷
V
IC
´
´
OUT+
÷
÷
R
+ R
R
+ R
Figure 80. Differential Input to Differential Ouput
Amplifier
G
F
G
F
ø
è
ø
è
(1)
To determine the VICR of the op amp, the voltage at
the negative input is evaluated at the extremes of
Depending on the source and load, input and output
termination can be accomplished by adding RIT and
RO.
VOUT+
.
As the gain of the op amp increases, the input
common-mode voltage becomes closer and closer to
the input common-mode voltage of the source.
Single-Ended Input to Differential Output Ampli-
fier
Setting the Output Common-Mode Voltage
The THS4509 can be used to amplify and convert
single-ended input signals to differential output sig-
nals. A basic block diagram of the circuit is shown in
Figure 81 (CM input not shown). The gain of the
circuit is again set by RF divided by RG.
The output common-mode voltage is set by the
voltage at the CM pin(s). The internal common-mode
control circuit maintains the output common-mode
voltage within 3-mV offset (typ) from the set voltage,
when set within 0.5 V of mid-supply, with less than
4mV differential offset voltage. If left unconnected,
the common-mode set point is set to mid-supply by
internal circuitry, which may be over-driven from an
external source. Figure 82 is representative of the
CM input. The internal CM circuit has about 700 MHz
of –3-dB bandwidth, which is required for best per-
21
THS4509
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SLOS454–JANUARY 2005
formance, but it is intended to be a DC bias input pin.
Bypass capacitors are recommended on this pin to
reduce noise at the output. The external current
required to overdrive the internal resistor divider is
given by Equation 2:
RS
RG
RF
VS+
RT
VSignal
VBias= VCM
RS
RO
VCM
VOUT-
2V - (V - V )
CM S+ S-
THS4509
RG
RO
I
=
EXT
VOUT+
50 kW
CM
(2)
RT
VS–
where VCM is the voltage applied to the CM pin.
VCM
VCM VCM
RF
V
S+
Figure 83. THS4509 DC Coupled Single-Supply
with Input Biased to VCM
50 kW
I
EXT
to internal
In Figure 84 the source is referenced to ground and
so is the input termination resistor. RPU is added to
the circuit to avoid violating the VICR of the op amp.
The proper value of resistor to add can be calculated
from Equation 3:
CM
CM circuit
50 kW
V
(V - V )
IC S+
S–
R
=
PU
æ
ö
æ
ö
1
1
1
Figure 82. CM Input Circuit
ç
CMç
÷
÷
ç
IC ç
÷
÷
V
- V
+
R
R
R
F
IN
F
ø
è
ø
è
(3)
Single-Supply Operation (3V to 5V)
VIC is the desire input common-mode voltage, VCM
=
CM, and RIN = RG+ RS||RT. To set to mid-supply,
make the value of RPU = RG+ RS||RT.
To facilitate testing with common lab equipment, the
THS4509 EVM allows split-supply operation, and the
characterization data presented in this data sheet
was taken with split-supply power inputs. The device
can easily be used with a single-supply power input
without degrading the performance. Figure 83, Fig-
ure 84, and Figure 85 show DC and AC-coupled
single-supply circuits with single-ended inputs. These
configurations all allow the input and output com-
mon-mode voltage to be set to mid-supply allowing
for optimum performance. The information presented
here can also be applied to differential input sources.
Table 3 is a modification of Table 1 to add the proper
values with RPU assuming a 50 Ω source impedance
and setting the input and output common-mode
voltage to mid-supply.
There are two drawbacks to this configuration. One is
it requires additional current from the power supply.
Using the values shown for a gain of 10 dB requires
37 mA more current with 5 V supply, and 22 mA
more current with 3 V supply.
In Figure 83, the source is referenced to the same
voltage as the CM pin (VCM). VCM is set by the
internal circuit to mid-supply. RT along with the input
impedance of the amplifier circuit provides input
The other drawback is this configuration also in-
creases the noise gain of the circuit. In the 10 dB
gain case, noise gain increases by a factor of 1.5.
termination, which is also referenced to VCM
.
Table 3. RPU Values for Various Gains
Gain
6 dB
RF
RG
RIT
RPU
Note RS and RT are added to the alternate input from
the signal input to balance the amplifier. Alternately,
one resistor can be used equal to the combined value
RG+ RS||RT on this input. This is also true of the
circuits shown in Figure 84 and Figure 85.
348 Ω
348 Ω
348 Ω
348 Ω
169 Ω
102 Ω
61.9 Ω
40.2 Ω
64.9 Ω
78.7 Ω
115 Ω
221 Ω
200 Ω
133 Ω
97.6 Ω
80.6 Ω
10 dB
14 dB
20 dB
22
THS4509
www.ti.com
SLOS454–JANUARY 2005
is inserted in series with the input to reduce harmon-
ics and noise from the signal source. Input termin-
ation is accomplished via the 69.8-Ω resistor and
0.22-µF capacitor to ground in conjunction with the
input impedance of the amplifier circuit. A 0.22-µF
capacitor and 49.9-Ω resistor is inserted to ground
across the 69.8-Ω resistor and 0.22-µF capacitor on
the alternate input to balance the circuit. Gain is a
function of the source impedance, termination, and
348-Ω feedback resistor. Refer to Table 3 for
component values to set proper 50-Ω termination for
other common gains. A split power supply of +4V and
-1V is used to set the input and output common-mode
voltages to approximately mid-supply while setting
the input common-mode of the ADS5500 to the
recommended +1.55V. This maintains maximum
headroom on the internal transistors of the THS4509
to insure optimum performance.
VS+
RPU
RS
RG
RF
VS+
RT
VS+
VSignal
RO
VOUT-
RPU
RG
THS 4509
RO
VOUT+
CM
RS
RT
VS-
RF
Figure 84. THS4509 DC Coupled Single-Supply
with RPU Used to Set VIC
Figure 85 shows AC coupling to the source. Using
capacitors in series with the termination resistors
allows the amplifier to self-bias both input and output
to mid-supply.
VIN
From
100 W
348 W
50-W
source
4 V
69.3 W
14-bit,
C
125 MSPS
RS
RG
RF
100 W
0.22 mF
100 W
AIN +
ADS5500
THS 4509
2.7 pF
100 W
VS+=3V to 5V
RT
AIN -
CM
VSignal
CM
RO
49.9 W
49.9 W
69.8 W
0.22 mF
C
VOUT-
V
-1
0.22 mF
THS 4509
RG
RO
0.1 mF
0.1 mF
348 W
VOUT+
CM
RS
RT
VS-
Figure 86. THS4509 + ADS5500 Circuit
C
C
RF
90
85
80
75
70
65
SFDR (dBc)
Figure 85. THS4509 AC Coupled Single-Supply
THS4509 + ADS5500 Combined Performance
SNR (dBFS)
The THS4509 is designed to be a high performance
drive amplifier for high performance data converters
like the ADS5500 14-bit 125-MSPS ADC. Figure 86
shows a circuit combining the two devices, and
Figure 87 shows the combined SNR and SFDR
performance versus frequency with –1 dBFS input
signal level sampling at 125 MSPS. The THS4509
amplifier circuit provides 10 dB of gain, converts the
single-ended input to differential, and sets the proper
input common-mode voltage to the ADS5500. The
100-Ω resistors and 2.7-pF capacitor between the
THS4509 outputs and ADS5500 inputs along with the
input capacitance of the ADS5500 limit the bandwidth
of the signal to 115 MHz (–3 dB). For testing, a signal
generator is used for the signal source. The gener-
ator is an AC-coupled 50-Ω source. A band-pass filter
10
20
30
40
50
60
70
80
90
100 110
Input Frequency - MHz
Figure 87. THS4509 + ADS5500 SFDR and SNR
Performance versus Frequency
Figure 88 shows the 2-tone FFT of the THS4509 +
ADS5500 circuit with 65 MHz and 70 MHz input
frequencies. The SFDR is 90 dBc.
23
THS4509
www.ti.com
SLOS454–JANUARY 2005
VIN
100 W
348 W
From
50-W
5 V
source
69.8 W
14-bit,
105 MSPS
225 W
0.22 mF
AIN+
THS4509
2.7pF
ADS5424
100
225 W
AIN–
VBG
CM
49.9 W
69.8 W
49.9 W
0.22 mF
0.22 mF
0.1 mF
0.1 mF
348 W
Figure 89. THS4509 + ADS5424 Circuit
95
90
85
80
75
70
SFDR (dBc)
Figure 88. THS4509 + ADS5500 2-Tone FFT with
65 MHz and 70 MHz Input
THS4509 + ADS5424 Combined Performance
SNR (dBFS)
Figure 89 shows the THS4509 driving the ADS5424
ADC, and Figure 90 shows their combined SNR and
SFDR performance versus frequency with –1 dBFS
input signal level and sampling at 80 MSPS.
10
20
30
40
50
60
70
As before, the THS4509 amplifier provides 10 dB of
gain, converts the single-ended input to differential,
and sets the proper input common-mode voltage to
the ADS5424. Input termination and circuit testing is
the same as described above for the THS4509 +
ADS5500 circuit.
Input Frequency - MHz
Figure 90. THS4509 + ADS5424 SFDR and SNR
Performance vs Frequency
The 225-Ω resistors and 2.7-pF capacitor between
the THS4509 outputs and ADS5424 inputs (along
with the input capacitance of the ADC) limit the
bandwidth of the signal to about 100MHz (-3dB).
Since the ADS5424s recommended input com-
mon-mode voltage is 2.4 V, the THS4509 is operated
from a single power supply input with VS+ = 5 V and
VS– = 0 V (ground).
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THS4509
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SLOS454–JANUARY 2005
Layout Recommendations
0.144
0.049
It is recommended to follow the layout of the external
components near the amplifier, ground plane con-
struction, and power routing of the EVM as closely as
possible. General guidelines are:
0.012
Pin 1
1. Signal routing should be direct and as short as
possible into and out of the opamp circuit.
0.0095
2. The feedback path should be short and direct
avoiding vias.
0.015
0.144
0.0705
0.0195
3. Ground or power planes should be removed from
directly under the amplifier’s input and output
pins.
0.010
vias
0.032
4. An output resistor is recommended on each
output, as near to the output pin as possible.
0.030
5. Two 10-µF and two 0.1-µF power-supply decoup-
ling capacitors should be placed as near to the
power-supply pins as possible.
0.0245
Top View
Figure 91. QFN Etch and Via Pattern
6. Two 0.1-µF capacitors should be placed between
the CM input pins and ground. This limits noise
coupled into the pins. One each should be placed
to ground near pin 4 and pin 9.
7. It is recommended to split the ground pane on
layer 2 (L2) as shown below and to use a solid
ground on layer 3 (L3). A single-point connection
should be used between each split section on L2
and L3.
8. A single-point connection to ground on L2 is
recommended for the input termination resistors
R1 and R2. This should be applied to the input
gain resistors if termination is not used.
9. The THS4509 recommended PCB footprint is
shown in Figure 91.
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THS4509
www.ti.com
SLOS454–JANUARY 2005
THS4509 EVM
Figure 92 is the THS4509 EVAL1 EVM schematic, layers 1 through 4 of the PCB are shown Figure 93, and
Table 4 is the bill of material for the EVM as supplied from TI.
GND
J5
V
V
S−
J4
S+
J6
VEE
VCC
0.1 µF
C10
0.1 µF
C4
10 µF
10 µF
10 µF
10 µF
0.1 µF
0.1 µF
C12
TP1
C9
C6
C3
C5
C13
J8
R5
348 Ω
R1
69.8 Ω
VCC
VCC
8
R9
open
6
5
J1
7
R3
12
PD
J3
C15
3
100 Ω
R12
R7
C1
open
T1
2
V
V
−
O+
6
1
R11
69.8 Ω
86.6 Ω
R8
49.9 Ω
U1
0.22 µF
11
C8
open
C7
open
+
5
4
O−
PwrPad10
J2
R4
4
3
86.6 Ω
Vocm
9
XFMR_ADT4−1WT
C2
open
100 Ω
R2
69.8 Ω
15 13
14 16
R10
open
VEE
R6
J7
348 Ω
TP3
VEE
TP2
C14
0.1 µF
C11
0.1 µF
Figure 92. THS4509 EVAL1 EVM Schematic
Figure 93. THS4509 EVAL1 EVM Layer 1 through 4
26
THS4509
www.ti.com
SLOS454–JANUARY 2005
Table 4. THS4509 EVAL1 EVM Bill of Materials
ITEM
DESCRIPTION
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
PART NUMBER
1
2
CAP, 10.0 µF, Ceramic, X5R, 6.3V
CAP, 0.1 µF, Ceramic, X5R, 10V
CAP, 0.22 µF, Ceramic, X5R, 6.3V
OPEN
0805 C3, C4, C5, C6
0402 C9, C10, C11, C12, C13, C14
0402 C15
4
6
1
4
2
1
3
2
2
2
1
3
(AVX) 08056D106KAT2A
(AVX) 0402ZD104KAT2A
(AVX) 04026D224KAT2A
3
4
0402 C1, C2, C7, C8
0402 R9, R10
0402 R12
5
OPEN
6
Resistor, 49.9 Ω, 1/16W, 1%
Resistor, 69.8 Ω, 1/16W, 1%
Resistor, 86.6 Ω, 1/16W, 1%
Resistor, 100 Ω, 1/16W, 1%
Resistor, 348 Ω, 1/16W, 1%
Transformer, RF
(KOA) RK73H1ETTP49R9F
(KOA) RK73H1ETTP69R8F
(KOA) RK73H1ETTP86R6F
(KOA) RK73H1ETTP1000F
(KOA) RK73H1ETTP3480F
(MINI-CIRCUITS) ADT1-1WT
(HH SMITH) 101
8
0402 R1, R2, R11
0402 R7, R8
9
10
11
12
13
0402 R3, R4
0402 R5, R6
T1
Jack, banana receptance, 0.25" diameter
hole
J4, J5, J6
14
15
16
17
18
19
20
OPEN
J1, J7, J8
J2, J3
3
2
3
1
4
4
1
Connector, edge, SMA PCB Jack
Test point, Red
(JOHNSON) 142-0701-801
(KEYSTONE) 5000
(TI) THS4509RGT
TP1, TP2, TP3
U1
IC, THS4509
Standoff, 4-40 HEX, 0.625" length
SCREW, PHILLIPS, 4-40, 0.250"
Printed circuit board
(KEYSTONE) 1808
SHR-0440-016-SN
(TI) EDGE# 6468901
27
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jan-2005
PACKAGING INFORMATION
Orderable Device
THS4509RGTR
THS4509RGTT
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
QFN
RGT
16
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
QFN
RGT
16
250 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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