SN74SSTVF16857VRG4 [TI]
14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TVSOP 0 to 70;
| 型号： | SN74SSTVF16857VRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 14-Bit Registered Buffer With SSTL_2 Inputs and Outputs 48-TVSOP 0 to 70 光电二极管 逻辑集成电路 触发器 电视 |
| 文件： | 总12页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢇ ꢃ ꢋꢌꢍ ꢄ ꢎꢏꢐ ꢍ ꢀꢄ ꢏꢎꢏꢑ ꢌ ꢒꢆ ꢆꢏ ꢎ
ꢓ ꢍꢄ ꢔ ꢀꢀ ꢄꢕ ꢖ ꢗ ꢍꢁ ꢘꢒꢄ ꢀ ꢙꢁꢑ ꢚ ꢒꢄ ꢘ ꢒꢄꢀ
SCES411B – AUGUST 2002 – REVISED APRIL 2003
DGG PACKAGE
(TOP VIEW)
D
D
Member of the Texas Instruments
Widebus Family
Operates at 2.3 V to 2.7 V for PC1600,
PC2100, and PC2700; 2.5 V to 2.7 V for
PC3200
Q1
Q2
GND
D1
D2
GND
V
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
D
D
Pinout and Functionality Compatible With
JEDEC Standard SSTV16857
V
DDQ
Q3
CC
600 ps Faster (Simultaneous Switching)
Than JEDEC Standard SSTV16857 in
PC2700 DIMM Applications
Q4
Q5
GND
V
D
D
D
D
D
Output Edge-Control Circuitry Minimizes
Switching Noise in Unterminated DIMM
Load
DDQ
Q6 10
39 CLK
Q7
CLK
V
11
12
38
37
V
DDQ
CC
Outputs Meet SSTL_2 Class I
Specifications
GND 13
Q8 14
Q9 15
36 GND
35
V
REF
Supports SSTL_2 Data Inputs
34 RESET
Differential Clock (CLK and CLK) Inputs
V
16
33 D8
DDQ
Supports LVCMOS Switching Levels on the
RESET Input
GND 17
Q10 18
Q11 19
Q12 20
32 D9
31 D10
30 D11
29 D12
D
RESET Input Disables Differential Input
Receivers, Resets All Registers, and
Forces All Outputs Low
V
21
28
V
DDQ
CC
GND 22
Q13 23
Q14 24
27 GND
26 D13
25 D14
D
D
D
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 14-bit registered buffer is designed for 2.3-V to 2.7-V V
operation.
CC
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled circuits
optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.
The SN74SSTVF16857 operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
0°C to 70°C
TSSOP – DGG Tape and reel SN74SSTVF16857GR
SSTVF16857
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
Copyright 2003, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢀꢀ ꢄ ꢅꢆ ꢇꢈ ꢉ ꢊꢂ
ꢇꢃ ꢋꢌꢍ ꢄ ꢎ ꢏꢐꢍ ꢀꢄ ꢏ ꢎꢏꢑ ꢌꢒ ꢆꢆ ꢏꢎ
ꢓꢍ ꢄ ꢔ ꢀꢀ ꢄ ꢕ ꢖꢗ ꢍ ꢁ ꢘꢒ ꢄꢀ ꢙꢁ ꢑ ꢚ ꢒꢄꢘ ꢒꢄ ꢀ
SCES411B – AUGUST 2002 – REVISED APRIL 2003
description/ordering information (continued)
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (V
) inputs are allowed. In addition, when
REF
RESET is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET input always must
be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in
the low state during power up.
FUNCTION TABLE
INPUTS
CLK
OUTPUT
Q
RESET
CLK
D
H
↑
↓
H
H
L
H
H
L
↑
↓
L
L or H
L or H
X
Q
0
X, or floating X, or floating X, or floating
L
logic diagram (positive logic)
34
RESET
38
39
CLK
CLK
35
48
V
REF
One of 14 Channels
D1
1D
C1
1
Q1
R
To 13 Other Channels
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES411B – AUGUST 2002 – REVISED APRIL 2003
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
or V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
CC
DDQ
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
DDQ
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0 or V > V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O
O
DDQ
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V , V
Package thermal impedance, q (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
Storage temperature range, T
O
O
DDQ
CC DDQ
, or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
JA
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
NOM
MAX
2.7
UNIT
V
V
Supply voltage
V
V
CC
DDQ
2.3
PC1600, PC2100, PC2700
PC3200
2.7
Output supply voltage
V
V
DDQ
2.5
1.15
1.25
0
2.7
PC1600, PC2100, PC2700
PC3200
1.25
1.3
1.35
1.35
V
REF
Reference voltage (V
Input voltage
= V /2)
DDQ
REF
V
V
V
V
V
V
V
V
V
V
V
V
I
CC
AC high-level input voltage
AC low-level input voltage
DC high-level input voltage
DC low-level input voltage
High-level input voltage
Low-level input voltage
Data inputs
Data inputs
Data inputs
Data inputs
RESET
V
V
+310mV
+150mV
1.7
IH
IL
REF
V
V
–310mV
–150mV
V
REF
V
IH
IL
REF
V
REF
V
IH
IL
RESET
0.7
V
Common-mode input voltage range
Peak-to-peak input voltage
High-level output current
CLK, CLK
CLK, CLK
0.97
360
1.53
V
ICR
I(PP)
mV
mA
mA
°C
I
I
–16
16
OH
Low-level output current
OL
T
A
Operating free-air temperature
0
70
NOTE 4: The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential
inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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ꢓꢍ ꢄ ꢔ ꢀꢀ ꢄ ꢕ ꢖꢗ ꢍ ꢁ ꢘꢒ ꢄꢀ ꢙꢁ ꢑ ꢚ ꢒꢄꢘ ꢒꢄ ꢀ
SCES411B – AUGUST 2002 – REVISED APRIL 2003
electrical characteristics for PC1600, PC2100, and PC2700 over recommended operating free-air
temperature range (unless otherwise noted)
V
AND
CC
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
DDQ
2.3 V
V
V
I = –18 mA
I
–1.2
V
IK
I
I
I
I
= –100 µA
= –8 mA
= 100 µA
= 8 mA
2.3 V to 2.7 V
2.3 V
V
DDQ
1.95
–0.2
OH
OH
OL
OL
V
V
OH
2.3 V to 2.7 V
2.3 V
0.2
0.35
±5
V
OL
I
I
All inputs
V = V
CC
or GND
2.7 V
µA
µA
I
Static standby
Static operating
RESET = GND
10
I
I
I
= 0
= 0
2.7 V
CC
O
RESET = V , V = V
or V
or V
8
25
mA
CC
I
IH(AC)
IL(AC)
Dynamic operating –
clock only
RESET = V , V = V
CLK and CLK switching 50% duty cycle
,
,
µA/
MHz
CC
I
IH(AC)
IL(AC)
28
RESET = V , V = V or V
CLK and CLK switching 50% duty cycle,
One data input switching at
µA/
clock
MHz/
D input
CC IH(AC) IL(AC)
I
I
2.5 V
CCD
O
Dynamic operating –
per each data input
7
one-half clock frequency, 50% duty cycle
Data inputs
CLK, CLK
RESET
V = V
I
± 310 mV
2.5
2.5
2.3
3
3
3
3.5
3.5
3.5
REF
V
ICR
= 1.25 V, V
= 360mV
C
pF
2.5 V
I(PP)
or GND
i
V = V
I
CC
†
All typical values are at V
CC
= 2.5 V, T = 25°C.
A
electrical characteristics for PC3200 over recommended operating free-air temperature range
(unless otherwise noted)
V
AND
CC
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
V
DDQ
2.5 V
V
V
I = –18 mA
I
–1.2
V
IK
I
I
I
I
= –100 µA
= –8 mA
= 100 µA
= 8 mA
2.5 V to 2.7 V
2.5 V
V
DDQ
1.95
–0.2
OH
OH
OL
OL
V
V
OH
2.5 V to 2.7 V
2.5 V
0.2
0.35
±5
V
OL
I
I
All inputs
V = V
CC
or GND
2.7 V
µA
µA
I
Static standby
Static operating
RESET = GND
10
I
I
I
= 0
= 0
2.7 V
CC
O
RESET = V , V = V
or V
or V
8
25
mA
CC
I
IH(AC)
IL(AC)
Dynamic operating –
clock only
RESET = V , V = V
CLK and CLK switching 50% duty cycle
,
,
µA/
MHz
CC
I
IH(AC)
IL(AC)
28
RESET = V , V = V or V
CLK and CLK switching 50% duty cycle,
One data input switching at
µA/
clock
MHz/
D input
CC IH(AC) IL(AC)
I
I
2.6 V
CCD
O
Dynamic operating –
per each data input
7
one-half clock frequency, 50% duty cycle
Data inputs
CLK, CLK
RESET
V = V
I
± 310 mV
2.5
2.5
2.3
3
3
3
3.5
3.5
3.5
REF
V
ICR
= 1.25 V, V
= 360mV
C
pF
2.6 V
I(PP)
or GND
i
V = V
I
CC
†
All typical values are at V
CC
= 2.6 V, T = 25°C.
A
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCES411B – AUGUST 2002 – REVISED APRIL 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V
= 2.5 V
± 0.2 V
V
= 2.6 V
± 0.1 V
CC
CC
†
†
UNIT
MIN
MAX
MIN
MAX
f
t
t
t
Clock frequency
250
250
MHz
ns
clock
Pulse duration, CLK, CLK high or low
Differential inputs active time (see Note 5)
Differential inputs inactive time (see Note 6)
2
2
w
22
22
22
22
ns
act
ns
inact
Fast slew rate (see Notes 7 and 9)
0.75
0.9
0.75
0.9
t
Setup time
Hold time
ns
ns
Data before CLK↑, CLK↓
Data after CLK↑, CLK↓
su
Slow slew rate (see Notes 8 and 9)
Fast slew rate (see Notes 7 and 9)
Slow slew rate (see Notes 8 and 9)
0.75
0.9
0.75
0.9
t
h
†
For this test condition, V
always is equal to V .
CC
DDQ
must be held at a valid input level and data inputs must be held low for a minimum time of t
NOTES: 5. V
max, after RESET is taken high.
max, after RESET is taken
REF
act
6.
V
, data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of t
REF inact
low.
7. For data signal input slew rate ≥1 V/ns.
8. For data signal input slew rate ≥0.5 V/ns and <1 V/ns.
9. CLK, CLK signals input slew rates are ≥1 V/ns.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 2.5 V
± 0.2 V
V
= 2.6 V
± 0.1 V
CC
CC
FROM
(INPUT)
TO
(OUTPUT)
†
†
PARAMETER
UNIT
MIN
250
1.1
MAX
MIN
250
1.1
MAX
f
t
MHz
ns
max
‡
CLK and CLK
Q
Q
2.6
5
2.6
5
pd
t
ns
RESET
PHL
†
‡
For this test condition, V
Single bit switching
always is equal to V
.
DDQ
CC
5
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SCES411B – AUGUST 2002 – REVISED APRIL 2003
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
C
= 30 pF
L
R
= 500 Ω
L
(see Note A)
LOAD CIRCUIT
t
w
V
V
IH
V
REF
V
REF
Input
IL
VOLTAGE WAVEFORMS
PULSE DURATION
V
LVCMOS
RESET
Input
CC
V
CC
/2
V
CC
/2
0 V
V
I(PP)
t
t
act
inact
Timing
Inputs
V
ICR
V
ICR
I
(operating)
(standby)
I
CC
CC
90%
(see
Note B)
t
t
PHL
PLH
10%
I
CC
V
OH
/2
Output
VOLTAGE AND CURRENT WAVEFORMS
INPUTS ACTIVE AND INACTIVE TIMES
V
DDQ
/2
V
DDQ
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
V
I(PP)
V
V
IH
Timing
Inputs
LVCMOS
RESET
Input
V
ICR
V
CC
/2
IL
t
PHL
/2
t
t
h
su
V
V
V
OH
IH
V
Input
V
REF
Output
V
REF
DDQ
V
OL
IL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A.
B.
C
includes probe and jig capacitance.
tested with clock and data inputs held at V or GND, and I = 0 mA.
CC O
L
I
CC
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω,
O
input slew rate = 1 V/ns ±20% (unless otherwise noted).
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
H.
V
V
V
= V
= V
REF
/2
REF
IH
IL
DDQ
+ 310 mV (ac voltage levels) for differential inputs. V = V for LVCMOS input.
IH CC
– 310 mV (ac voltage levels) for differential inputs. V = GND for LVCMOS input.
= V
and t
PHL
REF
IL
t
are the same as t .
pd
PLH
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2006
PACKAGING INFORMATION
Orderable Device
SN74SSTVF16857GR
SN74SSTVF16857GRG4
SN74SSTVF16857VR
SN74SSTVF16857VRG4
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
48
48
48
48
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
TSSOP
TVSOP
TVSOP
DGG
DGV
DGV
2000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74SSTVF16857GR
SN74SSTVF16857VR
TSSOP
TVSOP
DGG
DGV
48
48
2000
2000
330.0
330.0
24.4
16.4
8.6
7.1
15.8
10.2
1.8
1.6
12.0
12.0
24.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Aug-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74SSTVF16857GR
SN74SSTVF16857VR
TSSOP
TVSOP
DGG
DGV
48
48
2000
2000
346.0
346.0
346.0
346.0
41.0
33.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74SSTVF16859SRG3
13-Bit to 26-Bit Registered Buffer with SSTL_2 Inputs and Outputs 56-VQFN 0 to 70
TI
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