SN74LV74ANSRG4 [TI]
LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SOP-14;
| 型号： | SN74LV74ANSRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, SOP-14 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总23页 (文件大小：1173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
D
D
D
D
D
2-V to 5.5-V V Operation
D
D
D
I
Supports Partial-Power-Down Mode
CC
off
Operation
Max t of 8.5 ns at 5 V
pd
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
(Output Ground Bounce)
OLP
<0.8 V at V = 3.3 V, T = 25°C
CC
A
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Typical V
(Output V Undershoot)
OHV
OH
>2.3 V at V = 3.3 V, T = 25°C
CC
A
Support Mixed-Mode Voltage Operation on
All Ports
− 1000-V Charged-Device Model (C101)
SN54LV74A . . . FK PACKAGE
SN54LV74A . . . J OR W PACKAGE
SN74LV74A . . . D, DB, DGV, NS,
OR PW PACKAGE
SN74LV74A . . . RGY PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1CLR
1D
1CLK
1PRE
1Q
VCC
2CLR
2D
1
2
3
4
5
6
7
14
13
12
11
1
14
3
2
1
20 19
18
2D
NC
2CLK
1CLK
NC
1PRE
NC
4
5
6
7
8
1D
1CLK
1PRE
1Q
13 2CLR
12 2D
2
3
4
5
6
17
16
2CLK
11
10
9
2CLK
2PRE
2Q
10 2PRE
15 NC
14
9 10 11 12 13
9
8
1Q
GND
2Q
2Q
2PRE
1Q
1Q
7
8
NC − No internal connection
description/ordering information
These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V V operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QFN − RGY
SOIC − D
Reel of 1000
Tube of 50
SN74LV74ARGYR
SN74LV74AD
LV74A
LV74A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV74ADR
SN74LV74ANSR
SN74LV74ADBR
SN74LV74APW
SN74LV74APWR
SN74LV74APWT
SN74LV74ADGVR
SNJ54LV74AJ
SOP − NS
74LV74A
LV74A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV74A
TVSOP − DGV
CDIP − J
LV74A
SNJ54LV74AJ
SNJ54LV74AW
SNJ54LV74AFK
CFP − W
Tube of 150
Tube of 55
SNJ54LV74AW
SNJ54LV74AFK
−55°C to 125°C
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
description/ordering information (continued)
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
L
L
X
H
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram, each flip-flop (positive logic)
PRE
C
CLK
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
Q
C
C
C
CLR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
O
O
CC
Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV74A
SN74LV74A
MIN MAX
UNIT
MIN
2
MAX
V
V
Supply voltage
5.5
2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
CC
CC
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
V
V
V
× 0.3
CC
CC
CC
CC
V
IL
Low-level input voltage
× 0.3
× 0.3
× 0.3
× 0.3
CC
CC
V
V
Input voltage
0
0
5.5
0
0
5.5
V
V
I
Output voltage
V
CC
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−50
μA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
−2
−6
−2
−6
−12
50
2
I
High-level output current
Low-level output current
OH
mA
−12
50
μA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
OL
6
6
mA
12
12
200
100
20
85
200
100
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV74A
SN74LV74A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 μA
= −2 mA
= −6 mA
= −12 mA
= 50 μA
= 2 mA
2 V to 5.5 V
2.3 V
V
CC
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
V
V
V
OH
OL
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
= 6 mA
3 V
= 12 mA
4.5 V
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
μA
μA
μA
I
I
V = V or GND,
I = 0
O
20
20
CC
I
CC
I
off
V or V = 0 to 5.5 V
0
5
5
I
O
3.3 V
2
2
2
2
C
V = V or GND
pF
i
I
CC
5 V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V 0.2 V
(unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV74A
SN74LV74A
A
PARAMETER
UNIT
MIN
8
MAX
MIN
9
MAX
MIN
9
MAX
PRE or CLR low
CLK
t
w
Pulse duration
ns
8
9
9
Data
8
9
9
Setup time before CLK↑
t
t
ns
ns
su
PRE or CLR inactive
7
7
7
Hold time, data after CLK↑
0.5
0.5
0.5
h
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V 0.3 V
(unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV74A
SN74LV74A
A
PARAMETER
UNIT
MIN
6
MAX
MIN
7
MAX
MIN
7
MAX
PRE or CLR low
CLK
t
w
Pulse duration
ns
6
7
7
Data
6
7
7
Setup time before CLK↑
t
t
ns
ns
su
PRE or CLR inactive
5
5
5
Hold time, data after CLK↑
0.5
0.5
0.5
h
timing requirements over recommended operating free-air temperature range, VCC = 5 V 0.5 V
(unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV74A
SN74LV74A
A
PARAMETER
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
PRE or CLR low
CLK
t
w
Pulse duration
ns
5
5
5
Data
5
5
5
Setup time before CLK↑
t
t
ns
ns
su
PRE or CLR inactive
3
3
3
Hold time, data after CLK↑
0.5
0.5
0.5
h
switching characteristics over recommended operating free-air temperature range,
CC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
V
T = 25°C
SN54LV74A
SN74LV74A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
UNIT
MHz
ns
MIN
50*
30
TYP
100*
70
MAX
MIN
40*
25
1*
MAX
MIN
40
25
1
MAX
C = 15 pF
L
f
t
t
max
C = 50 pF
L
PRE or CLR
CLK
9.8* 14.8*
11.1* 16.4*
17*
19*
20
17
19
20
23
C = 15 pF
L
Q or Q
Q or Q
pd
pd
1*
1
PRE or CLR
CLK
13
17.4
20
1
1
C = 50 pF
L
ns
14.2
1
23
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV74A
SN74LV74A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
UNIT
MHz
ns
MIN
80*
50
TYP
140*
90
MAX
MIN
70*
45
MAX
MIN
70
45
1
MAX
C = 15 pF
L
f
t
t
max
C = 50 pF
L
PRE or CLR
CLK
6.9* 12.3*
7.9* 11.9*
1* 14.5*
14.5
14
C = 15 pF
L
Q or Q
Q or Q
pd
pd
1*
1
14*
18
1
PRE or CLR
CLK
9.2
15.8
15.4
1
18
C = 50 pF
L
ns
10.2
1
17.5
1
17.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
T = 25°C
SN54LV74A
SN74LV74A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
PARAMETER
UNIT
MHz
ns
MIN
130*
90
TYP
180*
140
5*
MAX
MIN
110*
75
1*
MAX
MIN
110
75
1
MAX
C = 15 pF
L
f
t
t
max
C = 50 pF
L
PRE or CLR
CLK
7.7*
7.3*
9.7
9*
8.5*
11
9
8.5
C = 15 pF
L
Q or Q
Q or Q
pd
5.6*
6.6
1*
1
PRE or CLR
CLK
1
1
11
C = 50 pF
L
ns
pd
7.2
9.3
1
10.5
1
10.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
SN74LV74A
PARAMETER
UNIT
MIN
TYP
0.1
0
MAX
0.8
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
Quiet output, maximum dynamic V
V
V
V
V
V
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.8
OL
OH
3.2
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
f = 10 MHz
V
TYP
21
UNIT
CC
3.3 V
C
Power dissipation capacitance
C = 50 pF,
pF
pd
L
5 V
23
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
R = 1 kΩ
L
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
Open
PLH PHL
t
C
C
L
/t
V
CC
L
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
V
su
CC
V
CC
50% V
50% V
Input
Input
CC
CC
50% V
50% V
CC
Data Input
0 V
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
CC
CC
CC
CC
0 V
0 V
t
t
t
t
PZL
PLH
PHL
PLZ
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
+ 0.3 V
OL
S1 at V
CC
V
OL
V
OL
(see Note B)
t
PHL
PLH
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PHL
PHZ
dis
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN74LV74AD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74ADBLE
SN74LV74ADBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LV74A
LV74A
LV74A
LV74A
LV74A
LV74A
LV74A
LV74A
LV74A
LV74A
LV74A
74LV74A
74LV74A
LV74A
LV74A
SN74LV74ADBRE4
SN74LV74ADBRG4
SN74LV74ADE4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
DB
DB
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74LV74ADG4
SN74LV74ADGVR
SN74LV74ADGVRE4
SN74LV74ADGVRG4
SN74LV74ADR
SOIC
D
50
Green (RoHS
& no Sb/Br)
TVSOP
TVSOP
TVSOP
SOIC
DGV
DGV
DGV
D
2000
2000
2000
2500
2500
2500
2000
2000
90
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74LV74ADRE4
SN74LV74ADRG4
SN74LV74ANSR
SN74LV74ANSRG4
SN74LV74APW
SOIC
D
Green (RoHS
& no Sb/Br)
SOIC
D
Green (RoHS
& no Sb/Br)
SO
NS
NS
PW
PW
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
SN74LV74APWE4
90
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
SN74LV74APWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV74A
SN74LV74APWLE
SN74LV74APWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LV74A
LV74A
LV74A
LV74A
LV74A
LV74A
LV74A
LV74A
SN74LV74APWRE4
SN74LV74APWRG4
SN74LV74APWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
PW
Green (RoHS
& no Sb/Br)
SN74LV74APWTE4
SN74LV74APWTG4
SN74LV74ARGYR
SN74LV74ARGYRG4
PW
250
Green (RoHS
& no Sb/Br)
PW
250
Green (RoHS
& no Sb/Br)
RGY
RGY
3000
3000
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV74A :
Automotive: SN74LV74A-Q1
•
Enhanced Product: SN74LV74A-EP
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV74ADBR
SN74LV74ADGVR
SN74LV74ADR
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
14
14
14
2000
2000
2500
2000
2000
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
12.4
12.4
12.4
12.4
8.2
6.8
6.5
7.0
6.9
6.9
6.9
3.75
6.6
4.0
9.0
5.6
5.6
5.6
5.6
3.75
2.5
1.6
2.1
1.6
1.6
1.6
1.6
1.15
12.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
12.0
16.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
SN74LV74APWR
SN74LV74APWR
SN74LV74APWRG4
SN74LV74APWT
SN74LV74ARGYR
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
PW
PW
RGY
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV74ADBR
SN74LV74ADGVR
SN74LV74ADR
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
14
14
14
2000
2000
2500
2000
2000
2000
250
367.0
367.0
367.0
364.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
364.0
367.0
367.0
367.0
367.0
38.0
35.0
38.0
27.0
35.0
35.0
35.0
35.0
SN74LV74APWR
SN74LV74APWR
SN74LV74APWRG4
SN74LV74APWT
SN74LV74ARGYR
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
PW
PW
RGY
3000
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
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