SN74LV74APW [TI]
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS; 双上升沿触发D型触发器
| 型号： | SN74LV74APW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS |
| 文件： | 总8页 (文件大小：159K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
SN54LV74A . . . J OR W PACKAGE
SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Typical V (Output Ground Bounce)
OLP
< 0.8 V at V , T = 25°C
CC
A
1CLR
1D
V
CC
2CLR
2D
1
2
3
4
5
6
7
14
13
12
11
Typical V
> 2 V at V , T = 25°C
(Output V
Undershoot)
OHV
CC
OH
1CLK
1PRE
1Q
A
2CLK
Latch-Up Performance Exceeds 250 mA Per
JESD 17
10 2PRE
9
8
1Q
2Q
2Q
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
GND
SN54LV74A . . . FK PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
3
2
1
20 19
18
2D
1CLK
NC
4
5
6
7
8
NC
17
16
description
2CLK
1PRE
NC
15 NC
14
These dual positive-edge-triggered D-type
flip-flops are designed for 2-V to 5.5-V V
operation.
2PRE
1Q
CC
9 10 11 12 13
A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the
levels of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) inputs meeting
the setup-time requirements is transferred to the
outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a voltage level
and is not directly related to the rise time of the
clock pulse. Following the hold-time interval, data
attheDinputcanbechangedwithoutaffectingthe
levels at the outputs.
NC – No internal connection
The SN54LV74A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV74A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is unstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
‡
logic symbol
4
5
6
9
8
S
1PRE
1CLK
1D
1Q
1Q
2Q
2Q
3
C1
2
1
1D
R
1CLR
10
11
12
13
2PRE
2CLK
2D
2CLR
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram, each flip-flop (positive logic)
PRE
C
CLK
C
C
Q
TG
C
C
C
C
D
TG
TG
TG
C
Q
C
C
CLR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LV74A
MIN MAX
SN74LV74A
UNIT
MIN
2
MAX
V
V
Supply voltage
2
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
5.5
V
V
V
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
× 0.3
× 0.3
5.5
V
V
Input voltage
0
0
V
V
I
Output voltage
0
V
0
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–2
–50
–2
–6
–12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
–6
mA
µA
–12
50
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
0
0
0
200
100
20
0
0
0
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
–55
125
–40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV74A
SN74LV74A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= –50 µA
2 V to 5.5 V
2.3 V
3 V
V
–0.1
2
V
CC
–0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= –2 mA
= –6 mA
= –12 mA
= 50 µA
= 2 mA
V
V
V
OH
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
3 V
0.1
0.4
0.44
0.55
±1
0.1
0.4
0.44
0.55
±1
V
OL
= 6 mA
= 12 mA
4.5 V
5.5 V
5.5 V
0 V
I
I
I
V = V
or GND
or GND,
µA
µA
µA
I
I
CC
CC
V = V
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
5
5
I
O
3.3 V
5 V
2.1
2.1
2.1
2.1
C
V = V
I
or GND
pF
i
CC
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V ± 0.2 V
CC
T
= 25°C
SN54LV74A
SN74LV74A
A
PARAMETER
UNIT
MIN
8
MAX
MIN
9
MAX
MIN
9
MAX
PRE or CLR low
CLK
t
w
Pulse duration
ns
8
9
9
Data
8
9
9
t
t
ns
ns
Setup time before CLK↑
su
PRE or CLR inactive
7
7
7
Hold time, data after CLK↑
0.5
0.5
0.5
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V ± 0.3 V
CC
T
= 25°C
SN54LV74A
SN74LV74A
A
PARAMETER
UNIT
MIN
6
MAX
MIN
7
MAX
MIN
7
MAX
PRE or CLR low
CLK
t
w
Pulse duration
ns
6
7
7
Data
6
7
7
t
t
ns
ns
Setup time before CLK↑
su
PRE or CLR inactive
5
5
5
Hold time, data after CLK↑
0.5
0.5
0.5
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
SN54LV74A
SN74LV74A
A
PARAMETER
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
PRE or CLR low
CLK
t
w
Pulse duration
ns
5
5
5
Data
5
5
5
t
t
ns
ns
Setup time before CLK↑
su
PRE or CLR inactive
3
3
3
Hold time, data after CLK↑
0.5
0.5
0.5
h
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
100
70
SN54LV74A
SN74LV74A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
50
MAX
MIN
40
25
1
MAX
MIN
40
25
1
MAX
C
= 15 pF*
= 50 pF
L
f
t
t
max
C
30
L
PRE or CLR
CLK
9.8
14.8
16.4
17.4
20
17
19
20
23
17
19
20
23
*
pd
C
C
= 15 pF
= 50 pF
Q or Q
Q or Q
L
11.1
13
1
1
PRE or CLR
CLK
1
1
ns
pd
L
14.2
1
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
140
90
SN54LV74A
SN74LV74A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
80
MAX
MIN
70
45
1
MAX
MIN
70
45
1
MAX
C
= 15 pF*
= 50 pF
L
f
t
t
max
C
50
L
PRE or CLR
CLK
6.9
12.3
11.9
15.8
15.4
14.5
14
14.5
14
*
pd
C
C
= 15 pF
= 50 pF
Q or Q
Q or Q
L
7.9
1
1
PRE or CLR
CLK
9.2
1
18
1
18
ns
pd
L
10.2
1
17.5
1
17.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
180
140
5
SN54LV74A
SN74LV74A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
130
90
MAX
MIN
110
75
1
MAX
MIN
110
75
1
MAX
C
= 15 pF*
= 50 pF
L
f
t
t
max
C
L
PRE or CLR
CLK
7.7
7.3
9.7
9.3
9
8.5
9
8.5
*
pd
C
C
= 15 pF
= 50 pF
Q or Q
Q or Q
L
5.6
1
1
PRE or CLR
CLK
6.6
1
11
1
11
ns
pd
L
7.2
1
10.5
1
10.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV74A
PARAMETER
UNIT
MIN
TYP
0.1
MAX
0.8
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.04
3.2
–0.8
OL
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
21
UNIT
CC
3.3 V
5 V
C
Power dissipation capacitance
C
pF
pd
23
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74A, SN74LV74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS381D – AUGUST 1997 – REVISED JUNE 1998
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
V
CC
Open Drain
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
t
50% V
CC
CC
CC
t
CC
0 V
0 V
t
PZL
t
t
PLH
PHL
PLZ
Output
Waveform 1
V
OH
≈ V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
CC
V
V
OL
+ 0.3 V
– 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
PHZ
t
PHL
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
V
OH
50% V
50% V
50% V
CC
CC
≈ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
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semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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TI
SN74LV74APWTG4
LV/LV-A/LVX/H SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN, PLASTIC, TSSOP-14
TI
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