SN74LV74AQDRG4Q1 [TI]
汽车类双路上升沿 D 类触发器 | D | 14 | -40 to 125;
| 型号： | SN74LV74AQDRG4Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类双路上升沿 D 类触发器 | D | 14 | -40 to 125 光电二极管 逻辑集成电路 触发器 锁存器 |
| 文件： | 总10页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢂꢃ ꢆꢇ ꢈ ꢉ
ꢊꢋꢆ ꢄ ꢌꢍ ꢀꢎ ꢏ ꢎꢅꢐ ꢇꢐꢊꢑ ꢐꢇꢏ ꢒꢎ ꢑ ꢑꢐ ꢒꢐꢊ ꢊꢇꢏ ꢓꢌ ꢐ ꢔꢄ ꢎꢌ ꢇ ꢔꢄꢍ ꢌ
SCLS556A − DECEMBER 2003 − REVISED MAY 2004
D OR PW PACKAGE
(TOP VIEW)
D
Qualification in Accordance With
AEC-Q100
†
D
Qualified for Automotive Applications
1
2
3
4
5
6
7
14
13
12
11
10
9
1CLR
1D
V
CC
2CLR
2D
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
1CLK
1PRE
1Q
2CLK
2PRE
2Q
D
D
D
2-V to 5.5-V V
Operation
CC
1Q
Max t of 13 ns at 5 V
pd
8
GND
2Q
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
D
D
D
D
D
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Support Mixed-Mode Voltage Operation on
All Ports
I
Supports Partial-Power-Down Mode
off
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
†
Contact factory for details. Q100 qualification data available on
request.
description/ordering informationS
This dual positive-edge-triggered D-type flip-flop is designed for 2-V to 5.5-V V
operation.
CC
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
SOIC − D
Tape and reel SN74LV74AQDRQ1
Tape and reel SN74LV74AQPWRQ1
LV74A
LV74A
−40°C to 125°C
TSSOP − PW
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
ꢌꢚ ꢙ ꢥꢠꢟ ꢝ ꢞ ꢟ ꢙꢗ ꢘꢙ ꢚ ꢛ ꢝ ꢙ ꢞ ꢢꢡ ꢟ ꢖꢘ ꢖꢟꢜ ꢝꢖ ꢙꢗꢞ ꢢꢡ ꢚ ꢝꢧ ꢡ ꢝꢡ ꢚ ꢛꢞ ꢙꢘ ꢏꢡꢨ ꢜꢞ ꢎꢗꢞ ꢝꢚ ꢠꢛ ꢡꢗꢝ ꢞ
ꢞ ꢝ ꢜ ꢗꢥ ꢜ ꢚꢥ ꢩ ꢜ ꢚꢚ ꢜ ꢗ ꢝꢪꢦ ꢌꢚ ꢙ ꢥꢠꢟ ꢝꢖꢙꢗ ꢢꢚ ꢙꢟ ꢡꢞ ꢞꢖ ꢗꢫ ꢥꢙꢡ ꢞ ꢗꢙꢝ ꢗꢡ ꢟꢡ ꢞꢞ ꢜꢚ ꢖꢤ ꢪ ꢖꢗꢟ ꢤꢠꢥ ꢡ
ꢝ ꢡ ꢞ ꢝꢖ ꢗꢫ ꢙꢘ ꢜ ꢤꢤ ꢢꢜ ꢚ ꢜ ꢛ ꢡ ꢝ ꢡ ꢚ ꢞ ꢦ
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢃ ꢆ ꢇꢈꢉ
ꢊ ꢋꢆꢄ ꢌꢍꢀ ꢎ ꢏ ꢎꢅ ꢐꢇ ꢐꢊ ꢑꢐ ꢇꢏꢒ ꢎ ꢑꢑ ꢐꢒꢐ ꢊ ꢊꢇ ꢏꢓ ꢌꢐ ꢔ ꢄꢎ ꢌꢇꢔ ꢄ ꢍ ꢌ
SCLS556A − DECEMBER 2003 − REVISED MAY 2004
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram, each flip-flop (positive logic)
PRE
C
CLK
C
C
Q
TG
C
C
C
C
TG
TG
TG
D
Q
C
C
C
CLR
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCLS556A − DECEMBER 2003 − REVISED MAY 2004
recommended operating conditions (see Note 4)
MIN
2
MAX
UNIT
V
Supply voltage
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
CC
CC
CC
V
High-level input voltage
V
V
× 0.7
× 0.7
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
CC
CC
CC
V
IL
Low-level input voltage
× 0.3
× 0.3
V
V
Input voltage
0
0
5.5
V
V
I
Output voltage
V
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
mA
12
200
100
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−40
125
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
−0.1
2
TYP
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
V
CC
OH
OH
OH
OH
OL
OL
OL
OL
V
V
OH
3 V
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
V
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
I
I
V = V
CC
or GND,
I = 0
O
20
CC
off
I
V or V = 0 to 5.5 V
0
5
I
O
3.3 V
2
2
C
V = V
or GND
pF
i
I
CC
5 V
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢂ ꢃ ꢆ ꢇꢈꢉ
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SCLS556A − DECEMBER 2003 − REVISED MAY 2004
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
A
PARAMETER
MIN
MAX
UNIT
MIN
8
MAX
PRE or CLR low
CLK
9
9
t
w
Pulse duration
ns
8
Data
8
9
Setup time before CLK↑
t
t
ns
ns
su
PRE or CLR inactive
7
7
Hold time, data after CLK↑
0.5
0.5
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
A
PARAMETER
MIN
MAX
UNIT
MIN
6
MAX
PRE or CLR low
CLK
7
7
t
w
Pulse duration
ns
6
Data
6
7
Setup time before CLK↑
t
t
ns
ns
su
PRE or CLR inactive
5
5
Hold time, data after CLK↑
0.5
0.5
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
A
PARAMETER
MIN
MAX
UNIT
MIN
5
MAX
PRE or CLR low
CLK
5
5
t
w
Pulse duration
ns
5
Data
5
5
Setup time before CLK↑
t
t
ns
ns
su
PRE or CLR inactive
3
3
Hold time, data after CLK↑
0.5
0.5
h
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
70
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
MAX
f
t
C
C
= 50 pF
= 50 pF
30
25
1
max
L
L
PRE or CLR
CLK
13
17.4
20
20
23
Q or Q
pd
14.2
1
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
90
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
MAX
f
t
C
C
= 50 pF
= 50 pF
50
45
1
max
L
L
PRE or CLR
CLK
9.2
15.8
15.4
18
18
Q or Q
pd
10.2
1
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢂꢃ ꢆꢇ ꢈ ꢉ
ꢊꢋꢆ ꢄ ꢌꢍ ꢀꢎ ꢏ ꢎꢅꢐ ꢇꢐꢊꢑ ꢐꢇꢏ ꢒꢎ ꢑ ꢑꢐ ꢒꢐꢊ ꢊꢇꢏ ꢓꢌ ꢐ ꢔ ꢄꢎ ꢌ ꢇꢔ ꢄꢍ ꢌ
SCLS556A − DECEMBER 2003 − REVISED MAY 2004
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
140
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN
MAX
UNIT
MHz
ns
MIN
MAX
f
t
C
C
= 50 pF
= 50 pF
90
75
1
max
L
L
PRE or CLR
CLK
6.6
9.7
9.3
12
13
Q or Q
pd
7.2
1
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
PARAMETER
MIN
TYP
0.1
0
MAX
0.8
UNIT
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.8
OL
3.2
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
21
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
23
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS556A − DECEMBER 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
CC
CC
0 V
0 V
t
t
t
t
t
PLZ
PLH
PHL
PZL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
PHL
PLH
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-May-2007
PACKAGING INFORMATION
Orderable Device
SN74LV74AQDRQ1
SN74LV74AQPWRQ1
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
NRND
SOIC
D
14
2500
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1 YEAR/
Level-1-235C-UNLIM
NRND
TSSOP
PW
14
2000
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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