SN74LV74D [TI]
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS; 双上升沿触发D型触发器
| 型号： | SN74LV74D |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS |
| 文件： | 总7页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV74, SN74LV74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996
SN54LV74 . . . J OR W PACKAGE
SN74LV74 . . . D, DP, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
Typical V (Output Ground Bounce)
OLP
< 0.8 V at V , T = 25°C
CC
A
1CLR
1D
V
CC
2CLR
2D
1
2
3
4
5
6
7
14
13
12
11
Typical V
> 2 V at V , T = 25°C
(Output V
Undershoot)
OHV
CC
OH
A
1CLK
1PRE
1Q
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
2CLK
10 2PRE
9
8
1Q
2Q
2Q
GND
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
SN54LV74 . . . FK PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
3
2
1
20 19
18
2D
1CLK
NC
4
5
6
7
8
NC
17
16
description
2CLK
1PRE
NC
15 NC
14
These dual positive-edge-triggered D-type flip-
flops are designed for 2.7-V to 5.5-V V
operation.
2PRE
1Q
CC
9 10 11 12 13
A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs regardless of the
levels of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) inputs meeting
the setup-time requirements is transferred to the
NC – No internal connection
outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed
without affecting the levels at the outputs.
The SN74LV74 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV74 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV74 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74, SN74LV74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
†
logic symbol
4
5
6
9
8
S
1PRE
1CLK
1D
1Q
1Q
2Q
2Q
3
C1
2
1
1D
R
1CLR
10
11
12
13
2PRE
2CLK
2D
2CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for D, DB, J, PW, and W packages.
logic diagram, each flip-flop (positive logic)
PRE
C
TG
C
CLK
C
C
Q
C
TG
C
C
TG
C
C
D
TG
C
Q
CLR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74, SN74LV74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . 1.25 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
A
DB or PW package . . . . . . . . . . . . . 0.5 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
recommended operating conditions (see Note 4)
SN54LV74
SN74LV74
UNIT
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
Supply voltage
5.5
5.5
V
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
High-level input voltage
IH
3.15
3.15
0.8
0.8
V
IL
Low-level input voltage
V
1.65
1.65
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
–6
V
CC
–6
O
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
I
High-level output current
Low-level output current
mA
mA
OH
OL
–12
6
–12
6
I
12
12
100
85
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
100
125
0
ns/V
T
A
–55
–40
°C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74, SN74LV74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV74
TYP
SN74LV74
TYP
†
PARAMETER
TEST CONDITIONS
V
CC
UNIT
MIN
MAX
MIN
MAX
I
I
I
I
I
I
= –100 µA
MIN to MAX
3 V
V
– 0.2
V
– 0.2
OH
OH
OH
OL
OL
OL
CC
2.4
3.6
CC
2.4
3.6
V
V
= –6 mA
= –12 mA
= 100 µA
= 6 mA
V
OH
4.5 V
MIN to MAX
3 V
0.2
0.4
0.55
±1
0.2
0.4
0.55
±1
V
OL
= 12 mA
4.5 V
3.6 V
I
I
V = V
or GND
or GND
µA
I
I
CC
CC
5.5 V
±1
±1
3.6 V
20
20
V = V
I = 0
O
µA
µA
pF
CC
I
5.5 V
20
20
One input at
– 0.6 V
Other inputs at
V or GND
CC
I
3 V to 3.6 V
500
500
CC
V
CC
3.3 V
5 V
2.5
3
2.5
3
C
V = V
or GND
CC
i
I
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV74
V = 5 V
CC
± 0.5 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
60
MIN
0
MAX
f
t
Clock frequency
70
50
ns
ns
clock
PRE or CLR low
CLK high or low
Data
15
15
6
20
20
8
25
25
12
8
Pulse duration, LE high
w
t
t
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
PRE or CLR inactive
5
6
3
3
3
h
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN74LV74
V = 5 V
CC
± 0.5 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
70
60
50
ns
ns
clock
PRE or CLR low
CLK high or low
Data
15
15
6
20
20
8
25
25
12
8
Pulse duration, LE high
w
t
t
ns
ns
Setup time, data before CLK↑
Hold time, data after CLK↑
su
PRE or CLR inactive
5
6
3
3
3
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74, SN74LV74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LV74
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
= 5 V ± 0.5 V
V
= 3.3 V ± 0.3 V
CC
MIN TYP MAX
V
CC
= 2.7 V
MAX
UNIT
CC
MIN TYP MAX
MIN
f
t
70
100
11
60
90
18
17
50
MHz
ns
max
PRE or CLR
CLK
19
17
27
26
34
28
Q or Q
pd
10
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN74LV74
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
= 5 V ± 0.5 V
V
= 3.3 V ± 0.3 V
CC
MIN TYP MAX
V
CC
= 2.7 V
MAX
UNIT
CC
MIN TYP MAX
MIN
f
t
70
100
11
60
90
18
17
50
MHz
ns
max
PRE or CLR
CLK
19
17
27
26
34
28
Q or Q
pd
10
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
32
UNIT
CC
3.3 V
C
Power dissipation capacitance per flip-flop
C
pF
pd
5 V
68
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV74, SN74LV74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
SCLS189C – FEBRUARY 1993 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
V
z
TEST
S1
S1
Open
1 kΩ
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
t
V
z
GND
GND
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
1 kΩ
(see Note A)
WAVEFORM
CONDITION
V
= 4.5 V
V
= 2.7 V
CC
to 5.5 V
CC
to 3.6 V
1.5 V
2.7 V
6 V
V
m
0.5 × V
CC
V
i
V
z
V
CC
LOAD CIRCUIT
2 × V
CC
V
i
V
m
Timing Input
0 V
t
w
t
t
su
h
V
i
V
i
V
m
V
m
Input
V
m
V
m
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
i
i
Output
Control
V
V
m
m
Input
V
m
V
m
0 V
0 V
V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
0.5 × V
z
OH
V
V
V
m
V
m
m
Output
Output
V
+ 0.3 V
– 0.3 V
S1 at V
(see Note B)
OL
z
V
OL
V
OL
t
PHZ
t
PLH
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
V
V
m
m
m
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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