SN74LV74APWT [TI]
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS; 双上升沿触发D型触发器
| 型号： | SN74LV74APWT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS |
| 文件： | 总16页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS381L − AUGUST 1997 − REVISED APRIL 2005
D
D
D
D
D
2-V to 5.5-V V
Operation
D
D
D
I
Supports Partial-Power-Down Mode
CC
off
Operation
Max t of 8.5 ns at 5 V
pd
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Support Mixed-Mode Voltage Operation on
All Ports
− 1000-V Charged-Device Model (C101)
SN54LV74A . . . FK PACKAGE
SN54LV74A . . . J OR W PACKAGE
SN74LV74A . . . D, DB, DGV, NS,
OR PW PACKAGE
SN74LV74A . . . RGY PACKAGE
(TOP VIEW)
(TOP VIEW)
(TOP VIEW)
1CLR
1D
V
CC
2CLR
2D
1
2
3
4
5
6
7
14
13
12
11
1
14
3
2
1
20 19
18
2D
1CLK
NC
4
5
6
7
8
1D
1CLK
1PRE
1Q
13 2CLR
12 2D
2
3
4
5
6
1CLK
1PRE
1Q
NC
17
16
2CLK
2CLK
1PRE
NC
11
10
9
2CLK
2PRE
2Q
10 2PRE
15 NC
14
9 10 11 12 13
9
8
1Q
2Q
2Q
2PRE
1Q
1Q
GND
7
8
NC − No internal connection
description/ordering information
These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V V
operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − D
Reel of 1000
Tube of 50
SN74LV74ARGYR
SN74LV74AD
LV74A
LV74A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV74ADR
SN74LV74ANSR
SN74LV74ADBR
SN74LV74APW
SN74LV74APWR
SN74LV74APWT
SN74LV74ADGVR
SNJ54LV74AJ
SOP − NS
74LV74A
LV74A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV74A
TVSOP − DGV
CDIP − J
LV74A
SNJ54LV74AJ
CFP − W
Tube of 150
Tube of 55
SNJ54LV74AW
SNJ54LV74AFK
SNJ54LV74AW
SNJ54LV74AFK
−55°C to 125°C
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢊ ꢁ ꢄꢏꢀꢀ ꢌ ꢎꢕ ꢏꢒꢖ ꢍꢀ ꢏ ꢁ ꢌꢎꢏꢉ ꢗꢘ ꢙꢚ ꢛꢜꢝ ꢞꢟꢠ ꢡꢗ ꢝꢜ ꢡꢗꢢ ꢙꢡꢚ ꢋꢒ ꢌ ꢉ ꢊ ꢣꢎ ꢍꢌ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢃ ꢇ ꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢆ ꢃꢇ
ꢉ ꢊꢇꢄ ꢋꢌꢀ ꢍ ꢎ ꢍꢅ ꢏꢐ ꢏꢉ ꢑꢏ ꢐꢎꢒ ꢍ ꢑꢑ ꢏꢒꢏ ꢉ ꢉꢐ ꢎꢓ ꢋꢏ ꢔ ꢄꢍ ꢋꢐꢔ ꢄ ꢌ ꢋꢀ
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
description/ordering information (continued)
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
PRE
L
CLR
CLK
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
X
H
†
†
H
L
L
X
H
H
H
H
H
↑
H
L
L
H
↑
H
H
L
X
Q
Q
0
0
†
This configuration is nonstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic diagram, each flip-flop (positive logic)
PRE
C
CLK
C
C
Q
TG
C
C
C
C
TG
TG
TG
D
Q
C
C
C
CLR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢃ ꢇꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢆꢃ ꢇ
ꢉꢊꢇ ꢄ ꢋꢌ ꢀꢍ ꢎ ꢍꢅꢏ ꢐꢏꢉꢑ ꢏꢐꢎ ꢒꢍ ꢑ ꢑꢏ ꢒꢏꢉ ꢉꢐꢎ ꢓꢋ ꢏ ꢔ ꢄ ꢍꢋ ꢐ ꢔꢄꢌ ꢋ ꢀ
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢃ ꢇ ꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢆ ꢃꢇ
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ꢑꢑ
ꢏꢒ
ꢏ
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ꢉ
ꢐ
ꢎꢓ
ꢋ
ꢏ
ꢔ
ꢄꢍ
ꢋ
ꢐ
ꢔ
ꢄ
ꢌ
ꢋ
ꢀ
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV74A
MIN MAX
SN74LV74A
MIN MAX
UNIT
V
V
Supply voltage
2
5.5
2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
CC
V
CC
V
CC
× 0.7
× 0.7
× 0.7
V
CC
V
CC
V
CC
× 0.7
× 0.7
× 0.7
High-level input voltage
V
V
IH
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
V
V
V
× 0.3
× 0.3
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
Input voltage
0
0
5.5
0
0
5.5
V
V
I
Output voltage
V
V
O
CC
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV74A
SN74LV74A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
V
CC
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
I
I
V = V
CC
or GND,
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
3.3 V
2
2
2
2
C
V = V
or GND
pF
i
I
CC
5 V
ꢋ
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ꢞ
ꢛ ꢠ ꢚ ꢙ ꢭ ꢡ ꢦꢘ ꢢ ꢚ ꢠ ꢜꢤ ꢛꢠ ꢮ ꢠ ꢨ ꢜꢦ ꢟꢠ ꢡ ꢗꢩ ꢣ ꢘꢢ ꢥꢢ ꢝꢗ ꢠꢥ ꢙꢚ ꢗꢙ ꢝ ꢛꢢ ꢗꢢ ꢢꢡ ꢛ ꢜꢗ ꢘꢠꢥ
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ꢝ ꢘ ꢢ ꢡ ꢭꢠ ꢜꢥ ꢛꢙ ꢚ ꢝ ꢜꢡ ꢗꢙ ꢡꢞ ꢠ ꢗ ꢘꢠ ꢚ ꢠ ꢦꢥ ꢜ ꢛꢞꢝ ꢗꢚ ꢫ ꢙꢗꢘ ꢜꢞꢗ ꢡꢜꢗ ꢙꢝꢠ ꢩ
ꢗ
ꢚ
ꢥ
ꢠ
ꢚ
ꢠ
ꢥ
ꢮ
ꢠ
ꢚ
ꢗ
ꢘ
ꢠ
ꢥ
ꢙ
ꢭ
ꢘ
ꢗ
ꢗ
ꢜ
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢃ ꢇꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢆꢃ ꢇ
ꢉꢊꢇ ꢄ ꢋꢌ ꢀꢍ ꢎ ꢍꢅꢏ ꢐꢏꢉꢑ ꢏꢐꢎ ꢒꢍ ꢑ ꢑꢏ ꢒꢏꢉ ꢉꢐꢎ ꢓꢋ ꢏ ꢔ ꢄ ꢍꢋ ꢐ ꢔꢄꢌ ꢋ ꢀ
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV74A
SN74LV74A
A
PARAMETER
UNIT
MIN
8
MAX
MIN
9
MAX
MIN
9
MAX
PRE or CLR low
CLK
t
w
Pulse duration
ns
8
9
9
Data
8
9
9
Setup time before CLK↑
t
t
ns
ns
su
PRE or CLR inactive
7
7
7
Hold time, data after CLK↑
0.5
0.5
0.5
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV74A
SN74LV74A
A
PARAMETER
UNIT
MIN
6
MAX
MIN
7
MAX
MIN
7
MAX
PRE or CLR low
CLK
t
w
Pulse duration
ns
6
7
7
Data
6
7
7
Setup time before CLK↑
t
t
ns
ns
su
PRE or CLR inactive
5
5
5
Hold time, data after CLK↑
0.5
0.5
0.5
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV74A
SN74LV74A
A
PARAMETER
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
PRE or CLR low
CLK
t
w
Pulse duration
ns
5
5
5
Data
5
5
5
Setup time before CLK↑
t
t
ns
ns
su
PRE or CLR inactive
3
3
3
Hold time, data after CLK↑
0.5
0.5
0.5
h
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
100*
70
SN54LV74A
SN74LV74A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
50*
30
MAX
MIN
40*
25
1*
MAX
MIN
40
25
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
t
t
max
PRE or CLR
CLK
9.8* 14.8*
11.1* 16.4*
17*
19*
20
17
19
20
23
C
C
= 15 pF
= 50 pF
Q or Q
Q or Q
pd
L
L
1*
1
PRE or CLR
CLK
13
17.4
20
1
1
ns
pd
14.2
1
23
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢋ
ꢒ
ꢌ
ꢉ
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ꢋ
ꢒ
ꢏ
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ꢍ
ꢏ
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ꢙ
ꢡ
ꢤ
ꢜ
ꢥ
ꢟ
ꢢ
ꢗ
ꢙ
ꢜ
ꢡ
ꢝ
ꢜ
ꢡ
ꢝ
ꢠ
ꢥ
ꢡ
ꢚ
ꢦ
ꢥ
ꢜ
ꢛ
ꢞ
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ꢜ
ꢥ
ꢚ
ꢦ
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ꢝ
ꢙ
ꢤ
ꢙ
ꢝ
ꢢ
ꢗ
ꢙ
ꢜ
ꢡ
ꢚ
ꢢ
ꢥ
ꢠ
ꢛ
ꢠ
ꢚ
ꢙ
ꢭ
ꢡ
ꢭ
ꢜ
ꢢ
ꢨ
ꢚ
ꢩ
ꢎ
ꢠ
ꢪ
ꢢ
ꢚ
ꢍ
ꢡ
ꢚ
ꢗ
ꢥ
ꢞ
ꢟ
ꢠ
ꢡ
ꢝ ꢘꢢ ꢡ ꢭꢠ ꢜꢥ ꢛꢙ ꢚ ꢝ ꢜꢡ ꢗꢙ ꢡꢞꢠ ꢗ ꢘꢠ ꢚ ꢠ ꢦꢥ ꢜꢛ ꢞꢝꢗ ꢚ ꢫ ꢙꢗꢘ ꢜꢞꢗ ꢡꢜꢗ ꢙꢝꢠ ꢩ
ꢗ
ꢚ
ꢥ
ꢠ
ꢚ
ꢠ
ꢥ
ꢮ
ꢠ
ꢚ
ꢗ
ꢘ
ꢠ
ꢥ
ꢙ
ꢭ
ꢘ
ꢗ
ꢗ
ꢜ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢃ ꢇ ꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢆ ꢃꢇ
ꢉ ꢊꢇꢄ ꢋꢌꢀ ꢍ ꢎ ꢍꢅ ꢏꢐ ꢏꢉ ꢑꢏ ꢐꢎꢒ ꢍ ꢑꢑ ꢏꢒꢏ ꢉ ꢉꢐ ꢎꢓ ꢋꢏ ꢔ ꢄꢍ ꢋꢐꢔ ꢄ ꢌ ꢋꢀ
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
140*
90
SN54LV74A
SN74LV74A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
80*
50
MAX
MIN
70*
45
MAX
MIN
70
45
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
t
t
max
PRE or CLR
CLK
6.9* 12.3*
7.9* 11.9*
1* 14.5*
14.5
14
C
C
= 15 pF
= 50 pF
Q or Q
Q or Q
pd
L
L
1*
1
14*
18
1
PRE or CLR
CLK
9.2
15.8
15.4
1
18
ns
pd
10.2
1
17.5
1
17.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
180*
140
5*
SN54LV74A
SN74LV74A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
130*
90
MAX
MIN
110*
75
1*
MAX
MIN
110
75
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
t
t
max
PRE or CLR
CLK
7.7*
7.3*
9.7
9*
8.5*
11
9
8.5
C
C
= 15 pF
= 50 pF
Q or Q
Q or Q
pd
L
L
5.6*
6.6
1*
1
PRE or CLR
CLK
1
1
11
ns
pd
7.2
9.3
1
10.5
1
10.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 6)
CC
L
A
SN74LV74A
PARAMETER
UNIT
MIN
TYP
0.1
0
MAX
0.8
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.8
OL
3.2
OH
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
21
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
23
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁꢂ ꢃ ꢄꢅꢆ ꢃ ꢇꢈ ꢀꢁ ꢆꢃ ꢄꢅ ꢆꢃ ꢇ
ꢉꢊꢇ ꢄ ꢋꢌ ꢀꢍ ꢎ ꢍꢅꢏ ꢐꢏꢉꢑ ꢏꢐꢎ ꢒꢍ ꢑ ꢑꢏ ꢒꢏꢉ ꢉꢐꢎ ꢓꢋ ꢏ ꢔ ꢄ ꢍꢋ ꢐ ꢔꢄꢌ ꢋ ꢀ
SCLS381L − AUGUST 1997 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
CC
CC
0 V
0 V
t
t
t
t
t
PLZ
PLH
PHL
PZL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
PHL
PLH
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74LV74AD
ACTIVE
SOIC
D
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV74ADBLE
SN74LV74ADBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV74ADBRE4
SN74LV74ADE4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
DB
D
14
14
14
14
14
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV74ADGVR
SN74LV74ADGVRE4
SN74LV74ADR
TVSOP
TVSOP
SOIC
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV74ADRE4
SN74LV74ANSR
SN74LV74ANSRG4
SN74LV74APW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV74APWE4
SN74LV74APWG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV74APWLE
SN74LV74APWR
OBSOLETE TSSOP
PW
PW
14
14
TBD
Call TI
Call TI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV74APWRE4
SN74LV74APWRG4
SN74LV74APWT
PW
PW
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV74APWTE4
SN74LV74ARGYR
SN74LV74ARGYRG4
PW
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
RGY
RGY
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated
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