SM72442MTX/NOPB [TI]

Programmable Maximum Power Point Tracking Controller for Photovoltaic Solar Panels;


型号：	SM72442MTX/NOPB
厂家：	TEXAS INSTRUMENTS
描述：	Programmable Maximum Power Point Tracking Controller for Photovoltaic Solar Panels 光电二极管
文件：	总21页 (文件大小：753K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SM72442

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Programmable Maximum Power Point Tracking Controller for Photovoltaic Solar Panels

Check for Samples: SM72442

FEATURES

DESCRIPTION

The SM72442 is a programmable MPPT controller

capable of controlling four PWM gate drive signals for

a 4-switch buck-boost converter. The SM72442 also

features a proprietary algorithm called Panel Mode

which allows for the panel to be connected directly to

the output of your power optimizer circuit. Along with

the SM72295 (Photovoltaic Full Bridge Driver), it

creates a solution for an MPPT configured DC-DC

converter with efficiencies up to 99.5%. Integrated

into the chip is an 8-channel, 12 bit A/D converter

used to sense input and output voltages and currents,

as well as board configuration. Externally

programmable values include maximum output

voltage and current as well as different settings

forslew rate, soft-start and Panel Mode.

•

Renewable Energy Grade

•

Programmable Maximum Power Point Tracking

Photovoltaic Solar Panel Voltage and Current

Diagnostic

•

Single Inductor Four Switch Buck-Boost

Converter Control

•

I2C Interface for Communication

VOUT Overvoltage Protection

Over-Current Protection

Package: TSSOP-28

Block Diagram

VDDA

VDDD

HIB

LIB

Vin

Iin

AVIN

AIIN

AIN0

AIN1

MPPT CONTROLLER

HIA

LIA

CS_N

SCLK

AVOUT

AIOUT

AIN2

AIN3

DIN

ADC_C

ADC

CONTROLLER

CLK GEN

ADC

DOUT

AIN4

AIN5

Vout

Iout

SCL

SDA

AIN6

AIN7

I2C

I2C0

I2C1

I2C2

VSSD

VSSA

Figure 1. Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

SM72442

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Vout(+)

PV(+)

PM DRIVER

Rsen_in

Gate 2

Gate 1

Gate 4

Current Sensing Amplifier

Vout(-)

Rsen_out

Gate 3

0.01 mF

2.2 mF

0.01 mF

2.2 mF

49.9W

0.01 mF

PV(-)

VDDA

AVIN

VDDD

AIIN

Current Sensing Amplifier

Current sensing Amplifier

RT1

RT2

RT3

RT4

NC3

NC1

AIOUT

PWM4

PWM3

PWM2

PWM1

Gate 4

Gate 3

Gate 2

Gate 1

HIB

LIB

HIA

H-Bridge

Driver

0.1 mF

RB2

0.1 mF

RB3

0.1 mF

RB4

LIA

SM72442

10k

NC2

SCL

SDA

I2C0

RB1

60.4k

NC4

RST

10k

CONFIGURATION RESISTOR

PM DRIVER

I2C1

I2C2

RFB1

AVOUT

VSSD

PM_OUT

VSSA

RFB2

Figure 2. Typical Application Circuit

Connection Diagram

Top View

RST

LIA

NC1

VDDD

VSSD

NC2

HIA

HIB

LIB

I2C0

NC4

I2C2

AIOUT

I2C1

SM72442

SCL

SDA

NC3

AIIN

PM_OUT

VDDA

VSSA

AVOUT

AVIN

Figure 3. TSSOP-28 Package

See Package Number PW0028A

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PIN DESCRIPTIONS

Name

RST

Description

Active low signal. External reset input signal to the digital circuit.

Reserved for test only. This pin should be grounded.

NC1

VDDD

Digital supply voltage. This pin should be connected to a 5V supply, and bypassed to VSSD with a 0.1 µF monolithic

ceramic capacitor.

VSSD

NC2

I2C0

I2C1

SCL

SDA

NC3

Digital ground. The ground return for the digital supply and signals.

No Connect. This pin should be pulled up to the 5V supply using 10k resistor.

Addressing for I2C communication.

I2C clock.

I2C data.

Reserved for test only. This pin should be grounded.

PM_OUT When Panel Mode is active, this pin will output a 400 kHz square wave signal with amplitude of 5V. Otherwise, it stays

low.

VDDA

Analog supply voltage. This voltage is also used as the reference voltage. This pin should be connected to a 5V

supply, and bypassed to VSSA with a 1 µF and 0.1 µF monolithic ceramic capacitor.

VSSA

Analog ground. The ground return for the analog supply and signals.

A/D Input Channel 0. Connect a resistor divider to 5V supply to set the maximum output voltage. Please refer to the

application section for more information on setting the resistor value.

AVIN

Input voltage sensing pin.

A/D Input Channel 2. Connect a resistor divider to a 5V supply to set the condition to enter and exit Panel Mode (PM).

Refer to configurable modes for SM72442 in the application section.

AVOUT Output voltage sensing pin.

A/D Input Channel 4. Connect a resistor divider to a 5V supply to set the maximum output current. Please refer to the

application section for more information on setting the resistor value.

AIIN

Input current sensing pin.

A/D Input Channel 6. Connect a resistor divider to a 5V supply to set the output voltage slew rate and various PM

configurations. Refer to configurable modes for SM72442 in the application section.

AIOUT

I2C2

NC4

LIB

Output current sensing pin.

Addressing for I2C communication.

No Connect. This pin should be connected with 60.4k pull-up resistor to 5V.

Low side boost PWM output.

HIB

High side boost PWM output.

HIA

High side buck PWM output.

LIA

Low side buck PWM output.

Panel Mode Pin. Active low. Pulling this pin low will force the chip into Panel Mode.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

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(1)

Absolute Maximum Ratings

Analog Supply Voltage V_A(VDDA - VSSA)

Digital Supply Voltage V_D(VDDD - VSSD)

Voltage on Any Pin to GND

Input Current at Any Pin⁽²⁾

-0.3 to 6.0V

-0.3 to V_A+0.3V max 6.0V

-0.3 to V_A+0.3V

±10 mA

Package Input Current⁽²⁾

±20 mA

Storage Temperature Range

ESD Rating⁽³⁾

-65°C to +150°C

2 kV

Human Body Model

(1) Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under

which operation of the device is ensured. Operating Ratings do not imply ensured performance limits. For ensured performance limits

and associated test conditions, see the Electrical Characteristics tables.

(2) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Recommended Operating Conditions

Operating Temperature

-40°C to 105°C

+4.75V to +5.25V

+4.75V to V_A

0 to V_A

V_ASupply Voltage

V_DSupply Voltage

Digital Input Voltage

Analog Input Voltage

Junction Temperature

0 to V_A

-40°C to 125°C

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Electrical Characteristics

Specifications in standard typeface are for T_J= 25°C, and those in boldface type apply over the full operating junction

temperature range⁽¹⁾

Parameter

Test Conditions

Min

Typ

Max

Units

ANALOG INPUT CHARACTERISTICS

AVin, AIin

Input Range

AVout, AIout

0 to V_A

I_DCL

DC Leakage Current

Input Capacitance⁽²⁾

±1

µA

Track Mode

C_INA

Hold Mode

DIGITAL INPUT CHARACTERISTICS

V_IL

Input Low Voltage

Input High Voltage

Digital Input Capacitance⁽²⁾

Input Current

2.8

0.8

V_IH

C_IND

I_IN

µA

±0.01

±1

DIGITAL OUTPUT CHARACTERISTICS

V_OH

Output High Voltage

Output Low Voltage

I_SOURCE= 200 µA V_A= V_D= 5V

V_D- 0.5

V_OL

I_SINK= 200 µA to 1.0 mA V_A= V_D= 5V

0.4

±1

I_OZH, I_OZL

C_OUT

Hi-Impedance Output Leakage Current V_A= V_D= 5V

Hi-Impedance Output Capacitance⁽²⁾

µA

POWER SUPPLY CHARACTERISTICS (C_L= 10 pF)

V_A,V_D

I_A+ I_D

P_C

Analog and Digital Supply Voltages

Total Supply Current

_A≥ V_D

4.75

5.25

V_A= V_D= 4.75V to 5.25V

11.5

57.5

Power Consumption

78.75

(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) Not tested. Ensured by design.

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Electrical Characteristics (continued)

Specifications in standard typeface are for T_J= 25°C, and those in boldface type apply over the full operating junction

temperature range⁽¹⁾

Parameter

Test Conditions

Min

Typ

Max

Units

PWM OUTPUT CHARACTERISTICS

f_PWM

PWM switching frequency

220

kHz

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Operation Description

OVERVIEW

The SM72442 is a programmable MPPT controller capable of outputting four PWM gate drive signals for a 4-

switch buck-boost converter with an independent Panel Mode. The typical application circuit is shown in Figure 2.

The SM72442 uses an advanced digital controller to generate its PWM signals. A maximum power point tracking

(MPPT) algorithm monitors the input current and voltage and controls the PWM duty cycle to maximize energy

harvested from the photovoltaic module. MPPT performance is very fast. Convergence to the maximum power

point of the module typically occurs within 0.01s. This enables the controller to maintain optimum performance

under fast-changing irradiance conditions.

Transitions between buck, boost, and Panel Mode are smoothed and advanced digital PWM dithering techniques

are employed to increase effective PWM resolution. Output voltage and current limiting functionality are

integrated into the digital control logic. The controller is capable of handling both shorted and no-load conditions

and will recover smoothly from both conditions.

RST pin is pulled low

° RST pin is pulled low

RESET

SOFT-START

Iout < Iout_th

° Iout >= Iout_th

Iout < Iout_th

PM_STARTUP

Iout > Iout_th

AND

Starting time

elapsed

PM pin is pulled low

In Buck-Boost mode for x seconds where x can be set on

ADC Ch 2

MPPT

Every 60 seconds after going into Panel Mode,

MPPT mode will be entered for a maximum of 4

seconds time to check whether or not the converter

is operating at maximum power point

There is an x% change in power from the power

when panel mode was engaged. This percentage

can be set on ADC Ch 2

Figure 4. High Level State Diagram for Startup

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STARTUP

SM72442 has a soft start feature that will ramp its output voltage for a fixed time of 250ms.

If no output current is detected during soft-start time, the chip will then be in Panel Mode for 60 seconds. A

counter will start once the minimum output current threshold is met (set by ADC input channel 4). During these

60 seconds, any variation on the output power will not cause the chip to enter MPPT mode. Once 60 seconds

have elapsed, at a certain power level variation at the output (set by ADC input channel 2) will engage the chip in

MPPT mode.

If the output current exceeded the current threshold set at A/D Channel 6 (A6) during soft-start, the chip will then

engage in MPPT mode.

Figure 5. Startup Sequence

MAXIMUM OUTPUT VOLTAGE

Maximum output voltage on the SM72442 is set by resistor divider ratio on pin A0. (Please refer to Figure 2

Typical Application Circuit).

(RFB1 + RFB2)

RFB2

RB1

V_{OUT_MAX}= 5 x

RT1 + RB1

where

•

RT1 and RB1 are the resistor divider on the ADC pin A0

RFB1 and RFB2 are the output voltage sense resistors. A typical value for RFB2 is about 2 kΩ

(1)

CURRENT LIMIT SETTING

Maximum output current can be set by changing the resistor divider on A4 (pin 18). Refer to Figure 2.

Overcurrent at the output is detected when the voltage on AIOUT (pin 21) equals the voltage on A4 (pin 18). The

voltage on A4 can be set by a resistor divider connected to 5V whereas the voltage on AIOUT can be set by a

current sense amplifier.

AVIN PIN

AVIN is an A/D input to sense the input voltage of the SM72442. A resistor divider can be used to scale max

voltage to about 4V, which is 80% of the full scale of the A/D input.

CONFIGURABLE SETTINGS

A/D pins A0, A2, A4, and A6 are used to configure the behavior of the SM72442 by adjusting the voltage applied

to them. One way to do this is through resistor dividers as shown in Figure 2, where RT1 to RT4 should be in the

range of 20 kΩ.

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Different conditions to enter and exit Panel Mode can be set on the ADC input channel 2. Listed below are

different conditions that a user can select on pin A2. “1:1” refers to the state in which the DC/DC converter

operates with its output voltage equal to its input voltage (also referred to as “Buck-Boost” mode in Figure 4.)

Entering Panel Mode

2s in 1:1 Mode

Exiting Panel Mode

3.1% power variation

1.6% power variation

4.69 V

4.06 V

3.44 V

2.81 V

2.19 V

1.56 V

0.94 V

0.31 V

1s in 1:1 Mode

0.4s in 1:1 Mode

0.2s in 1:1 Mode

2s in 1:1 Mode

1s in 1:1 Mode

0.4s in 1:1 Mode

0.2s in 1:1 Mode

The user can also select the output voltage slew rate, minimum current threshold and duration of Panel Mode

after the soft-start period has finished, by changing the voltage level on pin A6 which is the input of ADC channel

Output Voltage

Slew Rate Limit

Starting Panel Mode

Time

MPPT Exit

Threshold

MPPT Start

Threshold

Starting boost ratio

4.69 V

4.06 V

3.44 V

2.81 V

2.19 V

1.56 V

0.94 V

0.31 V

Slow

Not applicable

0 mA

1:1

60s

75mA

125mA

500mA

Slow

120s

300mA

1:1

Slow

1:1

Slow

Not applicable

60s

1:1.2

1:1

Slow

Fast

60s

1:1

No slew rate limit

60s

1:1

PARAMETER DEFINITIONS

Output Voltage Slew Rate Limit Settling Time: Time constant of the internal filter used to limit output voltage

change. For fast slew rate, every 1V increase, the output voltage will be held for 30 ms whereas in a slow slew

rate, the output voltage will be held for 62 ms for every 1V increase. (See Figure 6).

Starting PM Time: After initial power-up or reset, the output soft-starts and then enters Panel Mode for this

amount of time.

MPPT Exit Threshold and MPPT Start Threshold: These are the hysteretic thresholds for Iout_th.

Starting Boost Ratio – This is the end-point of the soft-start voltage ramp. 1:1 ratio means it stops when Vout =

Vin, 1:1.2 means it stops when Vout = 1.2 x Vin.

PANEL MODE PIN (PM) PIN

The SM72442 can be forced into Panel Mode by pulling the PM pin low. One sample application is to connect

this pin to the output of an external temperature sensor; therefore whenever an over-temperature condition is

detected the chip will enter a Panel Mode.

Once Panel Mode is enabled either when buck-boost mode is entered for a certain period of time (adjustable on

channel 2 of ADC) or when PM is pulled low, the PM_OUT pin will output a 400 kHz square wave signal. Using a

gate driver and transformer, this square wave signal can then be used to drive a Panel Mode FET as shown in

Figure 7.

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Fast

40V

30V

No Slew

Slow

DV = 10V

20 œ 40 ms

(Frequency

dependent)

600 ms

1200 ms

Figure 6. Slew Rate Limitation Circuit

VOUT

(+)

OUT

OUT_

0.47 mF

400 kHz

Square

Wave

499

10k

SM72442

SM72482

150

10k

PM_O

IN_

499 0.47 mF

Pulse

High

2.0

Figure 7. Sample Application for Panel Mode Operation

RESET PIN

When the reset pin is pulled low, the chip will cease its normal operation and turn-off all of its PWM outputs

including the output of PM_OUT pin. Below is an oscilloscope capture of a forced reset condition.

Figure 8. Forced Reset Condition

As seen in Figure 8, the initial value for output voltage and load current are 28V and 1A respectively. After the

reset pin is grounded both the output voltage and load current decreases immediately. MOSFET switching on the

buck-boost converter also stops immediately. VLOB indicates the low side boost output from the SM72295.

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ANALOG INPUT

An equivalent circuit for one of the ADC input channels is shown in Figure 9. Diode D1 and D2 provide ESD

protection for the analog inputs. The operating range for the analog inputs is 0V to V_A. Going beyond this range

will cause the ESD diodes to conduct and result in erratic operation.

The capacitor C1 in Figure 9 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1

is the on resistance of the multiplexer and track / hold switch; it is typically 500Ω. Capacitor C2 is the ADC

sampling capacitor; it is typically 30 pF. The ADC will deliver best performance when driven by a low-impedance

source (less than 100Ω). This is specially important when sampling dynamic signals. Also important when

sampling dynamic signals is a band-pass or low-pass filter which reduces harmonic and noise in the input. These

filters are often referred to as anti-aliasing filters.

30 pF

3 pF

Conversion Phase: Switch Open

Track Phase: Switch Close

Figure 9. Equivalent Input Circuit

DIGITAL INPUTS and OUTPUTS

The digital input signals have an operating range of 0V to V_A, where V_A= VDDA – VSSA. They are not prone to

latch-up and may be asserted before the digital supply V_D, where V_D= VDDD – VSSD, without any risk. The

digital output signals operating range is controlled by V_D. The output high voltage is V_D– 0.5V (min) while the

output low voltage is 0.4V (max).

SDA and SCL OPEN DRAIN OUTPUT

SCL and SDA output is an open-drain output and does not have internal pull-ups. A “high” level will not be

observed on this pin until pull-up current is provided by some external source, typically a pull-up resistor. Choice

of resistor value depends on many system factors; load capacitance, trace length, etc. A typical value of pull- up

resistor for SM72442 ranges from 2 kΩ to 10 kΩ. For more information, refer to the I2C Bus specification for

selecting the pull-up resistor value . The SCL and SDA outputs can operate while being pulled up to 5V and

3.3V.

I2C CONFIGURATION REGISTERS

The operation of the SM72442 can be configured through its I2C interface. Complete register settings for I2C

lines are shown below.

Table 1. reg0 Register Description

Bits

55:40

39:30

Field

RSVD

ADC6

Reset Value

16'h0

R/W

Bit Field Description

Reserved for future use.

10'h0

Analog Channel 6 (slew rate detection time constant,

see adc config worksheet)

29:20

19:10

9:0

ADC4

ADC2

ADC0

10'h0

Analog Channel 4 (iout_max: maximum allowed output

current)

Analog Channel 2 (operating mode, see adc_config

worksheet)

Analog Channel 0 (vout_max: maximum allowed output

voltage)

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Table 2. reg1 Register Description

Bits

55:41

Field

RSVD

mppt_ok

Vout

Reset Value

R/W

Bit Field Description

15'h0

1'h0

Reserved for future use.

Internal mppt_start signal (test only)

Voltage out

39:30

29:20

19:10

9:0

10'h0

Iout

Current out

Vin

Voltage in

Iin

Current in

Table 3. reg3 Register Description

Bits

55:47

Field

RSVD

Reset Value

R/W

Bit Field Description

9'd0

1'b0

Reserved

overide_adcprog

When set to 1'b1,the below overide registers used

instead of ADC

44:43

RSVD

1'b0

2'b01

1'b0

R/W

Reserved

power_thr_sel

is set ( 1/2^^5 or 1/2^^6 )

41:40

39:30

29:20

bb_in_ptmode_se

2'd0

R/W

reg3[46] is set ( 5%,10%,25% or 50%)

iout_max

10'd1023

maximum current threshold instead of ADC ch4

vout_max

maximum voltage threshold instead of ADC ch0

19:17

16:14

13:5

tdoff

tdon

3'h3

R/W

Dead time Off Time

Dead time On time

dc_open

9'hFF

1'b0

Open loop duty cycle (test only)

pass_through_sel

Overrides PM pin 28 and use reg3[3]

Control Panel Mode when pass_through_sel bit is 1'b1

pass_through_ma

nual

1'b0

bb_reset

1'b0

R/W

Soft reset

clk_oe_manual

Enable the PLL clock to appear on pin 5

Open Loop

operation

Open Loop operation (MPPT disabled, receives duty

cycle command from reg 3b13:5); set to 1 and then

assert & deassert bb_reset to put the device in

openloop (test only)

Table 4. reg4 Register Description

Bits

55:32

31:24

23:16

15:8

Field

RSVD

Reset Value

R/W

Bit Field Description

Reserved

24'd0

8'h0

Vout offset

Iout offset

Vin offset

Iin offset

Voltage out offset

Current out offset

Voltage in offset

Current in offset

7:0

Table 5. reg5 Register Description

Bits

55:40

39:30

29:20

19:10

9:0

Field

Reset Value

R/W

Bit Field Description

Reserved

RSVD

15'd0

10'd40

10'd24

10'd40

10'd24

iin_hi_th

iin_lo_th

iout_hi_th

iout_lo_th

Current in high threshold for start

Current in low threshold for start

Current out high threshold for start

Current out low threshold for start

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Using the I2C port, the user will be able to control the duty cycle of the PWM signal. Input and output voltage and

current offset can also be controlled using I2C on register 4. Control registers are available for additional

flexibility.

The thresholds iin_hi_th, iin_lo_th, iout_hi_th, iout_lo_th, in reg5 are compared to the values read in by the ADC

on the AIIN and AIOUT pins. Scaling is set by the scaling of the analog signal fed into AIIN and AIOUT. These

10–bit values determine the entry and exit conditions for MPPT.

COMMUNICATING WITH THE SM72442

The SCL line is an input, the SDA line is bidirectional, and the device address can be set by I2C0, I2C1 and I2C2

pins. Three device address pins allow connection of up to 7 SM72444s to the same I2C master. A pull-up

resistor (10k) to a 5V supply is used to set a bit 1 on the device address. Device addressing for slaves are as

follows:

I2C0

I2C1

I2C2

Hex

0x1

0x2

0x3

0x4

0x5

0x6

0x7

The data registers in the SM72442 are selected by the Command Register. The Command Register is offset

from base address 0xE0. Each data register in the SM72442 falls into one of two types of user accessibility:

1) Read only (Reg0, Reg1)

2) Write/Read same address (Reg3, Reg4, Reg5)

There are 7 bytes in each register (56 bits), and data must be read and written in blocks of 7 bytes. Figure 10

depicts the ordering of the bytes transmitted in each frame and the bits within each byte. In the read sequence

depicted in Figure 11 the data bytes are transmitted in Frames 5 through 11, starting from the LSByte, DATA1,

and ending with MSByte, DATA7. In the write sequence depicted in Figure 12, the data bytes are transmitted in

Frames 4 through 11. Only the 100kHz data rate is supported. Please refer to “The I2C Bus Specification”

version 2.1 (Doc#: 939839340011) for more documentation on the I2C bus.

7 Byte Data Frame:

DATA 1 DATA 2 DATA 3

LSByte

DATA 6 DATA 7

MSByte

Each Byte contains 8 bits data:

LSBit

MSBit

Figure 10. Endianness Diagram

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SCL

SDA

A6 A5 A4 A3 A2 A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

Ack

SM72442

Ack Repeat

Start by

Master

Start by

SM72442 Master

Frame 2

Command

Frame 1

Serial Bus Address Byte

SCL

(Continued)

SDA

(Continued)

A6 A5 A4 A3 A2 A1 A0

D7 D6 D5 D4 D3 D2 D1 D0

R/W

Ack

SM72442

Frame 3

Frame 4

Serial Bus Address Byte

Length Byte = 7

SCL

(Continued)

SDA

(Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Stop

Ack

No Ack

Master

SM72442

Frame 10

Data 6

Frame 11

Data 7

Figure 11. I2C Read Sequence

SCL

SDA

A6 A5 A4 A3 A2 A1 A0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

Ack

SM72442

Ack

SM72442

Start by

Master

Frame 2

Command

Frame 1

Serial Bus Address Byte

SCL

(Continued)

SDA

(Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Ack

SM72442

Frame 3

Length Byte = 7

Frame 4

Data 1

SCL

(Continued)

SDA

(Continued)

D7 D6 D5 D4 D3 D2 D1 D0

Stop

Ack

No Ack

Master

SM72442

Frame 10

Data 6

Frame 11

Data 7

Figure 12. I2C Write Sequence

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Product Folder Links: SM72442

SM72442

www.ti.com

SNVS689H –OCTOBER 2010–REVISED APRIL 2013

Noise coupling into digital lines greater than 400 mVp-p (typical hysteresis) and undershoot less than 500 mV

GND, may prevent successful I2C communication with SM72442. I2C no acknowledge is the most common

symptom, causing unnecessary traffic on the bus although the I2C maximum frequency of communication is

rather low (400 kHz max), care still needs to be taken to ensure proper termination within a system with multiple

parts on the bus and long printed board traces. Additional resistance can be added in series with the SDA and

SCL lines to further help filter noise and ringing. Minimize noise coupling by keeping digital races out of switching

power supply areas as well as ensuring that digital lines containing high speed data communications cross at

right angles to the SDA and SCL lines.

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Product Folder Links: SM72442

SM72442

SNVS689H –OCTOBER 2010–REVISED APRIL 2013

www.ti.com

REVISION HISTORY

Changes from Revision G (April 2013) to Revision H

Page

•

Changed layout of National Data Sheet to TI format .......................................................................................................... 15

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Product Folder Links: SM72442

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION

Orderable Device

SM72442MT/NOPB

SM72442MTE/NOPB

SM72442MTX/NOPB

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

-40 to 125

Top-Side Markings

Samples

Drawing

Qty

(1)

(2)

(3)

(4)

ACTIVE

TSSOP

Green (RoHS

& no Sb/Br)

CU SN

Level-3-260C-168 HR

SO2442

ACTIVE

250

Green (RoHS

& no Sb/Br)

-40 to 125

SO2442

2500

Green (RoHS

& no Sb/Br)

-40 to 125

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SM72442MTE/NOPB

SM72442MTX/NOPB

TSSOP

250

178.0

330.0

16.4

6.8

10.2

1.6

8.0

16.0

2500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SM72442MTE/NOPB

SM72442MTX/NOPB

TSSOP

250

213.0

367.0

191.0

367.0

55.0

38.0

2500

Pack Materials-Page 2

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SM72442MTX/NOPB [TI]

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