SM72445 [TI]

Programmable Maximum Power Point Tracking Controller With Adjustable PWM Frequency; 可编程最大功率点跟踪控制器，可调节PWM频率


型号：	SM72445
厂家：	TEXAS INSTRUMENTS
描述：	Programmable Maximum Power Point Tracking Controller With Adjustable PWM Frequency 可编程最大功率点跟踪控制器，可调节PWM频率控制器
文件：	总19页 (文件大小：350K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

March 7, 2012

SM72445

Programmable Maximum Power Point Tracking Controller

With Adjustable PWM Frequency

General Description

Features

The SM72445 is a programmable MPPT controller capable of

controlling four PWM gate drive signals for a 4-switch buck-

boost converter. The SM72445 also features a proprietary

algorithm called Panel Mode (PM) which allows for the panel

to be connected directly to the output of the power optimizer

circuit when the input to output voltage ratio is close to 1. This

provides an opportunity to optimize the efficiency of the power

optimizer when the load is naturally matching the maximum

power point of the panel. Along with the SM72295 (Photo-

voltaic Full Bridge Driver), it creates a solution for an MPPT

configured DC-DC converter with efficiencies up to 99.5%

(when operating with dedicated PM switches). Integrated into

the chip is an 8-channel, 10 bit A/D converter used to sense

input and output voltages and currents, as well as IC config-

uration. Externally programmable values include maximum

output voltage and current as well as different settings for slew

rate, soft-start and Panel Mode.

Renewable Energy Grade

■

110kHz,135kHz or 215kHz PWM operating frequency

Panel Mode pin for optional bypass switch control

Programmable maximum power point tracking

Photovoltaic solar panel voltage and current diagnostic

Single inductor four switch buck-boost converter control

I2C interface for communication

Output overvoltage protection

Over-current protection

■

Package

TSSOP-28

■

Block Diagram

30176102

FIGURE 1. Block Diagram

301761 SNVS795

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Connection Diagram

30176103

FIGURE 3. Top View

TSSOP-28

Ordering Information

Order Number

Description

NSC Package Drawing

Supplied As

Package Top Marking

2500 Units in Tape and

Reel

SM72445MTX

TSSOP-28

MTC28

SM72445

250 Units in Tape and

Reel

SM72445MTE

SM72445MT

TSSOP-28

MTC28

SM72445

48 Units in Rail

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Pin Descriptions

Name

RST

Description

Active low signal. External reset input signal to the digital circuit.

Reserved for test only. This pin should be grounded.

NC1

Digital supply voltage. This pin should be connected to a 5V supply, and bypassed to VSSD with a 0.1 µF monolithic

ceramic capacitor.

VDDD

VSSD

NC2

I2C0

I2C1

SCL

SDA

NC3

Digital ground. The ground return for the digital supply and signals.

This pin should be pulled up to the 5V supply using a 10k resistor.

Addressing for I2C communication.

I2C clock.

I2C data.

Reserved for test only. This pin should be grounded.

When Panel Mode is active, this pin will output a 440 kHz square wave signal with amplitude of 5V. Otherwise, it

stays low.

PM_OUT

Analog supply voltage. This voltage is also used as the reference voltage. This pin should be connected to a 5V

supply, and bypassed to VSSA with a 1 µF and 0.1 µF monolithic ceramic capacitor.

VDDA

VSSA

Analog ground. The ground return for the analog supply and signals.

A/D Input Channel 0. Connect a resistor divider to 5V supply to set the maximum output voltage. Please refer to

the application section for more information on setting the resistor value.

AVIN

Input voltage sensing pin.

A/D Input Channel 2. Connect a resistor divider to a 5V supply to set the condition to enter and exit Panel Mode

(PM). Refer to the “Configurable Settings” section.

AVOUT Output voltage sensing pin.

A/D Input Channel 4. Connect a resistor divider to a 5V supply to set the maximum output current. Please refer to

the application section for more information on setting the resistor value.

Input current sensing pin.

AIIN

A/D Input Channel 6. Connect a resistor divider to a 5V supply to set the output voltage slew rate and various PM

configurations. Refer to the “Configurable Settings” section.

AIOUT Output current sensing pin.

I2C2

NC4

LIB

Addressing for I2C communication.

This pin should be connected with a 60.4k pull-up resistor to 5V.

Low side boost PWM output.

HIB

HIA

LIA

High side boost PWM output.

High side buck PWM output.

Low side buck PWM output.

Panel Mode Pin. Active low. Pulling this pin low will force the chip into Panel Mode.

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Absolute Maximum Ratings (Note 1)

If Military/Aerospace specified devices are required,

please contact the Texas Instruments Sales Office/

Distributors for availability and specifications.

Recommended Operating

Conditions

Operating Temperature

-40°C to 105°C

V_ASupply Voltage

V_DSupply Voltage

Digital Input Voltage

Analog Input Voltage

Junction Temperature

+4.75V to +5.25V

+4.75V to V_A

0 to V_A

Analog Supply Voltage V_A

(VDDA - VSSA)

Digital Supply Voltage V_D

(VDDD - VSSD)

-0.3 to 6.0V

-0.3 to V_A+0.3V

max 6.0V

-0.3 to V_A+0.3V

0 to V_A

Voltage on Any Pin to GND

-40°C to 125°C

Input Current at Any Pin (Note 3)

Package Input Current (Note 3)

Storage Temperature Range

ESD Rating

±10 mA

±20 mA

-65°C to +150°C

(Note 2)

Human Body Model

2 kV

Electrical Characteristics

Specifications in standard typeface are for T_J= 25°C, and those in boldface type apply over the full operating junction temperature

range.(Note 3). Typical values represent the most likely parametric norm at T_J= 25°C, and are provided for reference purposes

only. Unless otherwise stated the following conditions apply: V_D=V_A=5V.

Symbol

Parameter

Conditions

Min

Typ

Max

Units

ANALOG INPUT CHARACTERISTICS

AVin, AIin

0 to V_A

Input Range

AVout, AIout

I_DCL

DC Leakage Current

±1

µA

Track Mode

Hold Mode

C_INA

Input Capacitance (Note 4)

DIGITAL INPUT CHARACTERISTICS

V_IL

Input Low Voltage

2.8

0.8

V_IH

C_IND

I_IN

Input High Voltage

Digital Input Capacitance (Note 4)

Input Current

µA

±0.01

±1

DIGITAL OUTPUT CHARACTERISTICS

V_OH

V_OL

I_SOURCE= 200 µA

V_D- 0.5

Output High Voltage

Output Low Voltage

I_SINK= 200 µA to 1.0 mA

0.4

Hi-Impedance Output Leakage

Current

I_OZH, I_OZL

C_OUT

±1

µA

Hi-Impedance Output

Capacitance (Note 4)

POWER SUPPLY CHARACTERISTICS (C_L= 10 pF)

Analog and Digital Supply

Voltages

V_A,V_D

4.75

5.25

16.5

V_A≥ V_D

I_A+ I_D

Total Supply Current

11.5

PWM OUTPUT CHARACTERISTICS

A2 High Frequency Setting:

f_PWM

PWM switching frequency

170

105

215

250

155

kHz

Dead time (for Buck switch node

and for Boost switch node)

t_DEAD

A2 MediumFrequency Setting:

f_PWM

PWM switching frequency

Dead time

135

kHz

t_DEAD

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Symbol

Parameter

Conditions

Min

Typ

Max

125

Units

PWM OUTPUT CHARACTERISTICS (Continued)

A2 Low Frequency Setting:

f_PWM

PWM switching frequency

Dead time

110

106

kHz

t_DEAD

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation

of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,

see the Electrical Characteristics tables.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.

Note 3: Min and Max limits are production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality

Control (SQC) methods.

Note 4: Not tested. Guaranteed by design.

Typical Performance Characteristics

Typical performance curves reflect the performance of the SM72445 as designed into the SM3320–1A1 reference design, and

are provided for reference purposes only. Unless otherwise stated the following conditions apply: T_J= 25°C.

Typical Efficiency, Vmp 33V

Peak Efficiency vs Vmp

30176154

30176152

Peak Efficiency vs Temperature

Frequency Temperature Dependence

1.025

1.020

1.015

1.010

1.005

1.000

0.995

0.990

0.985

0.980

0.975

-40 -20

20 40 60 80 100 120 140

30176153

TEMPERATURE (°C)

30176151

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Operation Description

OVERVIEW

the PWM duty cycle to maximize energy harvested from the

photovoltaic module. MPPT performance is very fast. Con-

vergence to the maximum power point of the module typically

occurs within 0.01s. This enables the controller to maintain

optimum performance under fast-changing irradiance condi-

tions.

The SM72445 is a programmable MPPT controller capable of

outputting four PWM gate drive signals for a 4 switch buck-

boost converter with an independent Panel Mode. The typical

application circuit is shown in Figure 2. The SM72445 does

not require a dedicated switch to implement Panel Mode. The

four buck-boost switches can be controlled to implement PM.

A dedicated switch may be used for higher efficiency. Setting

the voltage on pin A2 selects between the options.

Transitions between buck, boost, and Panel Mode are

smoothed. Output voltage and current limiting functionality

are integrated into the digital control logic. The controller is

capable of handling both shorted and no-load conditions and

will recover smoothly from both conditions.

The SM72445 uses an advanced digital controller to generate

its PWM signals. A maximum power point tracking (MPPT)

algorithm monitors the input current and voltage and controls

30176104

FIGURE 4. High Level State Diagram for Startup

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STARTUP

put connected to the reset pin of the SM72445 is one possible

implementation.

SM72445 has a soft start feature that will ramp its output volt-

age for a time of 250ms if the bridge is configured to run at

215kHz and up to 500ms if the bridge is configured for

110kHz.

The maximum output voltage is always enforced during

MPPT operation of the IC.

The following equation sets the maximum output voltage:

If no output current is detected during soft-start time, the de-

vice will then enter Panel Mode for 60 seconds. A counter will

start once the minimum output current threshold is met (set

by ADC input channel 4, pin A4). During these 60 seconds,

any variation on the output power will not cause the chip to

enter MPPT mode. Once 60 seconds have elapsed, the unit

will enter operational PM mode and the pre-determined power

level variation at the output will engage the chip in MPPT

mode.

Where RT1 and RB1 are the resistor divider on the ADC pin

A0 and RFB1 and RFB2 are the output voltage sense resis-

tors. A typical value for RFB2 is about 2 kΩ

CURRENT LIMIT SETTING

If the output current is greater than the current threshold set

at A/D Channel 6 (A6) during soft-start, the chip will then en-

gage in MPPT mode and will not be subject to the start-up

delay.

Maximum output current can be set by changing the resistor

divider on A4 (pin 18). Refer to Figure 2. Overcurrent at the

output is detected when the voltage on AIOUT (pin 21) equals

the voltage on A4 (pin 18). The voltage on A4 can be set by

a resistor divider connected to 5V whereas the voltage on

AIOUT can be set by a current sense amplifier.

AVIN PIN

AVIN is an A/D input to sense the input voltage of the

SM72445. A resistor divider can be used to scale max voltage

to about 4V, which is 80% of the full scale of the A/D input.

CONFIGURABLE SETTINGS

A/D pins A0, A2, A4, and A6 are used to configure the be-

havior of the SM72445 by adjusting the voltage applied to

them through resistor dividers as shown in Figure 2, where

RT1 to RT4 should be in the range of 20 kΩ.

The voltages of the configuration pins are read and the oper-

ating mode is then set at start-up and after each reset of the

device.

Three different frequencies for the PWM operation of the H-

bridge as well as two different implementations of the Panel

Mode switch can be set on the ADC input channel 2 (pin A2).

The table below lists the different conditions that a user can

select on pin A2. Each frequency has a different associated

dead time for the operation of the synchronous switches.

When dedicated PM switch modes are used, the unit will stop

switching the converter upon entering PM mode and the

PM_OUT pin will switch at a high frequency to provide acti-

vation of a dedicated Panel Mode switch. When the H-bridge

modes are used, the unit will keep the H-bridge switching at

half the operating frequency (to reduce switching losses) and

with a total input to output ratio of 1. The dead times are un-

changed during this phase.

30176105

FIGURE 5. Startup Sequence

MAXIMUM OUTPUT VOLTAGE

The maximum output voltage on the SM72445 is set by the

resistor divider ratio on pin A0. (Please refer to Figure 2 Typ-

ical Application Circuit).

The value of the voltage on pin A0 is sampled and stored by

the ADC of the SM72445 at start-up and after reset events.

While voltage on pin AVOUT is above the voltage set at pin

A0, the duty cycle of the converter will be reduced every

MPPT cycle (1ms-2ms depending on the set switching fre-

quency). This is true when the converter is running in MPPT

state or during Soft-Start. When the unit is in Panel Mode (PM)

or in Startup Panel Mode (PM_Startup) there is no control on

the output voltage and the device will not react to the presence

of a voltage on AVOUT higher than the A0 setpoint. See Fig-

ure 4 for more details on the different states of operation.

TABLE 1 Programmable Settings on Pin A2

PWM Frequency

setting

Panel Mode Operation

4.69 V

4.06 V

3.44 V

2.81 V

2.19 V

HIGH

LOW

MED.

HIGH

Uses dedicated PM

switch

Uses dedicated PM

switch

This means that the voltage limit setting cannot be used to

ensure overall maximum output voltage for the system: there

will be times during Panel Mode operation and Stand-by

mode operation when the output will increase above the pro-

grammed output voltage if the input (solar panel) gets over

that voltage limit. Therefore, the maximum output voltage

threshold set by programming A0 is only valid if its value is

higher than the maximum input voltage (solar panel in open

circuit at coldest operating point). If over-voltage protection

needs to be implemented, it must be done using external

components. For exampe, a voltage comparator with its out-

Uses H-bridge for PM

operation

Uses H-bridge for PM

operation

Uses H-bridge for PM

operation

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soft-start period has finished, by changing the voltage level

on pin A6 which is the input of ADC channel 6. The slew rate

limiter takes control of the duty cycle if the output voltage rises

faster than the programmed limit while the unit is running in

Boost mode (output voltage higher than input voltage). The

device will control the duty cycle so that the output voltage

stays within the allowed slew rate. The slew rate is never lim-

ited in Buck mode (output voltage lower than input voltage).

PWM Frequency

setting

Panel Mode Operation

1.56 V

0.94 V

0.31 V

LOW

MED.

HIGH

Uses dedicated PM

switch

Uses dedicated PM

switch

Uses dedicated PM

switch

The user can also select the output voltage slew rate, mini-

mum current threshold and duration of Panel Mode after the

TABLE 2 Programmable Settings on Pin A6

Output Voltage

Slew Rate Limit

Starting Panel MPPT Exit

Mode Time Threshold (on

MPPT Start

Threshold (on

AIOUT)

Starting boost ratio

AIOUT or AIIN)

4.69 V

4.06 V

3.44 V

2.81 V

2.19 V

1.56 V

0.94 V

0.31 V

10V/1.2s

Not applicable

0 V

N/A

1:1

60s

0.006xVDDA

0.023xVDDA

0.006xVDDA

0.023xVDDA

0.010xVDDA

0.039xVDDA

0.010xVDDA

0.039xVDDA

10V/1.2s

120s

1:1

10V/1.2s

1:1

10V/1.2s

Not applicable

60s

1:1.2

1:1

10V/1.2s

10V/0.6s

60s

1:1

No slew rate limit

60s

1:1

PARAMETER DEFINITIONS

means it stops when Vout = Vin, whereas a 1:1.2 ratio means

it stops when Vout = 1.2 x Vin.

Output Voltage Slew Rate Limit Settling Time: Time con-

stant of the internal filter used to limit output voltage change.

At the fast slew rate, the output voltage will be held for 60 ms

for every 1V increase, whereas in the slow slew rate, the out-

put voltage will be held for 120ms for every 1V increase. (See

Figure 6).

DEAD-TIME

The dead time of the switches to avoid cross conduction of

the buck FETs and boost FETs depends on the switching fre-

quency set: it is equal to (3/256) x 1/f_SWITCH. When the IC is

programmed for 215 kHz operation, the dead time between

HIA and LOA and between HIB and LOB will be 55ns.

Starting PM Time: After initial power-up or reset, the output

soft-starts and then enters Panel Mode for this amount of

time.

PANEL MODE PIN (PM)

MPPT Exit Threshold and MPPT Start Threshold: These

are the hysteretic thresholds for Iout_th read on pin AIOUT.

The values are expressed as a fraction of the voltage at pin

VDDA. AIOUT is the output current sensing pin and should

be connected to the output of a current sense amplifier. For

example, with a current sense amplification of 0.5V/A provid-

ed by an external current sense resistor and amplifier and

assuming VDDA=5V and A6=0.94V, the output current

threshold to bring the device out of stand-by mode will be

0.39A.

The SM72445 can be forced into Panel Mode by pulling the

PM pin low. One sample application is to connect this pin to

the output of an external temperature sensor; therefore when-

ever an over-temperature condition is detected the chip will

enter Panel Mode.

Once Panel Mode is enabled, either when the unit is running

in MPPT mode with a 1:1 conversion ratio or when PM is

pulled low, the PM_OUT pin will output a 440 kHz square

wave signal. Using a gate driver and transformer, this square

wave signal can then be used to drive a Panel Mode FET as

shown in Figure 7.

Starting Boost Ratio: This is the end-point of the soft-start

voltage ramp expressed as a ratio of VOUT/VIN. 1:1 ratio

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30176113

FIGURE 6. Slew Rate Limitation Circuit

30176107

FIGURE 7. Sample Application for Panel Mode Operation

RESET PIN

As seen in Figure 8, the initial value for output voltage and

load current are 28V and 1A respectively. After the reset pin

is grounded both the output voltage and load current de-

creases immediately. MOSFET switching on the buck-boost

converter also stops immediately. VLOB indicates the low

side boost output from the SM72295.

When the reset pin is pulled low, the chip will cease its normal

operation and turn-off all of its PWM outputs including the

output of PM_OUT pin. Below is an oscilloscope capture of a

forced reset condition.

ANALOG INPUT

An equivalent circuit for one of the ADC input channels is

shown in Figure 9. Diode D1 and D2 provide ESD protection

for the analog inputs. The operating range for the analog in-

puts is 0V to V_A. Going beyond this range will cause the ESD

diodes to conduct and result in erratic operation.

The capacitor C1 in Figure 9 has a typical value of 3 pF and

is mainly the package pin capacitance. Resistor R1 is the on

resistance of the multiplexer and track / hold switch; it is typ-

ically 500Ω. Capacitor C2 is the ADC sampling capacitor; it is

typically 30 pF. The ADC will deliver best performance when

driven by a low-impedance source (less than 100Ω). This is

especially important when sampling dynamic signals. Also

important when sampling dynamic signals is a band-pass or

low-pass filter which reduces harmonic and noise in the input.

These filters are often referred to as anti-aliasing filters.

30176108

FIGURE 8. Forced Reset Condition

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nals operating range is controlled by V_D. The output high

voltage is V_D– 0.5V (min) while the output low voltage is 0.4V

(max).

SCL and SDA

SCL is an input, and SDA is bidirectional with an open-drain

output. SCL and SDA do not have internal pull-ups. A “high”

level will not be observed on this pin until pull-up current is

provided by some external source, typically a pull-up resistor.

The choice of resistor value depends on many system factors

such as load capacitance and trace length. A typical value of

pull-up resistor for SM72445 ranges from 2 kΩ to 10 kΩ. For

more information, refer to the I2C Bus specification for se-

lecting the pull-up resistor value. The SCL and SDA outputs

can operate while being pulled up to 5V and 3.3V.

30176109

FIGURE 9. Equivalent Input Circuit

DIGITAL INPUTS and OUTPUTS

I2C CONFIGURATION REGISTERS

The digital input signals have an operating range of 0V to

V_A, where V_A= VDDA – VSSA. They are not prone to latch-

up and may be asserted before the digital supply V_D, where

V_D= VDDD – VSSD, without any risk. The digital output sig-

The operation of the SM72445 can be configured through its

I2C interface. Complete register settings for I2C lines are

shown below.

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reg0 Register Description

Bits

55:40

39:30

Field

RSVD

ADC6

Reset Value

16'h0

R/W

Bit Field Description

Reserved for future use.

10'h0

Analog Channel 6 (slew rate detection time constant,

see adc config worksheet)

29:20

19:10

9:0

ADC4

ADC2

ADC0

10'h0

Analog Channel 4 (iout_max: maximum allowed output

current)

Analog Channel 2 (operating mode, see adc_config

worksheet)

Analog Channel 0 (vout_max: maximum allowed

output voltage)

reg1 Register Description

Bits

55:41

Field

RSVD

mppt_ok

Vout

Reset Value

15'h0

R/W

Bit Field Description

Reserved for future use.

Internal mppt_start signal (test only)

Voltage out

1'h0

39:30

29:20

19:10

9:0

10'h0

Iout

10'h0

Current out

Vin

10'h0

Voltage in

Iin

10'h0

Current in

reg3 Register Description

Bits

55:47

Field

RSVD

Reset Value

9'd0

R/W

Bit Field Description

Reserved

overide_adcprog

1'b0

When set to 1'b1,the below overide registers used

instead of ADC

RSVD

1'b0

2'd1

3'd0

R/W

Reserved

44:43

42:40

A2_override

ADC2 (bits [9–7]) when reg3[46] is set. This allows

frequency and panel mode configuration to be set

through I2C

39:30

29:20

iout_max

vout_max

10'd1023

R/W

maximum current threshold instead of ADC ch4

maximum voltage threshold instead of ADC ch0

19:17

16:14

13:5

tdoff

tdon

3'h3

R/W

Dead time Off Time

Dead time On time

dc_open

9'hFF

1'b0

Open loop duty cycle (test only)

Overrides PM pin 28 and use reg3[3]

pass_through_s

pass_through_m

anual

1'b0

R/W

Control Panel Mode when pass_through_sel bit is 1'b1

bb_reset

1'b0

R/W

Soft reset

clk_oe_manual

Enable the PLL clock to appear on pin 5

Open Loop

operation

Open Loop operation (MPPT disabled, receives duty

cycle command from reg 3b13:5); set to 1 and then

assert & deassert bb_reset to put the device in

openloop (test only)

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reg4 Register Description

Bits

55:32

31:24

23:16

15:8

Field

RSVD

Reset Value

24'd0

8'h0

R/W

Bit Field Description

Reserved

Vout offset

Iout offset

Vin offset

Iin offset

Voltage out offset

Current out offset

Voltage in offset

Current in offset

8'h0

7:0

8'h0

reg5 Register Description

Bits

55:40

39:30

29:20

19:10

9:0

Field

Reset Value

15'd0

R/W

Bit Field Description

Reserved

RSVD

iin_hi_th

iin_lo_th

iout_hi_th

iout_lo_th

10'd40

Current in high threshold for start

Current in low threshold for start

Current out high threshold for start

Current out low threshold for start

10'd24

10'd40

10'd24

The open loop operation allows the user to set a fixed oper-

ating duty cycle (buck or boost) on the converter. The unit will

not sense current or voltage in this mode and will perform an

internal reset when exiting open loop mode.

Using the I2C port, the user will be able to control the duty

cycle of the PWM signal. Input and output voltage and current

offsets can also be controlled using I2C on register 4. Control

registers are available for additional flexibility.

The bb_reset bit performs a limited reset of the IC. While this

bit is set high, the unit will not output any driving signal and

will not sense any input. When this bit is transited back to zero,

the unit will go through its initialization phase according to the

programming mode set and possible I2C overrides. The IC

will NOT perform a sample of the A0–A6 input when the

bb_reset bit is cleared.

The thresholds iin_hi_th, iin_lo_th, iout_hi_th, iout_lo_th, in

reg5 are compared to the values read in by the ADC on the

AIIN and AIOUT pins. Scaling is set by the scaling of the ana-

log signal fed into AIIN and AIOUT. These 10–bit values

determine the entry and exit conditions for MPPT. The startup

high thresholds set the voltages at pin AIIN and AIOUT above

which the unit will begin transition from PM_Startup state to

MPPT state. The low thresholds set the voltage below which

the unit will transition back to PM_Startup (stand-by). The ini-

tial thresholds are a function of the value programmed in A6.

As determined by , if A6 was between 0 and 1.56V at start-

up, the thresholds will be 0.023*VDDA and 0.039*VDDA.

To change the PWM frequency options the first time after

power up, the following programming sequence must be

used :

•

set bb_reset bit (reg3[2]), set over-ride bit (reg3[46]), set

to the desired PWM code (reg3[42:40])

To run the system in Open Loop configuration, the Soft Reset

bit must be set then cleared. The ADC channels are inactive

when the device is used in Open Loop configuration.

•

reset bb_reset bit, keep over-ride bit, keep the desired

PWM code

To change PWM options subsequent to an earlier program-

ming :

COMMUNICATING WITH THE SM72445

•

set bb_reset bit, reset over-ride bit, set to the desired PWM

code

reset bb_reset bit, reset over-ride bit, keep the desired

PWM code

set bb_reset bit, set over-ride bit, keep the desired PWM

code

reset bb_reset bit, keep over-ride bit, keep the desired

PWM code

The SCL line is an input, the SDA line is bidirectional, and the

device address can be set by the I2C0, I2C1 and I2C2 pins.

Three device address pins allow connection of up to 7

SM72445s to the same I2C master. A pull-up resistor

(10kΩ) to a 5V supply is used to set a bit 1 on the device

address. Device addressing for slaves are as follows:

I2C0

I2C1

I2C2

Hex

0x1

0x2

0x3

0x4

0x5

0x6

0x7

The switching frequency will be returned to the default exter-

nal resistor setting after each hard reset of the IC.

The “tdoff” and” tdon” (REG3[14:19]) parameters allow mod-

ification of the dead time. the dead time for the turning on of

the synchronous rectifier (affecting buck and boost mode) will

be set by (td_on/256)*(1/f_switch). The default parameter for

td_on is 3.

The dead time for the turning on of the main switch after the

synchronous rectifier as turned off (affecting buck and boost

mode) will be set by (td_off/256)*(1/f_switch). The default pa-

rameter for td_off is 3. The dead time parameters are returned

to their default value after each hard reset of the IC.

The offsets are 8 bit signed numbers which are added or sub-

stracted to the results of the A/D converter and affect the

sensed values displayed in Register 0 as well as the thresh-

olds.

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The data registers in the SM72445 are selected by the Com-

mand Register. The Command Register is offset from base

address 0xE0. Each data register in the SM72445 falls into

one of two types of user accessibility:

Specification” version 2.1 (Doc#: 939839340011) for more

documentation on the I2C bus.

1) Read only (Reg0, Reg1)

2) Write/Read same address (Reg3, Reg4, Reg5)

There are 7 bytes in each register (56 bits), and data must be

read and written in blocks of 7 bytes. Figure 10 depicts the

ordering of the bytes transmitted in each frame and the bits

within each byte. In the read sequence depicted in Figure

11 the data bytes are transmitted in Frames 5 through 11,

starting from the LSByte, DATA1, and ending with MSByte,

DATA7. In the write sequence depicted in Figure 12, the data

bytes are transmitted in Frames 4 through 11. Only the

100kHz data rate is supported. Please refer to “The I2C Bus

30176116

FIGURE 10. Endianness Diagram

30176112

FIGURE 11. I2C Read Sequence

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30176114

FIGURE 12. I2C Write Sequence

Noise coupling into digital lines greater than 400 mVp-p (typ-

ical hysteresis) and undershoot less than 500 mV below GND,

may prevent successful I2C communication with SM72445.

I2C no acknowledge is the most common symptom, causing

unnecessary traffic on the bus. Although the I2C maximum

frequency of communication is rather low (400 kHz max), care

still needs to be taken to ensure proper termination within a

system with multiple parts on the bus and long printed board

traces. Additional resistance can be added in series with the

SDA and SCL lines to further help filter noise and ringing.

Minimize noise coupling by keeping digital traces out of

switching power supply areas as well as ensuring that digital

lines containing high speed data communications cross at

right angles to the SDA and SCL lines.

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Physical Dimensions

30176150

NS Package Drawing MTC28

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Notes

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Notes

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SM72445 [TI]

相关型号：

SM72445MT

SM72445MT/NOPB

SM72445MTE

SM72445MTE/NOPB

SM72445MTX

SM72445MTX/NOPB

SM72445_15

SM72480

SM72480

SM72480SD-105

SM72480SD-105/NOPB

SM72480SD-120