LMH6601 [TI]
具有关断状态的 250MHz、2.4V CMOS 运算放大器;
| 型号： | LMH6601 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有关断状态的 250MHz、2.4V CMOS 运算放大器 放大器 运算放大器 |
| 文件： | 总40页 (文件大小：2180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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LMH6601, LMH6601-Q1
SNOSAK9F –JUNE 2006–REVISED JUNE 2015
LMH6601 and LMH6601-Q1 250-MHz, 2.4-V CMOS Operational Amplifier With Shutdown
1 Features
3 Description
The LMH6601 device is a low-voltage (2.4 V to 5.5
V), high-speed voltage feedback operational amplifier
suitable for use in a variety of consumer and
industrial applications. With a bandwidth of 125 MHz
at a gain of +2 and ensured high-output current of
100 mA, the LMH6601 is an ideal choice for video
line driver applications, including HDTV. Low-input
bias current (50 pA maximum), rail-to-rail output, and
low current noise allow the use of the LMH6601 in
1
•
LMH6601-Q1 Qualified for Automotive
Applications
–
–
AEC-Q100 Grade 3
–40°C to 85°C Ambient Operating
Temperature Range
•
VS = 3.3 V, TA = 25°C, AV = 2 V/V, RL = 150 Ω to
V−, Unless Specified
•
•
•
•
•
125 MHz −3 dB Small Signal Bandwidth
75 MHz −3 dB Large Signal Bandwidth
30 MHz Large Signal 0.1-dB Gain Flatness
260 V/μs Slew Rate
various
industrial
applications
such
as
transimpedance amplifiers, active filters, or high-
impedance buffers. The LMH6601 is an attractive
solution for systems which require high performance
at low supply voltages. The LMH6601 is available in a
6-pin SC70 package, and includes a micropower
shutdown feature.
0.25%/0.25° Differential Gain and Differential
Phase
•
•
•
Rail-to-Rail Output
Device Information(1)
2.4-V to 5.5-V Single-Supply Operating Range
6-Pin SC70 Package
PART NUMBER
LMH6601
PACKAGE
BODY SIZE (NOM)
SC70 (6)
2.00 mm × 1.25 mm
LMH6601-Q1
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
•
•
•
•
•
•
Video Amplifiers
Charge Amplifiers
Set-Top Boxes
Response at a Gain of +2
for Various Supply Voltages
Sample and Holds
Transimpedance Amplifiers
Line Drivers
7
6
5
High-Impedance Buffers
Automotive
2.7V
4
5V
3
3.3V
2
1
0
-1
1
10
100
1000
FREQUENCY (MHz
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6601, LMH6601-Q1
SNOSAK9F –JUNE 2006–REVISED JUNE 2015
www.ti.com
Table of Contents
7.1 Overview ................................................................. 20
7.2 Feature Description................................................. 20
7.3 Device Functional Modes........................................ 21
Application and Implementation ........................ 23
8.1 Application Information............................................ 23
8.2 Typical Application .................................................. 29
Power Supply Recommendations...................... 32
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings - for LMH6601 ..................................... 3
6.3 ESD Ratings - for LMH6601-Q1 ............................... 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics, 5 V ................................... 4
6.7 Electrical Characteristics, 3.3 V ................................ 6
6.8 Electrical Characteristics, 2.7 V ................................ 8
6.9 Switching Characteristics, 5 V ................................ 10
6.10 Switching Characteristics, 3.3 V ........................... 11
6.11 Switching Characteristics, 2.7 V ........................... 11
6.12 Typical Characteristics.......................................... 12
Detailed Description ............................................ 20
8
9
10 Layout................................................................... 32
10.1 Layout Guidelines ................................................. 32
10.2 Layout Examples................................................... 32
11 Device and Documentation Support ................. 33
11.1 Documentation Support ........................................ 33
11.2 Related Links ........................................................ 33
11.3 Community Resources.......................................... 33
11.4 Trademarks........................................................... 33
11.5 Electrostatic Discharge Caution............................ 33
11.6 Glossary................................................................ 33
12 Mechanical, Packaging, and Orderable
Information ........................................................... 33
7
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (March 2013) to Revision F
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Removed IOS over temperature limit in Electrical Characteristics, 2.7 V ............................................................................... 8
Moved the SAG Compensation section to the Typical Application section.......................................................................... 25
Changed section titled Other Applications to Charge Preamplifier ..................................................................................... 28
•
•
•
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format ............................................................................................................. 1
2
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Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
www.ti.com
SNOSAK9F –JUNE 2006–REVISED JUNE 2015
5 Pin Configuration and Functions
DCK Package
6-Pin SC70
Top View
6
5
+
1
V
OUTPUT
SD
-
2
3
V
-
+
4
-IN
+IN
Pin Functions
PIN
I/O
DESCRIPTION
NO.
1
NAME
OUTPUT
V-
O
I
Output
2
Negative supply
Noninverting input
Inverting input
Shutdown
3
+IN
I
4
-IN
I
5
SD
I
6
V+
I
Positive supply
6 Specifications
6.1 Absolute Maximum Ratings(1)
MIN
MAX
±2.5
UNIT
V
VIN Differential
Input Current(2)
±10
200 mA(3)
mA
mA
V
Output Current
Supply Voltage (V+ – V−)
6
Voltage at Input/Output Pins
V++0.5,
V
V−−0.5
Junction Temperature
150
235
260
150
°C
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
Soldering Information
Storage Temperature
°C
°C
−65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Negative input current implies current flowing out of the device.
(3) The maximum continuous output current (IOUT) is determined by device power dissipation limitations.
6.2 ESD Ratings - for LMH6601
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±1000
(1) Human Body Model, applicable std. MIL-STD-883, Method 3015.7.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2006–2015, Texas Instruments Incorporated
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LMH6601, LMH6601-Q1
SNOSAK9F –JUNE 2006–REVISED JUNE 2015
www.ti.com
6.3 ESD Ratings - for LMH6601-Q1
VALUE
±2000
±1000
UNIT
Human body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
V(ESD)
Electrostatic discharge
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.4 Recommended Operating Conditions(1)
MIN
2.4
MAX
5.5
UNIT
Supply Voltage (V+ – V−)
Operating Temperature
V
−40
85
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.5 Thermal Information
LMH6601,
LMH6601-Q1
THERMAL METRIC(1)
UNIT
DCK (SC70)
6 PINS
414
RθJA
Junction-to-ambient thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.6 Electrical Characteristics, 5 V
Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1)
PARAMETER
FREQUENCY DOMAIN RESPONSE
SSBW
TEST CONDITIONS
MIN(2)
TYP(2)
MAX(2)
UNIT
VOUT = 0.25 VPP
130
250
2.5
0
–3-dB Bandwidth Small Signal
MHz
SSBW_1
Peak
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
Peaking
dB
dB
Peak_1
LSBW
Peaking
–3-dB Bandwidth Large Signal
Peaking
VOUT = 2 VPP
81
MHz
dB
Peak_2
0.1 dB BW
GBWP_1k
GBWP_150
AVOL
VOUT = 2 VPP
0
0.1-dB Bandwidth
VOUT = 2 VPP
30
MHz
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150 Ω to VS/2
0.5 V < VOUT < 4.5 V
155
125
66
Gain Bandwidth Product
MHz
Large Signal Open-Loop Gain
Full Power BW
56
dB
–1 dB, AV = +4, VOUT = 4.2 VPP
RL = 150 Ω to VS/2
,
PBW
DG
30
0.06%
0.10
MHz
4.43 MHz, 1.7 V ≤ VOUT ≤ 3.3 V,
RL = 150 Ω to V−
Differential Gain
4.43 MHz, 1.7 V ≤ VOUT ≤ 3.3 V
RL = 150 Ω to V−
DP
Differential Phase
deg
pF
TIME DOMAIN RESPONSE
OS
CL
Overshoot
0.25-V Step
10%
50
Capacitor Load Tolerance
AV = −1, 10% Overshoot, 75 Ω in Series
(1) Electrical Characteristics, 5 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
4
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Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
www.ti.com
SNOSAK9F –JUNE 2006–REVISED JUNE 2015
Electrical Characteristics, 5 V (continued)
Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1)
PARAMETER
DISTORTION and NOISE PERFORMANCE
HD2
TEST CONDITIONS
MIN(2)
TYP(2)
MAX(2)
UNIT
2 VPP, 10 MHz
−56
−61
−73
−64
−58
7
Harmonic Distortion (2nd
)
dBc
dBc
HD2_1
HD3
HD3_1
THD
VN1
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
2 VPP, 10 MHz
Harmonic Distortion (3rd)
Total Harmonic Distortion
Input Voltage Noise
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
>10 MHz
nV/√Hz
fA/√Hz
VN2
1 MHz
10
IN
Input Current Noise
>1 MHz
50
STATIC, DC PERFORMANCE
±1
±2.4
±5
VIO
Input Offset Voltage
mV
At temperature extremes
(3)
DVIO
IB
Input Offset Voltage Average Drift See
−5
5
μV/°C
pA
(4)
(4)
Input Bias Current
Input Offset Current
Input Resistance
Input Capacitance
See
See
50
25
IOS
RIN
CIN
2
pA
0 V ≤ VIN ≤ 3.5 V
10
1.3
59
TΩ
pF
55
51
53
50
56
53
Positive Power Supply Rejection
Ratio
+PSRR
DC
DC
DC
dB
dB
At temperature
extremes
61
68
Negative Power Supply Rejection
Ratio
−PSRR
At temperature
extremes
CMRR
CMVR
Common-Mode Rejection Ratio
Input Voltage Range
dB
V
At temperature
extremes
CMRR > 50 dB (At temperature
extremes)
V− – 0.20
–
V+ – 1.5
11.5
9.6
Normal Operation
VOUT = VS/2
mA
nA
At temperature
extremes
13.5
ICC
Supply Current
Shutdown
SD tied to ≤ 0.5 V
100
(5)
–210
–480
–190
VOH1
VOH2
VOH3
RL = 150 Ω to V–
RL = 75 Ω to VS/2
RL = 10 kΩ to V–
At temperature
extremes
Output High Voltage
(Relative to V+)
–190
–12
mV
–60
At temperature
extremes
–110
(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(4) This parameter is ensured by design and/or characterization and is not tested in production.
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
SNOSAK9F –JUNE 2006–REVISED JUNE 2015
www.ti.com
Electrical Characteristics, 5 V (continued)
Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1)
PARAMETER
TEST CONDITIONS
MIN(2)
TYP(2)
MAX(2)
UNIT
5
45
VOL1
VOL2
VOL3
RL = 150 Ω to V–
At temperature
extremes
125
Output Low Voltage
(Relative to V–)
RL = 75 Ω to VS/2
RL = 10 kΩ to V–
120
5
mV
45
At temperature
extremes
125
Source
Sink
150
180
VOUT < 0.6 V from
Respective Supply
IO
Output Current
mA
VOUT = VS/2,
VID = ±18 mV
IO_1
±100
(6)
THD < −30 dBc, f = 200 kHz,
RL tied to VS/2, VOUT = 4 VPP
Load
Output Load Rating
20
Ω
RO_Enabled Output Resistance
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
MISCELLANEOUS PERFORMANCE
Enabled, AV = +1
Shutdown
0.2
>100
5
Ω
MΩ
pF
Shutdown
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5)
See (5) (At temperature extremes)
See (5) (At temperature extremes)
SD = 5 V(5)
0
0.5
5
V
V
Voltage Limit for Enable (Pin 5)
Logic Input Current (Pin 5)
Turnon Glitch
4.5
10
2.2
60
pA
V
V_glitch
IsolationOFF
Off Isolation
1 MHz, RL = 1 kΩ
dB
(6) “VID” is input differential voltage (input overdrive).
6.7 Electrical Characteristics, 3.3 V
Single-Supply with VS= 3.3 V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1)
PARAMETER
FREQUENCY DOMAIN RESPONSE
SSBW
TEST CONDITIONS
MIN(2)
TYP(2)
MAX(2)
UNIT
VOUT = 0.25 VPP
125
250
3
–3-dB Bandwidth Small Signal
MHz
SSBW_1
Peak
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
Peaking
dB
dB
Peak_1
LSBW
Peaking
0.05
75
–3-dB Bandwidth Large Signal
Peaking
VOUT = 2 V PP
MHz
dB
Peak_2
0.1 dB BW
GBWP_1k
GBWP_150
AVOL
VOUT = 2 VPP
0
0.1-dB Bandwidth
VOUT = 2 VPP
30
MHz
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150 Ω to VS/2
0.3 V < VOUT < 3 V
115
105
67
Gain Bandwidth Product
MHz
Large Signal Open-Loop Gain
Full Power BW
56
dB
–1 dB, AV = +4, VOUT = 2.8 VPP
RL = 150 Ω to VS/2
,
PBW
DG
30
0.06%
0.23
MHz
4.43 MHz, 0.85 V ≤ VOUT ≤ 2.45 V,
RL = 150 Ω to V−
Differential Gain
4.43 MHz, 0.85 V ≤ VOUT ≤ 2.45 V
RL = 150 Ω to V−
DP
Differential Phase
deg
(1) Electrical Characteristics, 3.3 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
6
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Copyright © 2006–2015, Texas Instruments Incorporated
Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
www.ti.com
SNOSAK9F –JUNE 2006–REVISED JUNE 2015
Electrical Characteristics, 3.3 V (continued)
Single-Supply with VS= 3.3 V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1)
PARAMETER
TIME DOMAIN RESPONSE
TEST CONDITIONS
MIN(2)
TYP(2)
MAX(2)
UNIT
OS
CL
Overshoot
Capacitor Load Tolerance
0.25-V Step
10%
50
AV = −1, 10% Overshoot, 82 Ω in Series
pF
DISTORTION and NOISE PERFORMANCE
HD2
2 VPP, 10 MHz
−61
−79
−53
−69
Harmonic Distortion (2nd
)
dBc
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
HD2_1
HD3
2 VPP, 10 MHz
Harmonic Distortion (3rd)
Total Harmonic Distortion
dBc
dBc
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
HD3_2
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
THD
−66
VN1
VN2
IN
>10 MHz
1 MHz
7
10
50
Input Voltage Noise
Input Current Noise
nV/√Hz
fA/√Hz
>1 MHz
STATIC, DC PERFORMANCE
±1
±2.6
±5.5
VIO
Input Offset Voltage
mV
At temperature extremes
(3)
DVIO
IB
Input Offset Voltage Average Drift
Input Bias Current
See
−4.5
5
μV/°C
pA
(4)
See
50
25
(4)
IOS
RIN
CIN
Input Offset Current
Input Resistance
See
2
pA
0 V ≤ VIN ≤ 1.8 V
15
1.4
80
TΩ
Input Capacitance
pF
DC
61
51
57
52
58
55
Positive Power Supply Rejection
Ratio
+PSRR
dB
dB
At temperature extremes
DC
72
73
Negative Power Supply Rejection
Ratio
−PSRR
At temperature extremes
DC
CMRR
CMVR
Common-Mode Rejection Ratio
Input Voltage
dB
V
At temperature extremes
CMRR > 50 dB (At temperature
extremes)
V− – 0.20
V+ – 1.5
11
9.2
Normal Operation
mA
nA
At temperature
VOUT = VS/2
ICC
Supply Current
13
extremes
Shutdown: SD tied to ≤ 0.33 V(5)
100
–210
–360
–190
VOH1
VOH2
VOH3
RL = 150 Ω to V–
At temperature
extremes
Output High Voltage
(Relative to V+)
RL = 75 Ω to VS/2
–190
–10
mV
–50
RL = 10 kΩ to V−
At temperature
extremes
–100
(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(4) This parameter is ensured by design and/or characterization and is not tested in production.
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
Copyright © 2006–2015, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
SNOSAK9F –JUNE 2006–REVISED JUNE 2015
www.ti.com
Electrical Characteristics, 3.3 V (continued)
Single-Supply with VS= 3.3 V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1)
PARAMETER
TEST CONDITIONS
MIN(2)
TYP(2)
MAX(2)
UNIT
4
45
VOL1
VOL2
VOL3
RL = 150 Ω to V–
At temperature
extremes
125
Output Low Voltage
(Relative to V–)
RL = 75 Ω to VS/2
RL = 10 kΩ to V–
105
4
mV
45
At temperature
extremes
125
VOUT < 0.6 V from Source
Respective
Supply
50
75
IO
Output Current
Sink
mA
IO_1
VOUT = VS/2, VID = ±18 mV(6)
±75
THD < −30 dBc, f = 200 kHz,
RL tied to VS/2, VOUT = 2.6 VPP
Load
Output Load Rating
25
Ω
RO_Enabled Output Resistance
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
MISCELLANEOUS PERFORMANCE
Enabled, AV = +1
Shutdown
0.2
>100
5.6
Ω
MΩ
pF
Shutdown
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5)
See (5) (At temperature extremes)
See (5) (At temperature extremes)
SD = 3.3 V(5)
0
0.33
3.3
V
V
Voltage Limit for Enable (Pin 5)
Logic Input Current (Pin 5)
Turnon Glitch
2.97
8
1.6
60
pA
V
V_glitch
IsolationOFF
Off Isolation
1 MHz, RL = 1 kΩ
dB
(6) “VID” is input differential voltage (input overdrive).
6.8 Electrical Characteristics, 2.7 V
Single-Supply with VS = 2.7 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise
specified.(1)
PARAMETER
FREQUENCY DOMAIN RESPONSE
SSBW
TEST CONDITIONS
MIN(2)
TYP(2)
MAX(2)
UNIT
VOUT = 0.25 VPP
120
250
3.1
0.1
73
–3-dB Bandwidth Small Signal
MHz
SSBW_1
Peak
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
Peaking
dB
dB
Peak_1
LSBW
Peaking
–3-dB Bandwidth Large Signal
Peaking
VOUT = 2 V PP
MHz
dB
Peak_2
0.1 dB BW
GBWP_1k
GBWP_150
AVOL
VOUT = 2 VPP
0
0.1-dB Bandwidth
VOUT = 2 VPP
30
MHz
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150 Ω to VS/2
0.25 V < VOUT < 2.5 V
110
81
Gain Bandwidth Product
MHz
Large Signal Open-Loop Gain
Full Power BW
56
65
dB
–1 dB, AV = +4, VOUT = 2 VPP
,
PBW
DG
13
MHz
RL = 150 Ω to VS/2
4.43 MHz, 0.45 V ≤ VOUT ≤ 2.05 V
RL = 150 Ω to V−
Differential Gain
0.12%
(1) Electrical Characteristics, 2.7 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
8
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SNOSAK9F –JUNE 2006–REVISED JUNE 2015
Electrical Characteristics, 2.7 V (continued)
Single-Supply with VS = 2.7 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise
specified.(1)
PARAMETER
TEST CONDITIONS
MIN(2)
TYP(2)
MAX(2)
UNIT
4.43 MHz, 0.45 V ≤ VOUT ≤ 2.05 V
RL = 150 Ω to V−
DP
Differential Phase
0.62
deg
TIME DOMAIN RESPONSE
OS Overshoot
DISTORTION and NOISE PERFORMANCE
0.25-V Step
10%
HD2
HD3
VN1
VN2
IN
Harmonic Distortion (2nd
)
1 VPP, 10 MHz
1 VPP, 10 MHz
>10 MHz
−58
−60
8.4
12
dBc
dBc
Harmonic Distortion (3rd)
Input Voltage Noise
Input Current Noise
nV/√Hz
fA/√Hz
1 MHz
>1 MHz
50
STATIC, DC PERFORMANCE
±1
±3.5
±6.5
VIO
Input Offset Voltage
mV
At temperature extremes
(3)
DVIO
IB
Input Offset Voltage Average Drift
Input Bias Current
See
−6.5
5
μV/°C
pA
(4)
See
50
25
(4)
IOS
RIN
CIN
Input Offset Current
Input Resistance
See
2
pA
0V ≤ VIN ≤ 1.2V
20
1.6
68
TΩ
Input Capacitance
pF
58
53
56
53
57
52
Positive Power Supply Rejection
Ratio
+PSRR
DC
DC
DC
dB
dB
At temperature
extremes
69
77
Negative Power Supply Rejection
Ratio
−PSRR
At temperature
extremes
CMRR
CMVR
Common-Mode Rejection Ratio
Input Voltage
dB
V
At temperature
extremes
CMRR > 50 dB (At temperature
extremes)
V− – 0.20
–
9
V+ – 1.5
10.6
Normal Operation
mA
nA
At temperature
VOUT = VS/2
12.5
ICC
Supply Current
extremes
Shutdown
100
SD tied to ≤ 0.27 V(5)
–260
–420
–200
VOH1
VOH2
VOH3
RL = 150 Ω to V–
At temperature
extremes
Output High Voltage
(Relative to V+)
RL = 75 Ω to VS/2
–200
–10
mV
–50
100
RL = 10 kΩ to V–
At temperature
extremes
(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(4) This parameter is ensured by design and/or characterization and is not tested in production.
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
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Electrical Characteristics, 2.7 V (continued)
Single-Supply with VS = 2.7 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise
specified.(1)
PARAMETER
TEST CONDITIONS
RL = 150 Ω to V–
MIN(2)
TYP(2)
MAX(2)
45
UNIT
4
VOL1
VOL2
125
Output Low Voltage
(Relative to V–)
RL = 75 Ω to VS/2
RL = 10 kΩ to V–
125
4
mV
45
VOL3
At temperature
extremes
125
V
OUT ≤ 0.6 V from Source
25
62
IO
Respective
Supply
Sink
Output Current
mA
Source
Sink
25
35
VOUT = VS/2, VID
= ±18 mV(6)
IO_1
THD < −30 dBc, f = 200 kHz, RL tied to
VS/2, VOUT = 2.2 VPP
Load
Output Load Rating
Output Resistance
40
Ω
RO_Enable
Enabled, AV = +1
Shutdown
0.2
>100
5.6
Ω
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
MISCELLANEOUS PERFORMANCE
MΩ
pF
Shutdown
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5)
See (5) (At temperature extremes)
See (5) (At temperature extremes)
SD = 2.7 V(5)
0
0.27
2.7
V
V
Voltage Limit for Enable (Pin 5)
Logic Input Current (Pin 5)
Turnon Glitch
2.43
4
1.2
60
pA
V
V_glitch
IsolationOFF
Off Isolation
1 MHz, RL = 1 kΩ
dB
(6) “VID” is input differential voltage (input overdrive).
6.9 Switching Characteristics, 5 V
Single-Supply with VS= 5 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise
specified.
PARAMETER
TIME DOMAIN RESPONSE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRS/TRL
SR
Rise and Fall Time
Slew Rate
0.25-V Step
2.6
275
50
ns
2-V Step
V/μs
TS
1-V Step, ±0.1%
Settling Time
ns
ns
TS_1
PD
1-V Step, ±0.02%
220
2.4
Propagation Delay
Input to Output, 250-mV Step, 50%
MISCELLANEOUS PERFORMANCE
Ton
Turnon Time
1.4
520
<20
µs
ns
ns
Toff
Turnoff Time
T_OL
Overload Recovery
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SNOSAK9F –JUNE 2006–REVISED JUNE 2015
6.10 Switching Characteristics, 3.3 V
Single-Supply with VS= 3.3 V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise specified.(1)
PARAMETER
TIME DOMAIN RESPONSE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRS/TRL
SR
Rise and Fall Time
Slew Rate
0.25-V Step
2.7
260
70
ns
2-V Step
V/μs
TS
1-V Step, ±0.1%
Settling Time
ns
ns
TS_1
PD
1-V Step, ±0.02%
300
2.6
Propagation Delay
Input to Output, 250-mV Step, 50%
MISCELLANEOUS PERFORMANCE
Ton
Toff
Turnon Time
Turnoff Time
3.5
µs
ns
500
(1) Electrical Characteristics, 3.3 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
6.11 Switching Characteristics, 2.7 V
Single-Supply with VS = 2.7 V, AV = +2, RF = 604 Ω, SD tied to V+, VOUT = VS/2, RL = 150 Ω to V− unless otherwise
specified.(1)
PARAMETER
TIME DOMAIN RESPONSE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TRS/TRL
SR
Rise and Fall Time
Slew Rate
0.25-V Step
2.7
260
147
410
3.4
ns
2-V Step
V/μs
TS
1-V Step, ±0.1%
Settling Time
ns
ns
TS_1
PD
1-V Step, ±0.02%
Propagation Delay
Input to Output, 250-mV Step, 50%
MISCELLANEOUS PERFORMANCE
Ton
Toff
Turnon Time
Turnoff Time
5.2
µs
ns
760
(1) Electrical Characteristics, 2.7 V values apply only for factory testing conditions at the temperature indicated. Factory testing conditions
result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA.
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6.12 Typical Characteristics
Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T
= 25°C.
3
3
80
80
V
= 3.3V
V
= 5V
S
GAIN
S
GAIN
0
-3
0
-3
40
40
0
0.25 V
PP
0
0.25 V
PHASE
PP
PHASE
-6
-40
-40
-80
-120
-160
-200
-6
1 V
PP
-9
-80
-9
1 V
PP
2 V
PP
-12
-120
-160
-200
-12
-15
-18
2 V
PP
-15
-18
1
10
100
1000
1
1000
10
100
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 1. Frequency Response
for Various Output Amplitudes
Figure 2. Frequency Response
for Various Output Amplitudes
3
80
150
125
V
= 2.7V
A
= +2
V
S
GAIN
0.25 V
PP
0
-3
40
0.25 V
PP
0
PHASE
-40
-80
-120
-160
-200
-6
100
75
1 V
PP
1 V
PP
-9
2 V
PP
-12
-15
-18
2 V
PP
50
2.5
3
3.5
4
4.5
5
1
10
100
1000
V
(V)
S
FREQUENCY (MHz)
Figure 4. −3 dB BW vs. Supply Voltage
Figure 3. Frequency Response
for Various Output Amplitudes
for Various Output Swings
3
0
60
3
60
A
= +1
V
GAIN
GAIN
A
= +2
V
40
0
40
A
= -1
= -2
= -5
V
A
= +5
V
-3
20
-3
-6
20
PHASE
PHASE
A
= +10
V
A
A
V
-6
0
0
-9
-20
-40
-60
-80
-100
-9
-20
-40
-60
-80
-100
V
A
= +1
V
-12
-15
-18
-21
-12
-15
-18
-21
A
= +2
V
A
= +5
V
A
= -10
V
A
= +10
V
V
= 0.25 V
PP
V
= 0.25 V
OUT PP
OUT
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Noninverting Frequency Response
for Various Gain
Figure 6. Inverting Frequency Response
for Various Gain
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SNOSAK9F –JUNE 2006–REVISED JUNE 2015
Typical Characteristics (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T
= 25°C.
6
3
6
3
30
2.7V
V
= 0.25 V
PP
PHASE
GAIN
OUT
-
0
R
TIED TO V
L
3.3V
5V
0
0
-30
1 k:
-3
-3
-60
50:
150:
-6
-6
-90
-9
-9
-120
-150
-180
-210
2.7V
3.3V
5V
100
-12
-15
-18
-12
-15
-18
A
V
= +1
V
= 0.25 V
OUT
PP
1
10
100
1000
1
10
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Frequency Response
for Various Loads
Figure 8. Frequency Response
for Various Supply Voltages
6
140
130
20 pF
10 pF
3
0
5V
5 pF
0 pF
120
110
-3
-6
3.3V
-9
100
20 pF
0 pF
-12
-15
-18
90
80
A
V
= +2
V
V
= 0.25 V
PP
OUT
-
= 2 V
OUT
PP
R
= 1 k: || C to V
L
L
100
-40 -20
0
20
40
60
80
1
10
100
1000
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 9. −3 dB BW
vs. Ambient Temperature
Figure 10. Frequency Response
for Various Capacitor Load
7
6
6
5
4
3
2
1
0
5
2.7V
4
THD < -30 dBc
5V
3
3.3V
2
1
V
A
= 5V
= +2
S
V
0
R
L
= 150: to V /2
S
-1
10k
100k
1M
10M
100M
1
10
100
1000
FREQUENCY (Hz)
FREQUENCY (MHz
Figure 11. Frequency Response
for Various Supply Voltage
Figure 12. Maximum Output Swing
vs. Frequency
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Typical Characteristics (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T
= 25°C.
2.5
2
1
5V
3.3V
3.3V
1.5
1
5V
2.7V
0.1
A
V
= +5 V/V
R
to V /2
S
L
V
_DC = V /2
OUT
0.5
S
UNDISORTED OUTPUT SWING
(LIMITED BY SOURCE CURRENT)
0.01
0
10 20 30 40 50 60 70 80 90 100
(:)
0
20
40
60
80
100
R
L
I
(mA)
SINK
Figure 14. Output Swing vs. Sink Current
for Various Supply Voltages
Figure 13. Peak Output Swing vs. RL
-30
10
V
= 2 V
PP
OUT
-35
-40
-45
1
-50
-55
-60
-65
-70
-75
3.3V
2.7V
5V
5V
0.1
-80
-85
-90
3.3V
0.01
0
20
40
60
80
100
1
100
10
0.1
I
(mA)
SOURCE
FREQUENCY (MHz)
Figure 15. Output Swing vs. Source Current
for Various Supply Voltages
Figure 16. HD2 vs. Frequency
-30
-40
V
= 2 V
PP
OUT
R
= 1 k: to V /2
L
S
-35
-40
-45
-50
-55
-60
-65
V
= 5V
S
-50
-60
10 MHz
2.7V
-70
-80
3.3V
-70
-75
-80
-85
-90
1 MHz
-90
5V
-100
1
10
100
0.1
0
0.5
1
1.5
2
2.5
3
3.5
)
4 4.5 5
FREQUENCY (MHz)
OUTPUT (V
PP
Figure 18. THD vs. Output Swing
Figure 17. HD3 vs. Frequency
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SNOSAK9F –JUNE 2006–REVISED JUNE 2015
Typical Characteristics (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T
= 25°C.
310
290
-20
-30
-40
R
= 1 k: to V /2
L
S
5V, FALLING
V
= 3.3V
S
270
3.3V, FALLING
-50
-60
5V, RISING
250
230
210
3.3V RISING
10 MHz
-70
-80
190
170
-90
A
V
= +2
V
1 MHz
= 2 V
PP
OUT
-100
150
0
0.5
1
2
2.5
3
-40 -20
0
20
40
60 80 100
1.5
OUTPUT (V
)
PP
TEMPERATURE (°C)
Figure 20. Slew Rate vs. Ambient Temperature
Figure 19. THD vs. Output Swing
80
70
60
A
= -1
V
R
= 150: to V /2
L
S
V
= 5V
S
50
40
30
20
V
= 5V
S
R
= 150: to V /2
L
S
A
V
= -1
V
10
0
= 1 V
PP
OUT
TIME (20 ns/DIV)
0
0.5
1
1.5
2
2.5
(V
3 3.5 4 4.5 5
V
)
OUT PP
Figure 22. Output Settling
Figure 21. Settling Time (±1%) vs. Output Swing
250
25
250
200
25
20
SETTLING TIME
SETTLING TIME
200
20
10% OVERSHOOT
ACROSS C
10% OVERSHOOT
L
150
100
50
15
10
5
150
100
50
15
10
ACROSS C
L
A
= -1
A = -1
V
V
R
= R = 1 k:
F
R
= R = 1 k:
F
L
L
V
V
= 5V
V
V
= 3.3V
S
O
S
O
= 1 V STEP
PP
= 1 V STEP
PP
5
0
ISOLATION RESISTOR
50 100 150
(pF)
ISOLATION RESISTOR
50 100 150
(pF)
0
0
0
0
200
250
0
200
250
C
L
C
L
Figure 23. Isolation Resistor and Settling Time vs. CL
Figure 24. Isolation Resistor and Settling Time vs. CL
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Typical Characteristics (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T
= 25°C.
0
100
10
1
V
A
= 5V
= +2
A
= +1
S
V
V
-10
-20
R
R
= R = 510:
G
F
L
= 100 k:
-30
-40
-50
-60
-70
2.7V
3.3V
5V
-80
-90
0.1
100k
1M
10M
100k
FREQUENCY (Hz)
10M
100M
100M
100
1k
10k
1M
FREQUENCY (Hz)
Figure 25. Closed-Loop Output Impedance
vs. Frequency for Various Supply Voltages
Figure 26. Off Isolation vs. Frequency
10000
250
200
60
50
40
30
20
10
0
150
PHASE
1000
100
50
2.7V
3.3V
0
100
GAIN
5V
10
1
10
1M
FREQUENCY (Hz)
100M
500M
1k
10k 100k
10M
10k
FREQUENCY (Hz)
100
1k
100k 1M
10M
Figure 27. Noise Voltage vs. Frequency
Figure 28. Open-Loop Gain and Phase
90
80
70
3.3V
80
2.7V
70
60
60
50
40
30
20
10
0
50
5V
40
30
20
10
0
1M
FREQUENCY (Hz)
10M
100M
1k
10k
100k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 29. CMRR vs. Frequency
Figure 30. +PSRR vs. Frequency
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SNOSAK9F –JUNE 2006–REVISED JUNE 2015
Typical Characteristics (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T
= 25°C.
10
9.8
9.6
80
70
60
50
40
30
20
10
0
3.3V
2.7V
5V
9.4
9.2
5V
3.3V
9
8.8
8.6
8.4
8.2
2.7V
-40 -20
0
20
40
60
80 100
10k
100k
1M
10M
100M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 32. Supply Current vs. Ambient Temperature
Figure 31. −PSRR vs. Frequency
18
12
V
V
=
5V
S
125°C
16
14
12
10
-
MEASURE FROM V
CM
10
85°C
8
-40°C
25°C
6
4
8
6
4
2
0
25°C
-40°C
2
0
5
0
0.5
1
1.5
2
2.5
(V)
3
3.5
4
4.5
1.5
2
2.5
3
3.5
(V)
4
4.5
V
CM
V
S
Figure 33. Supply Current vs. VCM
Figure 34. Supply Current vs. Supply Voltage
1.00
0.80
0.60
7
6.5
6
V
S
= 2.7V
UNIT 2
5.5
5
0.40
0.20
4.5
4
UNIT 1
3.5
3
0.00
-0.20
-0.40
-0.60
-0.80
UNIT 3
2.5
V
S
= 3.3V
2
1.5
1
0.5
0
-40 -20
0
20
40
60 80 100
-1.8 -1.4 -1 -0.6 -0.2 0.2 0.6
(mV)
1 1.4 1.8 2.2
TEMPERATURE (°C)
V
IO
Figure 35. Offset Voltage
Figure 36. Offset Voltage Distribution
vs. Ambient Temperature for 3 Representative Units
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Typical Characteristics (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T
= 25°C.
4
2
1000
100
10
125°C
85°C
25°C
125°
0
-2
-4
-6
OPERATION IS NOT
RECOMMENDED
-40°C
1
.1
25°C
-8
V
V
= 3.3V
S
-
MEASURED FROM V
V = 5V
S
CM
.01
-10
0
0.5
1
1.5
(V)
2
2.5
-1
0
1
2
3
4
5
6
V
CM
V
(V)
CM
Figure 37. Offset Voltage
vs. VCM (Typical Part)
Figure 38. Input Bias Current
vs. Common Mode Voltage
1.5
2.5
2
V
A
V
= 0.25 V
PP
V
A
V
= 2 V
PP
OUT
OUT
= +2
= +2
V
S
V
S
= 2.7V
= 2.7V
1.4
1.3
1.2
1.5
1
0.5
0
1.1
0
20
40
60
80
100
0
20
40
60
80
100
TIME (ns)
TIME (ns)
Figure 40. Large Signal Step Response
Figure 39. Small Signal Step Response
2.5
-
R
L
= 100: to V
A
= +1
V
0V
2
1.5
1
0V
V
= ±1.65V
S
R
L
= 150: to V /2
S
0.5
2.5 Ps/DIV
0
10
20
30
TIME (ns)
Figure 42. Turn On/Off Waveform
Figure 41. Large Signal Step Response
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Typical Characteristics (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604 Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150 Ω to V−, T
= 25°C.
0.2
0.1
0.2
0.1
-
V
= 5V
R
= 150: TO V
S
L
DC COUPLED
DG MEASURED RELATIVE
TO V = V /2 IN EACH
0
OUT
CASE
S
-0.1
V
= 2.5V
S
V
= 3.3V
-
S
0
-0.1
-0.2
-0.2
-0.3
V
= 5V
S
R
= 150: TO V
DC COUPLED
DP MEASURED
L
V
= 3.3V
S
-0.4
V
= 2.5V
RELATIVE TO V
=
S
OUT
-0.5
-0.6
V
/2 IN EACH CASE
S
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
-2.5 -2 -0.5 -1 -0.5
0
0.5
1
1.5
2
V
FROM V /2 (V)
V
FROM V /2 (V)
OUT
S
OUT
S
Figure 44. DP vs. VOUT for Various VS
Figure 43. DG vs. VOUT for Various VS
0.4
1
V
= 5V
S
0.8
R
= 150:
L
AC COUPLED
0.6
0.3
0.2
DG MEASURED
RELATIVE TO V
IN EACH CASE
= V /2
S
OUT
0.4
DC COUPLED
0.2
0
0.1
0
-0.2
AC COUPLED
-0.4
-0.6
-0.8
-1
V
= 5V
S
R
= 150:
L
-0.1
-0.2
DC COUPLED
DP MEASURED RELATIVE TO
V
= V /2 IN EACH CASE
OUT
S
-1
-0.6
-0.2
0.2
0.6
1
1
-1
-0.6
-0.2
0.2
0.6
V
FROM V /2 (V)
S
V
FROM V /2 (V)
OUT
OUT
S
Figure 45. DG vs. VOUT
Figure 46. DP vs. VOUT
(DC- and AC-Coupled Load Compared)
(DC- and AC-Coupled Load Compared)
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7 Detailed Description
7.1 Overview
The high-speed, ultra-high input impedance of the LMH6601 and its fast slew rate make the device an ideal
choice for video amplifier and buffering applications. There are cost benefits in having a single operating supply.
Single-supply video systems can take advantage of the low supply voltage operation of the LMH6601 along with
its ability to operate with input common-mode voltages at or slightly below the V− rail. Additional cost savings can
be achieved by eliminating or reducing the value of the input and output AC-coupling capacitors commonly
employed in single-supply video applications.
7.2 Feature Description
7.2.1 Shutdown Capability and Turn On/Off Behavior
With the device in shutdown mode, the output goes into high-impedance (ROUT > 100 MΩ) mode. In this mode,
the only path between the inputs and the output pin is through the external components around the device. So,
for applications where there is active signal connection to the inverting input, with the LMH6601 in shutdown, the
output could show signal swings due to current flow through these external components. For noninverting
amplifiers in shutdown, no output swings would occur, because of complete input-output isolation, with the
exception of capacitive coupling.
For maximum power saving, the LMH6601 supply current drops to around 0.1 μA in shutdown. All significant
power consumption within the device is disabled for this purpose. Because of this, the LMH6601 turnon time is
measured in microseconds whereas its turnoff is fast (nanoseconds) as would be expected from a high speed
device like this.
The LMH6601 SD pin is a CMOS compatible input with a pico-ampere range input current drive requirement.
This pin must be tied to a level or otherwise the device state would be indeterminate. The device shutdown
threshold is half way between the V+ and V− pin potentials at any supply voltage. For example, with V+ tied to 10
V and V− equal to 5 V, you can expect the threshold to be at 7.5 V. The state of the device (shutdown or normal
operation) is ensured over temperature as long as the SD pin is held to within 10% of the total supply voltage.
For V+ = 10 V, V− = 5 V, as an example:
•
•
Shutdown Range 5 V ≤ SD ≤ 5.5 V
Normal Operation Range 9.5 V ≤ SD ≤ 10 V
7.2.2 Overload Recovery and Swing Close to Rails
The LMH6601 can recover from an output overload in less than 20 ns. See Figure 47 for the input and output
scope photos:
V
= ±2.5V
S
INPUT (4 V
)
OUTPUT (1V/DIV)
PP
TIME (10 ns/DIV)
Figure 47. LMH6601 Output Overload Recovery Waveform
In Figure 47, the input step function is set so that the output is driven to one rail and then the other and then the
output recovery is measured from the time the input crosses 0 V to when the output reaches this point.
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Feature Description (continued)
Also, when the LMH6601 input voltage range is exceeded near the V+ rail, the output does not experience output
phase reversal, as do some op amps. This is particularly advantageous in applications where output phase
reversal must be avoided at all costs, such as in servo loop control among others. This adds to the set of
features of the LMH6601, which make this device easy to use.
In addition, the LMH6601 output swing close to either rail is well-behaved as shown in the scope photo of
Figure 48.
0V
0V
V
S
= ±2.5V
1 ms/DIV
Figure 48. Clean Swing of the LMH6601 to Either Rail
With some op amps, when the output approaches either one or both rails and saturation starts to set in, there is
significant increase in the transistor parasitic capacitances which leads to loss of Phase Margin. That is why with
these devices, there are sometimes hints of instability with output close to the rails. With the LMH6601, as can
be seen in Figure 48, the output waveform remains free of instability throughout its range of voltages.
7.3 Device Functional Modes
7.3.1 Optimizing Performance
With many op amps, additional device nonlinearity and sometimes less loop stability arises when the output must
switch from current-source mode to current-sink mode or vice versa. When it comes to achieving the lowest
distortion and the best Differential Gain/ Differential Phase (DG/ DP, broadcast video specs), the LMH6601 is
optimized for single-supply DC-coupled output applications where the load current is returned to the negative rail
(V−). That is where the output stage is most linear (lowest distortion) and which corresponds to unipolar current
flowing out of this device. To that effect, it is easy to see that the distortion specifications improve when the
output is only sourcing current which is the distortion-optimized mode of operation for the LMH6601. In an
application where the LMH6601 output is AC-coupled or when it is powered by separate dual supplies for V+ and
V−, the output stage supplies both source and sink current to the load and results in less than optimum distortion
(and DG/DP). Figure 49 compares the distortion results between a DC- and an AC-coupled load to show the
magnitude of this difference. See the DG/DP plots, Figure 43 through Figure 46, in Typical Characteristics, for a
comparison between DC- and AC-coupling of the video load.
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Device Functional Modes (continued)
-20
-30
-40
-50
-60
-70
-80
-90
-100
V
V
V
= 3.3V
S
= 2 V
PP
OUT
OUT
_DC = V /2
S
HD3, AC COUPLED
HD2, AC COUPLED
HD3, DC COUPLED
HD2, DC COUPLED
0.1
1
10
100
FREQUENCY (MHz)
Figure 49. Distortion Comparison between DC- and AC-Coupling of the Load
In certain applications, it may be possible to optimize the LMH6601 for best distortion (and DG/DP) even though
the load may require bipolar output current by adding a pulldown resistor to the output. Adding an output
pulldown resistance of appropriate value could change the LMH6601 output loading into source-only. This comes
at the price of higher total power dissipation and increased output current requirement.
Figure 50 shows how to calculate the pulldown resistor value for both the dual-supply and for the AC-coupled
load applications.
+
+
V
V
I
L-MAX
C
O
V
V
O
O
LMH6601
LMH6601
R
P
R
L
R
R
L
P
-
V
-
V
(a) DUAL SUPPLY
(b) AC-COUPLED LOAD
V–
(V )
VO_MIN
-1
R
RP
RP
≤
≤
L
IL_MAX
O_MIN
V
is the most
O_MIN
negative swing at output
V
is the most
O_MIN
negative swing at output
and I
is maximum load
L_MAX
current with direction shown
Figure 50. Output Pulldown Value for Dual-Supply and AC-Coupling
Furthermore, with a combination of low closed-loop gain setting (that is, AV = +1 for example where device
bandwidth is the highest), light output loading (RL > 1 kΩ) , and with a significant capacitive load (CL > 10 pF) ,
the LMH6601 is most stable if output sink current is kept to less than about 5 mA. The pulldown method
described in Figure 50 is applicable in these cases as well where the current that would normally be sunk by the
op amp is diverted to the RP path instead.
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
8.1.1 DC-Coupled, Single-Supply Baseband Video Amplifier and Driver
The LMH6601 output can swing very close to either rail to maximize the output dynamic range which is of
particular interest when operating in a low-voltage, single-supply environment. Under light output load conditions,
the output can swing as close as a few mV of either rail. This also allows a video amplifier to preserve the video
black level for excellent video integrity. In the example shown in Figure 51, the baseband video output is
amplified and buffered by the LMH6601 which then drives the 75-Ω back-terminated video cable for an overall
gain of +1 delivered to the 75-Ω load. The input video would normally have a level between 0 V to approximately
0.75 V.
V
= 2.7V
S
VIDEO IN (0-0.75V)
75: CABLE
+
V
LOAD
LMH6601
R
75:
-
S
R
75:
T
R
75:
L
R
620:
F
R
620:
G
Figure 51. Single-Supply Video Driver Capable of Maintaining Accurate Video Black Level
With the LMH6601 input common-mode range including the V− (ground) rail, there will be no need for AC-
coupling or level shifting and the input can directly drive the noninverting input which has the additional
advantage of high amplifier input impedance. With LMH6601’s wide rail-to-rail output swing, as stated earlier, the
video black level of 0 V is maintained at the load with minimal circuit complexity and using no AC-coupling
capacitors. Without true rail-to-rail output swing of the LMH6601, and more importantly without the LMH6601’s
ability of exceedingly close swing to V−, the circuit would not operate properly as shown at the expense of more
complexity. This circuit will also work for higher input voltages. The only significant requirement is that there is at
least 1.8 V from the maximum input voltage to the positive supply (V+).
The Composite Video Output of some low-cost consumer video equipment consists of a current source which
develops the video waveform across a load resistor (usually 75 Ω), as shown in Figure 52. With these
applications, the same circuit configuration just described and shown in Figure 52 will be able to buffer and drive
the Composite Video waveform which includes sync and video combined. However, with this arrangement, the
LMH6601 supply voltage must be at least 3.3 V or higher to allow proper input common-mode voltage headroom
because the input can be as high as 1-V peak.
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Application Information (continued)
VIDEO DAC
CURRENT
OUTPUT
V
S
= 3.3V
COMPOSITE
VIDEO IN 0-1V
+
V
LOAD
i
O
LMH6601
U1
75:
R
S
75:
-
R
L
75:
R
620:
F
R
620:
G
Figure 52. Single-Supply Composite Video Driver for Consumer Video Outputs
If the Video In signal is Composite Video with negative going Sync tip, a variation of the previous configurations
should be used. This circuit produces a unipolar (more than 0 V) DC-coupled single-supply video signal as
shown in Figure 53.
3.3V
R
30 k:
1
V
S
= 3.3V
0.8V
PP
0.61V ± 1.41V
0V - 2V
V
LOAD
+
LMH6601
R
10 k:
U1
2
R
75:
-
S
R
L
3.3V
75:
R
3
1.3 k:
VIDEO IN
-0.3V to 0.75V
R
620:
F
R
R
560:
T
G
75:
Figure 53. Single-Supply, DC-Coupled Composite Video Driver for Negative Going Sync Tip
In the circuit of Figure 53, the input is shifted positive by means of R1, R2, and RT in order to satisfy the common-
mode input range of the U1. The signal will loose 20% of its amplitude in the process. The closed-loop gain of U1
must be set to make up for this 20% loss in amplitude. This gives rise to the gain expression shown in
Equation 1, which is based on a getting a 2 VPP output with a 0.8 VPP input:
2V
R
F
-1 = 1.5V/V
=
0.8V
R ||R
G
3
(1)
R3 will produce a negative shift at the output due to VS (3.3 V in this case). R3 must be set so that the Video In
sync tip (−0.3 V at RT or 0.61 V at U1 noninverting input) corresponds to near 0 V at the output.
©
¨
©
¨
¨
§
§
1 +
§
RF
R3
0.61
RF
RG
RF
RG
¨
¨
¨
1 +
=
= 0.227
3.3V ± 0.61 ¨
¨
©
§
©
(2)
Equation 1 and Equation 2 must be solved simultaneously to arrive at the values of R3, RF, and RG which will
satisfy both. From the data sheet, one can set RF = 620 Ω to be close to the recommended value for a gain of
+2. It is easier to solve for RG and R3 by starting with a good estimate for one and iteratively solving Equation 1
and Equation 2 to arrive at the results. Here is one possible iteration cycle for reference:
RF = 620 Ω
(3)
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Application Information (continued)
Table 1. Finding External Resistor Values by Iteration for Figure 53
ESTIMATE
RG (Ω)
CALCULATED
(from Equation 2)
R3 (Ω)
Equation 1 LHS
CALCULATED
COMMENT
(COMPARE Equation 1 LHS calculated to RHS)
1k
1.69k
1.56k
1.37k
239
0.988
1.15
1.45
4.18
1.59
Increase Equation 1 LHS by reducing RG
Increase Equation 1 LHS by reducing RG
Increase Equation 1 LHS by reducing RG
Reduce Equation 1 LHS by increasing RG
Close to target value of 1.5V/V for Equation 1
820
620
390
560
1.30k
The final set of values for RG and R3 in Table 1 are values which will result in the proper gain and correct video
levels (0 V to 1 V) at the output (VLOAD).
8.1.2 How to Pick the Right Video Amplifier
Apart from output current drive and voltage swing, the op amp used for a video amplifier and cable driver should
also possess the minimum requirement for speed and slew rate. For video type loads, it is best to consider Large
Signal Bandwidth (or LSBW in the TI data sheet tables) as video signals could be as large as 2 VPP when
applied to the commonly used gain of +2 configuration. Because of this relatively large swing, the op amp Slew
Rate (SR) limitation should also be considered. Table 2 shows these requirements for various video line rates
calculated using a rudimentary technique and intended as a first-order estimate only.
Table 2. Rise Time, −3 dB BW, and Slew Rate Requirements for Various Video Line Rates
VIDEO
STANDARD
LINE RATE
(HxV)
REFRESH
RATE
HORIZONTA
L
ACTIVE
(KH%)
VERTICAL
ACTIVE
(KV%)
PIXEL TIME
(ns)
RISE TIME
(ns)
LSBW
(MHz)
SR
(V/μs)
(Hz)
TV_NTSC
VGA
451x483
640x480
30
75
75
75
75
75
84
80
76
77
75
74
92
95
96
95
96
96
118.3
33
39.4
11
9
41
32
146
237
387
655
973
SVGA
XGA
800x600
20.3
12.4
7.3
6.8
4.1
2.4
1.6
52
1024x768
1280x1024
1600x1200
85
SXGA
UXGA
143
213
4.9
For any video line rate (HxV corresponding to the number of Active horizontal and vertical lines), the speed
requirements can be estimated if the Horizontal Active (KH%) and Vertical Active (KV%) numbers are known.
These percentages correspond to the percentages of the active number of lines (horizontal or vertical) to the total
number of lines as set by VESA standards. Here are the general expressions and the specific calculations for the
SVGA line rate shown in Table 2.
1
x KH x KV
REFRESH_RATE
5
x 1 x 10
PIXEL_TIME (ns) =
H x V
1
x 76 x 96
75 Hz
5
=
x 1 x 10 = 20.3 ns
800 x 600
(4)
Requiring that an “On” pixel is illuminated to at least 90 percent of its final value before changing state will result
in the rise/fall time equal to, at most, ⅓ the pixel time as shown in Equation 5:
PIXEL_TIME
20.3 ns
6.8 ns
=
=
RISE/FALL_TIME =
3
3
(5)
Assuming a single pole frequency response roll-off characteristic for the closed-loop amplifier used, we have:
0.35
0.35
52 MHz
=
=
-3 dB_BW =
RISE/FALL_TIME
6.8 ns
(6)
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Rise/Fall times are 10%-90% transition times, which for a 2 VPP video step would correspond to a total voltage
shift of 1.6V (80% of 2 V). So, the Slew Rate requirement can be calculated as follows:
1.6V
1.6V
x 1 x 103
237(V/Ps)
=
=
SR(V/Ps) =
RISE/FALL_TIME (ns)
6.8 ns
(7)
The LMH6601 specifications show that it would be a suitable choice for video amplifiers up to and including the
SVGA line rate as demonstrated above.
For more information about this topic and others relating to video amplifiers, see Application Note 1013, Video
Amplifier Design for Computer Monitors (SNVA031).
8.1.3 Current to Voltage Conversion (Transimpedance Amplifier (TIA)
Being capable of high speed and having ultra low input bias current makes the LMH6601 a natural choice for
Current to Voltage applications such as photodiode I-V conversion. In these type of applications, as shown in
Figure 54, the photodiode is tied to the inverting input of the amplifier with RF set to the proper gain (gain is
measured in Ω).
C
F
R
F
-
D
LMH6601
1
V
OUT
U1
C
D
C
A
+
V
BIAS
Figure 54. Typical Connection of a Photodiode Detector to an Op Amp
With the LMH6601 input bias current in the femto-amperes range, even large values of gain (RF) do not increase
the output error term appreciably. This allows circuit operation to a lower light intensity level which is always of
special importance in these applications. Most photo-diodes have a relatively large capacitance (CD) which would
be even larger for a photo-diode designed for higher sensitivity to light because of its larger area. Some
applications may run the photodiode with a reverse bias to reduce its capacitance with the disadvantage of
increased contributions from both dark current and noise current. Figure 55 shows a typical photodiode
capacitance plot vs. reverse bias for reference.
600
T = 23°C
PIN-RD100
500
400
300
200
PIN-RD100A
PIN-RD15
PIN-RD07
100
0
0.1
1
10
100
REVERSED BIAS VOLTAGE (V)
Figure 55. Typical Capacitance vs. Reverse Bias (Source: OSI Optoelectronics)
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The diode capacitance (CD) combined with the input capacitance of the LMH6601 (CA) has a bearing on the
stability of this circuit and how it is compensated. With large transimpedance gain values (RF), the total combined
capacitance on the amplifier inverting input (CIN = CD + CA) will work against RF to create a zero in the Noise
Gain (NG) function (see Figure 56). If left untreated, at higher frequencies where NG equals the open-loop
transfer function excess phase shift around the loop (approaching 180°) and therefore, the circuit could be
unstable. This is illustrated in Figure 56.
OP AMP OPEN-
LOOP GAIN
I-V GAIN (Ω)
NOISE GAIN (NG)
1 + sR (C + C )
IN
F
F
1 + sR C
F
F
C
IN
1 +
C
F
0 dB
1
GBWP
1
FREQUENCY
f
z
=
f
=
P
2πR C
F
F
2πR C
F
IN
Figure 56. Transimpedance Amplifier Graphical Stability Analysis and Compensation
Figure 56 shows that placing a capacitor, CF, with the proper value, across RF will create a pole in the NG
function at fP. For optimum performance, this capacitor is usually picked so that NG is equal to the open-loop
gain of the op amp at fP. This will cause a “flattening” of the NG slope beyond the point of intercept of the two
plots (open-loop gain and NG) and will results in a Phase Margin (PM) of 45° assuming fP and fZ are at least a
decade apart. This is because at the point of intercept, the NG pole at fP will have a 45° phase lead contribution
which leaves 45° of PM. For reference, Figure 56 also shows the transimpedance gain (I-V (Ω))
Here is the theoretical expression for the optimum CF value and the expected −3-dB bandwidth:
CIN
CF =
2S(GBWP)RF
(8)
GBWP
#
f
-3 dB
2SR C
F
IN
(9)
Table 3 lists the results, along with the assumptions and conditions, of testing the LMH6601 with various
photodiodes having different capacitances (CD) at a transimpedance gain (RF) of 10 kΩ.
Table 3. Transimpedance Amplifier Compensation and Performance Results for Figure 54
CD
(pF)
CIN
(pF)
CF_CALCULATED
(pF)
CF USED
(pF)
−3 dB BW
CALCULATED
(MHz)
−3 dB BW
MEASURED (MHz) OVERSHOOT (%)
STEP RESPONSE
10
50
12
52
1.1
2.3
7.2
1
3
8
14
7
15
7
6
4
9
500
502
2
2.5
CA = 2 pF GBWP = 155 MHz VS = 5 V
(10)
8.1.4 Transimpedance Amplifier Noise Considerations
When analyzing the noise at the output of the I-V converter, it is important to note that the various noise sources
(that is, op amp noise voltage, feedback resistor thermal noise, input noise current, photodiode noise current) do
not all operate over the same frequency band. Therefore, when the noise at the output is calculated, this should
be taken into account.
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The op amp noise voltage will be gained up in the region between the noise gain’s “zero” and its “pole” (fz and fp
in Figure 56). The higher the values of RF and CIN, the sooner the noise gain peaking starts and therefore its
contribution to the total output noise would be larger. It is obvious to note that it is advantageous to minimize CIN
(for example, by proper choice of op amp, by applying a reverse bias across the diode at the expense of excess
dark current and noise). However, most low noise op amps have a higher input capacitance compared to
ordinary op amps. This is due to the low noise op amp’s larger input stage.
8.1.5 Charge Preamplifier
R
R
C
C
= 10 M: to 10 G:
F
= 1 M: or SMALLER FOR HIGH COUNTING RATES
S
= 1 pF
F
= 1 pF to 10 PF
D
V
= Q/C WHERE Q is CHARGE
F
OUT
CREATED BY ONE PHOTON or PARTICLE
ADJUST V FOR MAXIMUM SNR
BIAS
C
F
R
F
C
10 k:
R
S
D
-
LMH6601
V
+
-
OUT
U1
+
1000 pF
D
1
V
BIAS
Figure 57. Charge Preamplifier Taking Advantage of the Femto-Ampere Range Input Bias Current of the
LMH6601
8.1.6 Capacitive Load
The LMH6601 can drive a capacitive load of up to 1000 pF with correct isolation and compensation. Figure 58
illustrates the in-loop compensation technique to drive a large capacitive load.
R
R
F
G
C
F
-
R
S
V
OUT
LMH6601
V
IN
U1
+
R
2 k:
L
C
L
Figure 58. In-Loop Compensation Circuit for Driving a Heavy Capacitive Load
When driving a high-capacitive load, an isolation resistor (RS) should be connected in series between the op amp
output and the capacitive load to provide isolation and to avoid oscillations. A small-value capacitor (CF) is
inserted between the op amp output and the inverting input as shown such that this capacitor becomes the
dominant feedback path at higher frequency. Together these components allow heavy capacitive loading while
keeping the loop stable.
There are few factors which affect the driving capability of the op amp:
•
•
Op amp internal architecture
Closed-loop gain and output capacitor loading
Table 4 shows the measured step response for various values of load capacitors (CL), series resistor (RS) and
feedback resistor (CF) with gain of +2 (RF = RG = 604 Ω) and RL = 2 kΩ:
28
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Table 4. LMH6601 Step Response Summary for the Circuit of Figure 58
CL
(pF)
RS
(Ω)
CF
(pF)
trise/ tfall
(ns)
OVERSHOOT
(%)
10
0
0
1
1
6(1)
7(1)
10
8
50
6
110
300
500
910
47
6
1
16
20
10
10
10
10
10
12
80
192
33
65
(1) Response limited by input step generator rise time of 5 ns
Figure 59 shows the increase in rise/fall time (bandwidth decrease) at VOUT with larger capacitive loads,
illustrating the trade-off between the two:
70
60
50
40
30
20
10
0
10
100
CAP LOAD C (pF)
1000
L
Figure 59. LMH6601 In-Loop Compensation Response
8.2 Typical Application
8.2.1 SAG Compensation for AC-Coupled Video
Many monitors and displays accept AC-coupled inputs. This simplifies the amplification and buffering task in
some respects. The capacitors shown in Figure 60 (except CG2), and especially CO, are the large electrolytic type
which are considerably costly and take up valuable real estate on the board. It is possible to reduce the value of
the output coupling capacitor, CO, which is the largest of all, by using what is called SAG compensation. SAG
refers to what the output video experiences due to the low frequency video content it contains which cannot
adequately go through the output AC-coupling scheme due to the low frequency limit of this circuit. The −3 dB
low frequency limit of the output circuit is given by:
f_low_frequency (−3 dB)= 1/ (2*π* 75*2(Ω) * Co) = ∼ 4.82 Hz for CO = 220 μF
(11)
5V
R
5V
1
C
IN
0.47 PF
510 k:
R
O
CABLE
V
75:
IN
+
LMH6601
U1
V
OUT
R
IN
75:
R
2
510 k:
C
-
O
R
L
220 PF
75:
R
F
620:
R
G
C
G2
620:
+
C
G
47 PF
Figure 60. AC-Coupled Video Amplifier and Driver
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Typical Application (continued)
8.2.2 Design Requirements
As shown in Figure 60, R1 and R2 simply set the input to the center of the input linear range while CIN AC
couples the video onto the input of the op amp. The op amp is set for a closed-loop gain of 2 with RF and RG. CG
is there to make sure the device output is also biased at mid-supply. Because of the DC bias at the output, the
load must be AC-coupled as well through CO. Some applications implement a small valued ceramic capacitor
(not shown) in parallel with CO which is electrolytic. The reason for this is that the ceramic capacitor will tend to
shunt the inductive behavior of the Electrolytic capacitor at higher frequencies for an improved overall low
impedance output.
CG2 is intended to boost the high-frequency gain to improve the video frequency response. This value is to be set
and trimmed on the board to meet the specific system requirements of the application.
A possible implementation of the SAG compensation is shown in Figure 61.
V
_5V
CC
R
V
_5V
1
CC
C
IN
C
68 PF
+
O
510 k:
R
0.47 PF
O
75:
CABLE
V
IN
+
V
-
O
LMH6601
V
L
R
2
510 k:
R
T
75:
U1
-
R
75:
L
R
4
R
1 k:
3
2 k:
C
1
22 PF
-
+
R
5
680:
Figure 61. AC-Coupled Video Amplifier/Driver With SAG Compensation
8.2.3 Detailed Design Procedure
In the circuit of Figure 61, the output coupling capacitor value and size is reduced at the expense of a slightly
more complicated circuitry. Note that C1 is not only part of the SAG compensation, but it also sets the amplifier’s
DC gain to 0 dB so that the output is set to mid-rail for linearity purposes. Also, exceptionally high values are
chosen for the R1 and R2 biasing resistors (510 kΩ). The LMH6601 has extremely low input bias current which
allows this selection thereby reducing the CIN value in this circuit such that CIN can even be a nonpolar capacitor
which will reduce cost.
At high enough frequencies where both CO and C1 can be considered to be shorted out, R3 shunts R4 and the
closed-loop gain is determined by:
Closed_loop_Gain (V/V) = VL/VIN = (1+ (R3||R4)/ R5) x [RL/(RL+RO)]= 0.99 V/V
(12)
At intermediate frequencies, where the CO, RO, RL path experiences low frequency gain loss, the R3, R5, C1 path
provides feedback from the load side of CO. With the load side gain reduced at these lower frequencies, the
feedback to the op amp inverting node reduces, causing an increase at the output of the op amp as a response.
For NTSC video, low values of CO influence how much video black level shift occurs during the vertical blanking
interval (∼1.5 ms) which has no video activity and thus is sensitive to the charge dissipation of the CO through the
load which could cause output SAG. An especially tough pattern is the NTSC pattern called “Pulse & Bar.” With
this pattern the entire top and bottom portion of the field is black level video where, for about 11 ms, CO is
discharging through the load with no video activity to replenish that charge.
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Typical Application (continued)
8.2.4 Application Curves
Figure 62 shows the output of the Figure 61 circuit highlighting the SAG.
Figure 62. AC-Coupled Video Amplifier/Driver Output Scope Photo Showing Video SAG
With the circuit of Figure 61 and any other AC-coupled pulse amplifier, the waveform duty cycle variations exert
additional restrictions on voltage swing at any node. This is illustrated in the waveforms shown in Figure 63.
If a stage has a 3 VPP unclipped swing capability available at a given node, as shown in Figure 63, the maximum
allowable amplitude for an arbitrary waveform is ½ of 3 V or 1.5 VPP. This is due to the shift in the average value
of the waveform as the duty cycle varies. Figure 63 shows what would happen if a 2 VPP signal were applied. A
low duty cycle waveform, such as the one in Figure 63B, would have high positive excursions. At low enough
duty cycles, the waveform could get clipped on the top, as shown, or a more subtle loss of linearity could occur
prior to full-blown clipping. The converse of this occurs with high duty cycle waveforms and negative clipping, as
depicted in Figure 63C.
4.0V (+) CLIPPING
(A)
50% DUTY CYCLE
2V
2.5V
p-p
NO CLIPPING
1.0V (-) CLIPPING
4.0V (+) CLIPPING
(B)
2V
p-p
LOW DUTY CYCLE
CLIPPED POSITIVE
2.5V
1.0V (-) CLIPPING
4.0V (+) CLIPPING
2.5V
(C)
HIGH DUTY CYCLE
CLIPPED NEGATIVE
2V
p-p
1.0V (-) CLIPPING
Figure 63. Headroom Considerations With AC-Coupled Amplifiers
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9 Power Supply Recommendations
The LMH6601 can operate off a single-supply or with dual supplies. The input CM capability of the parts (CMVR)
extends all the way down to the V- rail to simplify single-supply applications. Supplies should be decoupled with
low-inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins. TI recommends
the use of ground plane, and as in most high-speed devices, it is advisable to remove ground plane close to
device sensitive pins such as the inputs.
10 Layout
10.1 Layout Guidelines
Generally, a good high-frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15, Frequent Faux Pas in Applying Wideband Current
Feedback Amplifiers, SNOA367, for more information).
10.2 Layout Examples
SC-70 Board Layout (Actual size = 1.5 in × 1.5 in
Figure 64. Layer 1 Silk
SC-70 Board Layout (Actual size = 1.5 in × 1.5 in
Figure 65. Layer 2 Silk
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SNOSAK9F –JUNE 2006–REVISED JUNE 2015
11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For additional information, see the following:
•
•
Application Note 1013, Video Amplifier Design for Computer Monitors, SNVA031
Application Note OA-15, Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, SNOA367
11.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 5. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
LMH6601
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
LMH6601-Q1
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
LMH6601MG/NOPB
LMH6601MGX/NOPB
LMH6601QMG/NOPB
ACTIVE
ACTIVE
ACTIVE
SC70
SC70
SC70
DCK
DCK
DCK
6
6
6
1000 RoHS & Green
3000 RoHS & Green
1000 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
A95
A95
AKA
SN
SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LMH6601, LMH6601-Q1 :
Catalog: LMH6601
•
Automotive: LMH6601-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Oct-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6601MG/NOPB
LMH6601MGX/NOPB
LMH6601QMG/NOPB
SC70
SC70
SC70
DCK
DCK
DCK
6
6
6
1000
3000
1000
178.0
178.0
178.0
8.4
8.4
8.4
2.25
2.25
2.25
2.45
2.45
2.45
1.2
1.2
1.2
4.0
4.0
4.0
8.0
8.0
8.0
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Oct-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6601MG/NOPB
LMH6601MGX/NOPB
LMH6601QMG/NOPB
SC70
SC70
SC70
DCK
DCK
DCK
6
6
6
1000
3000
1000
208.0
208.0
208.0
191.0
191.0
191.0
35.0
35.0
35.0
Pack Materials-Page 2
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