LMH6601MG [NSC]
250 MHz, 2.4V CMOS Op Amp with Shutdown; 250兆赫， 2.4V CMOS运算放大器，带有关断
| 型号： | LMH6601MG |
| 厂家： | 
National Semiconductor |
| 描述： | 250 MHz, 2.4V CMOS Op Amp with Shutdown |
| 文件： | 总27页 (文件大小：1509K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2006
LMH6601
250 MHz, 2.4V CMOS Op Amp with Shutdown
General Description
Features
The LMH6601 is a low voltage (2.4V – 5.5V), high speed
voltage feedback operational amplifier suitable for use in a
variety of consumer and industrial applications. With a band-
width of 125 MHz at a gain of +2 and guaranteed high output
current of 100 mA, the LMH6601 is an ideal choice for video
line driver applications including HDTV. Low input bias cur-
rent (50 pA maximum), rail-to-rail output, and low current
noise allow the LMH6601 to be used in various industrial
applications such as transimpedance amplifiers, active fil-
ters, or high-impedance buffers. The LMH6601 is an attrac-
tive solution for systems which require high performance at
low supply voltages. The LMH6601 is available in a 6-pin
SC70 package, and includes a micropower shutdown fea-
ture.
VS = 3.3V, TA = 25˚C, AV = 2 V/V, RL = 150Ω to V−, unless
specified.
n 125 MHz −3 dB small signal bandwidth
n 75 MHz −3 dB large signal bandwidth
n 30 MHz large signal 0.1 dB gain flatness
n 260 V/µs slew rate
n 0.25%/0.25˚ differential gain/differential phase
n Rail-to-rail output
n 2.4V – 5.5V single supply operating range
n SC70-6 Package
Applications
n Video amplifier
n Charge amplifier
n Set-top box
n Sample & hold
n Transimpedance amplifier
n Line driver
n High impedance buffer
Response at a Gain of +2 for Various Supply Voltages
20136441
© 2006 National Semiconductor Corporation
DS201364
www.national.com
Absolute Maximum Ratings (Note 1)
Storage Temperature Range
Junction Temperature
−65˚C to +150˚C
+150˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Soldering Information
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
235˚C
260˚C
ESD Tolerance (Note 4)
Human Body Model
Machine Model
2 kV
200V
2.5V
Operating Ratings (Note 1)
Supply Voltage (V+ – V−)
VIN Differential
2.4V to 5.5V
Input Current
10 mA
Operating Temperature Range
−40˚C to +85˚C
Output Current
200 mA (Note 3)
Package Thermal Resistance (θJA
)
Supply Voltage (V+ – V−)
6.0V
6-pin SC70
414˚C/W
Voltage at Input/Output Pins
V++0.5V, V−−0.5V
5V Electrical Characteristics Single Supply with VS= 5V, AV = +2, RF = 604Ω, SD tied to V+, VOUT
=
VS/2, RL = 150Ω to V− unless otherwise specified. Boldface limits apply at temperature extremes. (Note 2)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 6) (Note 6) (Note 6)
Frequency Domain Response
SSBW
SSBW_1
Peak
–3 dB Bandwidth Small Signal VOUT = 0.25 VPP
130
250
2.5
0
MHz
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
Peaking
Peaking
dB
dB
Peak_1
LSBW
–3 dB Bandwidth Large Signal VOUT = 2 VPP
81
MHz
dB
Peak_2
Peaking
VOUT = 2 VPP
0
0.1 dB BW 0.1 dB Bandwidth
VOUT = 2 VPP
30
MHz
GBWP_1k
GBWP_150
AVOL
Gain Bandwidth Product
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150Ω to VS/2
155
125
MHz
<
<
Large Signal Open Loop Gain 0.5V VOUT 4.5V
56
66
30
dB
PBW
Full Power BW
Differential Gain
Differential Phase
–1 dB, AV = +4, VOUT = 4.2 VPP
,
MHz
RL = 150Ω to VS/2
DG
DP
4.43 MHz, 1.7V ≤ VOUT ≤ 3.3V,
RL = 150Ω to V−
0.06
0.10
%
4.43 MHz, 1.7V ≤ VOUT ≤ 3.3V
RL = 150Ω to V−
deg
Time Domain Response
TRS/TRL
OS
Rise & Fall Time
0.25V Step
2.6
10
ns
%
Overshoot
Slew Rate
Settling Time
0.25V Step
SR
2V Step
275
50
V/µs
TS
1V Step, 0.1%
1V Step, 0.02%
ns
TS_1
PD
220
2.4
50
Propagation Delay
Input to Output, 250 mV Step, 50%
AV = −1, 10% Overshoot, 75Ω in
Series
ns
CL
Cap Load Tolerance
pF
Distortion & Noise Performance
HD2
HD2_1
HD3
HD3_1
THD
VN1
Harmonic Distortion (2nd
)
2 VPP, 10 MHz
−56
−61
−73
−64
−58
7
dBc
dBc
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
2 VPP, 10 MHz
Harmonic Distortion (3rd)
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
Total Harmonic Distortion
Input Voltage Noise
>
10 MHz
nV/
fA/
VN2
1 MHz
10
>
IN
Input Current Noise
1 MHz
50
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2
5V Electrical Characteristics Single Supply with VS= 5V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2,
RL = 150Ω to V− unless otherwise specified. Boldface limits apply at temperature extremes. (Note 2) (Continued)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 6) (Note 6) (Note 6)
Static, DC Performance
VIO
Input Offset Voltage
1
2.4
mV
5.0
DVIO
Input Offset Voltage Average
Drift
(Note 8)
−5
µV/˚C
IB
Input Bias Current
Input Offset Current
Input Resistance
Input Capacitance
Positive Power Supply
Rejection Ratio
(Note 9)
(Note 9)
5
2
50
25
pA
pA
GΩ
pF
IOS
>
RIN
100
1.3
59
CIN
+PSRR
DC
DC
55
51
dB
−PSRR
CMRR
Negative Power Supply
Rejection Ratio
53
61
68
dB
dB
50
Common Mode Rejection Ratio DC
56
53
V− -0.20
>
CMVR
ICC
Input Voltage Range
Supply Current
CMRR 50 dB
Normal Operation
VOUT = VS/2
–
V+ - 1.5
11.5
V
9.6
mA
nA
13.5
Shutdown
100
SD tied to ≤ 0.5V (Note 5)
RL = 150Ω to V–
VOH1
Output High Voltage
(Relative to V+)
–210
–190
–480
VOH2
VOH3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
–190
–12
mV
mV
–60
–110
VOL1
Output Low Voltage
(Relative to V–)
RL = 150Ω to V–
+5
+45
+125
VOL2
VOL3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
+120
+5
+45
+125
<
IO
Output Current
VOUT 0.6V from
Source
Sink
150
180
Respective Supply
mA
IO_1
Load
VOUT = VS/2,
100
VID
=
18 mV (Note 10)
<
Output Load Rating
THD −30 dBc, f = 200 kHz,
RL tied to VS/2, VOUT = 4 VPP
Enabled, AV = +1
20
Ω
RO_Enabled Output Resistance
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
Miscellaneous Performance
0.2
Ω
>
Shutdown
100
MΩ
pF
Shutdown
5.0
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5) (Note 5)
Voltage Limit for Enable (Pin 5) (Note 5)
0
0.5
5.0
V
V
4.5
Logic Input Current (Pin 5)
Turn-on Glitch
SD = 5V (Note 5)
10
2.2
1.4
520
60
pA
V
V_glitch
Ton
Turn-on Time
µs
ns
dB
ns
Toff
Turn-off Time
IsolationOFF Off Isolation
T_OL Overload Recovery
1 MHz, RL = 1 kΩ
<
20
3
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3.3V Electrical Characteristics Single Supply with VS= 3.3V, AV = +2, RF = 604Ω, SD tied to V+,
VOUT = VS/2, RL = 150Ω to V− unless otherwise specified. Boldface limits apply at temperature extremes. (Note 2)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 6) (Note 6) (Note 6)
Frequency Domain Response
SSBW
SSBW_1
Peak
–3 dB Bandwidth Small Signal VOUT = 0.25 VPP
125
250
3
MHz
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
Peaking
Peaking
dB
dB
Peak_1
LSBW
0.05
75
–3 dB Bandwidth Large Signal VOUT = 2 V
MHz
dB
PP
Peak_2
Peaking
VOUT = 2 VPP
0
0.1 dB BW 0.1 dB Bandwidth
VOUT = 2 VPP
30
MHz
GBWP_1k
GBWP_150
AVOL
Gain Bandwidth Product
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150Ω to VS/2
115
105
MHz
<
<
Large Signal Open Loop Gain 0.3V VOUT 3V
56
67
30
dB
PBW
Full Power BW
Differential Gain
Differential Phase
–1 dB, AV = +4, VOUT = 2.8VPP
,
MHz
RL = 150Ω to VS/2
DG
DP
4.43 MHz, 0.85V ≤ VOUT ≤ 2.45V,
RL = 150Ω to V−
0.0.6
0.23
%
4.43 MHz, 0.85V ≤ VOUT ≤ 2.45V
RL = 150Ω to V−
deg
Time Domain Response
TRS/TRL
OS
Rise & Fall Time
0.25V Step
2.7
10
ns
%
Overshoot
Slew Rate
Settling Time
0.25V Step
SR
2V Step
260
70
V/µs
TS
1V Step, 0.1%
1V Step, 0.02%
Input to Output, 250 mV Step, 50%
AV = −1, 10% Overshoot, 82Ω in
Series
ns
TS_1
PD
300
2.6
50
Propagation Delay
ns
CL
Cap Load Tolerance
pF
Distortion & Noise Performance
HD2
Harmonic Distortion (2nd
)
2 VPP, 10 MHz
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
2 VPP, 10 MHz
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
−61
−79
dBc
HD2_1
HD3
Harmonic Distortion (3rd)
−53
−69
dBc
dBc
HD3_2
THD
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
−66
>
VN1
VN2
IN
10 MHz
7
nV/
fA/
mV
1 MHz
10
50
>
1 MHz
Static, DC Performance
VIO
Input Offset Voltage
1
2.6
5.5
DVIO
Input Offset Voltage Average
Drift
(Note 8)
−4.5
µV/˚C
IB
Input Bias Current
Input Offset Current
Input Resistance
Input Capacitance
(Note 9)
(Note 9)
5
2
50
25
pA
pA
GΩ
pF
IOS
RIN
CIN
>
100
1.4
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4
3.3V Electrical Characteristics Single Supply with VS= 3.3V, AV = +2, RF = 604Ω, SD tied to V+,
VOUT = VS/2, RL = 150Ω to V− unless otherwise specified. Boldface limits apply at temperature extremes. (Note
2) (Continued)
Symbol
+PSRR
Parameter
Condition
Min
Typ
Max
Units
dB
(Note 6) (Note 6) (Note 6)
Positive Power Supply
Rejection Ratio
DC
DC
61
51
80
72
73
−PSRR
CMRR
Negative Power Supply
Rejection Ratio
57
dB
52
Common Mode Rejection Ratio DC
58
dB
55
V− -0.20
>
CMVR
ICC
Input Voltage Range
Supply Current
CMRR 50 dB
Normal Operation
VOUT = VS/2
–
V+ -1.5
11
V
9.2
mA
nA
13
Shutdown
100
SD tied to ≤ 0.33V (Note 5)
RL = 150Ω to V–
VOH1
Output High Voltage
(Relative to V+)
–210
–190
–360
VOH2
VOH3
RL = 75Ω to VS/2
RL = 10 kΩ to V−
–190
–10
mV
mV
–50
–100
VOL1
Output Low Voltage
(Relative to V–)
RL = 150Ω to V–
+4
+45
+125
VOL2
VOL3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
+105
+4
+45
+125
<
IO
Output Current
VOUT 0.6V from
Source
Sink
50
75
Respective Supply
mA
IO_1
Load
VOUT = VS/2, VID
(Note 10)
=
18 mV
75
<
Output Load Rating
THD −30 dBc, f = 200 kHz,
RL tied to VS/2, VOUT = 2.6 VPP
Enabled, AV = +1
25
Ω
RO_Enabled Output Resistance
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
Miscellaneous Performance
0.2
Ω
>
Shutdown
100
MΩ
pF
Shutdown
5.6
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5) (Note 5)
Voltage Limit for Enable (Pin 5) (Note 5)
0
0.33
3.3
V
V
2.97
Logic Input Current (Pin 5)
Turn-on Glitch
SD = 3.3V (Note 5)
8
pA
V
V_glitch
Ton
1.6
3.5
500
60
Turn-on Time
µs
ns
dB
Toff
Turn-off Time
IsolationOFF Off Isolation
1 MHz, RL = 1 kΩ
5
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2.7V Electrical Characteristics Single Supply with VS = 2.7V, AV = +2, RF = 604Ω, SD tied to V+, VOUT
= VS/2, RL = 150Ω to V− unless otherwise specified. Boldface limits apply at temperature extremes. (Note 2)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 6) (Note 6) (Note 6)
Frequency Domain Response
SSBW
SSBW_1
Peak
–3 dB Bandwidth Small Signal VOUT = 0.25 VPP
120
250
3.1
0.1
73
MHz
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
Peaking
Peaking
dB
dB
Peak_1
LSBW
–3 dB Bandwidth Large Signal VOUT = 2 V
MHz
dB
PP
Peak_2
Peaking
VOUT = 2 VPP
0
0.1 dB BW 0.1 dB Bandwidth
VOUT = 2VPP
30
MHz
GBWP_1k
GBWP_150
AVOL
Gain Bandwidth Product
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150Ω to VS/2
110
81
MHz
<
<
Large Signal Open Loop Gain 0.25V VOUT 2.5V
56
65
13
dB
PBW
Full Power BW
Differential Gain
Differential Phase
–1 dB, AV = +4, VOUT = 2 VPP
RL = 150Ω to VS/2
,
MHz
DG
DP
4.43 MHz, 0.45V ≤ VOUT ≤ 2.05V
RL = 150Ω to V−
0.12
0.62
%
4.43 MHz, 0.45V ≤ VOUT ≤ 2.05V
RL = 150Ω to V−
deg
Time Domain Response
TRS/TRL
OS
Rise & Fall Time
0.25V Step
2.7
10
ns
%
Overshoot
Slew Rate
Settling Time
0.25V Step
SR
2V Step
260
147
410
3.4
V/µs
TS
1V Step, 0.1%
1V Step, 0.02%
Input to Output, 250 mV Step, 50%
ns
ns
TS_1
PD
Propagation Delay
Distortion & Noise Performance
HD2
HD3
VN1
VN2
IN
Harmonic Distortion (2nd
Harmonic Distortion (3rd)
)
1 VPP, 10 MHz
1 VPP, 10 MHz
−58
−60
8.4
12
dBc
dBc
>
Input Voltage Noise
10 MHz
1 MHz
nV/
fA/
>
Input Current Noise
1 MHz
50
Static, DC Performance
VIO
Input Offset Voltage
1
3.5
mV
6.5
DVIO
Input Offset Voltage Average
Drift
(Note 8)
−6.5
µV/˚C
IB
Input Bias Current
Input Offset Current
Input Resistance
Input Capacitance
Positive Power Supply
Rejection Ratio
(Note 9)
(Note 9)
5
2
50
pA
pA
GΩ
pF
IOS
25
>
RIN
100
1.6
68
CIN
+PSRR
DC
DC
58
53
dB
−PSRR
CMRR
CMVR
Negative Power Supply
Rejection Ratio
56
69
77
–
dB
dB
53
Common Mode Rejection Ratio DC
Input Voltage Range CMRR 50 dB
57
52
V− -0.20
V+ -1.5
V
>
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6
2.7V Electrical Characteristics Single Supply with VS = 2.7V, AV = +2, RF = 604Ω, SD tied to V+, VOUT
=
VS/2, RL = 150Ω to V− unless otherwise specified. Boldface limits apply at temperature extremes. (Note 2) (Continued)
Symbol
ICC
Parameter
Supply Current
Condition
Min
Typ
Max
Units
(Note 6) (Note 6) (Note 6)
Normal Operation
9.0
100
10.6
mA
nA
VOUT = VS/2
12.5
Shutdown
SD tied to ≤ 0.27V (Note 5)
RL = 150Ω to V–
VOH1
Output High Voltage
(Relative to V+)
–260
–200
–420
VOH2
VOH3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
–200
–10
mV
mV
–50
100
VOL1
Output Low Voltage
(Relative to V–)
RL = 150Ω to V–
+4
+45
+125
VOL2
VOL3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
+125
+4
+45
125
IO
Output Current
VOUT ≤ 0.6V from
Respective Supply
Source
Sink
25
62
mA
IO_1
Load
VOUT = VS/2, VID
mV (Note 10)
=
18
Source
Sink
25
35
<
Output Load Rating
THD −30 dBc, f = 200 kHz, RL tied
to VS/2, VOUT = 2.2 VPP
Enabled, AV = +1
40
Ω
RO_Enable Output Resistance
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
Miscellaneous Performance
0.2
Ω
>
Shutdown
100
MΩ
pF
Shutdown
5.6
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5) (Note 5)
Voltage Limit for Enable (Pin 5) (Note 5)
0
0.27
2.7
V
V
2.43
Logic Input Current (Pin 5)
Turn-on Glitch
SD = 2.7V (Note 5)
4
pA
V
V_glitch
Ton
1.2
5.2
760
60
Turn-on Time
µs
ns
dB
Toff
Turn-off Time
IsolationOFF Off Isolation
1 MHz, RL = 1 kΩ
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of
>
the device such that T = T . No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where T
T .
J
A
J
A
Note 3: The maximum continuous output current (I
) is determined by device power dissipation limitations.
OUT
Note 4: Human Body Model is 1.5 kΩ in series with 100 pF. Machine Model is 0Ω in series with 200 pF.
Note 5: SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10% of total supply
voltage away from either supply rail.
Note 6: Typical numbers are the most likely parametric norm. Bold numbers refer to over temperature limits.
Note 7: Negative input current implies current flowing out of the device.
Note 8: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Note 9: Guaranteed by design.
Note 10: “V ” is input differential voltage (input overdrive).
ID
7
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Connection Diagram
6-Pin SC70
20136401
Top View
Ordering Information
Package
Part Number
LMH6601MG
LMH6601MGX
Package Marking
Transport Media
NSC Drawing
1k Units Tape and Reel
3k Units Tape and Reel
6-Pin SC70
A95
MAA06A
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8
Typical Performance Characteristics Unless otherwise noted, all data is with AV = +2, RF = RG
=
604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T = 25˚C.
Frequency Response for Various Output Amplitudes
Frequency Response for Various Output Amplitudes
20136414
20136413
Frequency Response for Various Output Amplitudes
−3 dB BW vs. Supply Voltage for Various Output Swings
20136420
20136415
Non-inverting Frequency Response for Various Gain
Inverting Frequency Response for Various Gain
20136416
20136417
9
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Typical Performance Characteristics Unless otherwise noted, all data is with AV = +2, RF = RG
=
604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T = 25˚C. (Continued)
Frequency Response for Various Loads
Frequency Response for Various Supply Voltages
20136419
20136421
−3 dB BW vs. Ambient Temperature
Frequency Response for Various Cap Load
20136422
20136418
Frequency Response for Various Supply Voltage
Max Output Swing vs. Frequency
20136426
20136441
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10
Typical Performance Characteristics Unless otherwise noted, all data is with AV = +2, RF = RG
=
604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T = 25˚C. (Continued)
Output Swing vs. Sink Current for Various Supply
Voltages
Peak Output Swing vs. RL
20136427
20136464
Output Swing vs. Source Current for Various Supply
Voltages
HD2 vs. Frequency
20136404
20136465
HD3 vs. Frequency
THD vs. Output Swing
20136405
20136402
11
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Typical Performance Characteristics Unless otherwise noted, all data is with AV = +2, RF = RG
=
604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T = 25˚C. (Continued)
THD vs. Output Swing
Slew Rate vs. Ambient Temperature
20136423
20136403
Settling Time ( 1%) vs. Output Swing
Output Settling
20136412
20136411
Isolation Resistor & Settling Time vs. CL
Isolation Resistor & Settling Time vs. CL
20136429
20136428
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12
Typical Performance Characteristics Unless otherwise noted, all data is with AV = +2, RF = RG
=
604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T = 25˚C. (Continued)
Closed Loop Output Impedance vs. Frequency for
Various Supply Voltages
Off Isolation vs. Frequency
20136410
20136408
Noise Voltage vs. Frequency
Open Loop Gain/ Phase
20136435
20136424
CMRR vs. Frequency
+PSRR vs. Frequency
20136425
20136439
13
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Typical Performance Characteristics Unless otherwise noted, all data is with AV = +2, RF = RG
=
604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T = 25˚C. (Continued)
−PSRR vs. Frequency
Supply Current vs. Ambient Temperature
20136433
20136440
Supply Current vs. VCM
Supply Current vs. Supply Voltage
20136437
20136467
Offset Voltage vs. Ambient Temperature
for 3 Representative Units
Offset Voltage Distribution
20136434
20136436
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14
Typical Performance Characteristics Unless otherwise noted, all data is with AV = +2, RF = RG
=
604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T = 25˚C. (Continued)
Offset Voltage vs. VCM (Typical Part)
Input Bias Current vs. Common Mode Voltage
20136438
20136442
Small Signal Step Response
Large Signal Step Response
20136430
20136431
Large Signal Step Response
Turn On/Off Waveform
20136466
20136432
15
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Typical Performance Characteristics Unless otherwise noted, all data is with AV = +2, RF = RG
=
604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T = 25˚C. (Continued)
DG vs. VOUT for Various VS
DP vs. VOUT for Various VS
20136472
20136471
DG vs. VOUT (DC and AC Coupled Load Compared)
DP vs. VOUT (DC and AC Coupled Load Compared)
20136473
20136474
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16
Application Information
OPTIMIZING PERFORMANCE
With many op amps, additional device non-linearity and
sometimes less loop stability arises when the output has to
switch from current-source mode to current-sink mode or
vice versa. When it comes to achieving the lowest distortion
and the best Differential Gain/ Differential Phase (DG/ DP,
broadcast video specs), the LMH6601 is optimized for single
supply DC coupled output applications where the load cur-
rent is returned to the negative rail (V−). That is where the
output stage is most linear (lowest distortion) and which
corresponds to unipolar current flowing out of this device. To
that effect, it is easy to see that the distortion specifications
improve when the output is only sourcing current which is the
distortion-optimized mode of operation for the LMH6601. In
application where the LMH6601 output is AC coupled or
when it is powered by separate dual supplies for V+ and V−,
the output stage supplies both source and sink current to the
load and results in less than optimum distortion (and DG/
DP). Figure 1 compares the distortion results between a DC
and an AC coupled load to show the magnitude of this
difference. See the DG/DP plots in the Typical Performance
Characteristics section for a comparison between DC and
AC coupling of the video load.
20136470
FIGURE 2. Output Pull-Down Value for Dual Supply &
AC Coupling
Furthermore, with a combination of low closed loop gain
setting (i.e. AV = +1 for example where device bandwidth is
>
the highest), light output loading (RL
1 kΩ) , and with a
>
significant capacitive load (CL
10 pF) , the LMH6601 is
most stable if output sink current is kept to less than about 5
mA. The pull-down method described in Figure 2 is appli-
cable in these cases as well where the current that would
normally be sunk by the op amp is diverted to the RP path
instead.
SHUTDOWN CAPABILITY AND TURN ON/ OFF
BEHAVIOR
With the device in shutdown mode, the output goes into high
>
impedance (ROUT 100 MΩ) mode. In this mode, the only
path between the inputs and the output pin is through the
external components around the device. So, for applications
where there is active signal connection to the inverting input,
with the LMH6601 in shutdown, the output could show signal
swings due to current flow through these external compo-
nents. For non-inverting amplifiers in shutdown, no output
swings would occur, because of complete input-output iso-
lation, with the exception of capacitive coupling.
20136406
FIGURE 1. Distortion Comparison between DC & AC
Coupling of the Load
For maximum power saving, the LMH6601 supply current
drops to around 0.1 µA in shutdown. All significant power
consumption within the device is disabled for this purpose.
Because of this, the LMH6601 turn on time is measured in
micro-seconds whereas its turn off is fast (nano-seconds) as
would be expected from a high speed device like this.
In certain applications, it may be possible to optimize the
LMH6601 for best distortion (and DG/DP) even though the
load may require bipolar output current by adding a pull-
down resistor to the output. Adding an output pull-down
resistance of appropriate value could change the LMH6601
output loading into source-only. This comes at the price of
higher total power dissipation and increased output current
requirement.
The LMH6601 SD pin is a CMOS compatible input with a
pico-ampere range input current drive requirement. This pin
needs to be tied to a level or otherwise the device state
would be indeterminate. The device shutdown threshold is
half way between the V+ and V− pin potentials at any supply
voltage. For example, with V+ tied to 10V and V− equal to 5V,
you can expect the threshold to be at 7.5V. The state of the
device (shutdown or normal operation) is guaranteed over
temperature as longs as the SD pin is held to within 10% of
the total supply voltage.
Figure 2 shows how to calculate the pull-down resistor value
for both the dual supply and for the AC coupled load appli-
cations.
For V+ = 10V, V− = 5V, as an example:
•
•
Shutdown Range
5V ≤ SD ≤ 5.5V
9.5V ≤ SD ≤ 10V
Normal Operation Range
17
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With some op amps, when the output approaches either one
or both rails and saturation starts to set in, there is significant
increase in the transistor parasitic capacitances which leads
to loss of Phase Margin. That is why with these devices,
there are sometimes hints of instability with output close to
the rails. With the LMH6601, as can be seen in Figure 4, the
output waveform remains free of instability throughout its
range of voltages.
Application Information (Continued)
OVERLOAD RECOVERY AND SWING CLOSE TO RAILS
The LMH6601 can recover from an output overload in less
than 20 ns. See Figure 3 below for the input and output
scope photos:
SINGLE SUPPLY VIDEO APPLICATION
The LMH6601’s high speed and fast slew rate make it an
ideal choice for video amplifier and buffering applications.
There are cost benefits in having a single operating supply.
Single supply video systems can take advantage of the
LMH6601’s low supply voltage operation along with its ability
to operate with input common mode voltages at or slightly
below the V− rail. Additional cost savings can be achieved by
eliminating or reducing the value of the input and output AC
coupling capacitors commonly employed in single supply
video applications. This Application section shows some
circuit techniques used to help in doing just that.
DC COUPLED, SINGLE SUPPLY BASEBAND VIDEO
AMPLIFIER/DRIVER
20136407
The LMH6601 output can swing very close to either rail to
maximize the output dynamic range which is of particular
interest when operating in a low voltage single supply envi-
ronment. Under light output load conditions, the output can
swing as close as a few milli-volts of either rail. This also
allows a video amplifier to preserve the video black level for
excellent video integrity. In the example shown below in
Figure 5, the baseband video output is amplified and buff-
ered by the LMH6601 which then drives the 75Ω back ter-
minated video cable for an overall gain of +1 delivered to the
75Ω load. The input video would normally have a level
between 0V to approximately 0.75V.
FIGURE 3. LMH6601 Output Overload Recovery
Waveform
In Figure 3, the input step function is set so that the output is
driven to one rail and then the other and then the output
recovery is measured from the time the input crosses 0V to
when the output reaches this point.
Also, when the LMH6601 input voltage range is exceeded
near the V+ rail, the output does not experience output phase
reversal, as some op amps do. This is particularly advanta-
geous in applications where output phase reversal has to be
avoided at all costs, such as in servo loop control among
others. This adds to the LMH6601’s set of features which
make this device easy to use.
In addition, the LMH6601’s output swing close to either rail is
well-behaved as can be seen in the scope photo of Figure 4.
20136444
FIGURE 5. Single Supply Video Driver Capable of
Maintaining Accurate Video Black Level
20136443
FIGURE 4. LMH6601’s “Clean” Swing to Either Rail
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18
Application Information (Continued)
With the LMH6601 input common mode range including the
V− (ground) rail, there will be no need for AC coupling or
level shifting and the input can directly drive the non-
inverting input which has the additional advantage of high
amplifier input impedance. With LMH6601’s wide rail-to-rail
output swing, as stated earlier, the video black level of 0V is
maintained at the load with minimal circuit complexity and
using no AC coupling capacitors. Without true rail-to-rail
output swing of the LMH6601, and more importantly without
the LMH6601’s ability of exceedingly close swing to V−, the
circuit would not operate properly as shown at the expense
of more complexity. This circuit will also work for higher input
voltages. The only significant requirement is that there is at
least 1.8V from the maximum input voltage to the positive
supply (V+).
20136446
FIGURE 7. Single Supply DC Coupled Composite
The Composite Video Output of some low cost consumer
video equipment consists of a current source which devel-
ops the video waveform across a load resistor (usually 75Ω),
as shown in Figure 6 below. With these applications, the
same circuit configuration just described and shown in Fig-
ure 6 will be able to buffer and drive the Composite Video
waveform which includes sync and video combined. How-
ever, with this arrangement, the LMH6601 supply voltage
needs to be at least 3.3V or higher in order to allow proper
input common mode voltage headroom because the input
can be as high as 1V peak.
Video Driver for Negative Going Sync Tip
In the circuit of Figure 7, the input is shifted positive by
means of R1, R2, and RT in order to satisfy U1’s Common
Mode input range. The signal will loose 20% of its amplitude
in the process. The closed loop gain of U1 will need to be set
to make up for this 20% loss in amplitude. This gives rise to
the gain expression shown below which is based on a get-
ting a 2 VPP output with a 0.8 VPP input:
(1)
R3 will produce a negative shift at the output due to VS (3.3V
in this case). R3 will need to be set so that the “Video In” sync
tip (−0.3V at RT or 0.61V at U1 non-inverting input) corre-
sponds to near 0V at the output.
(2)
Equation (1) and Equation (2) need to be solved simulta-
neously to arrive at the values of R3, RF, and RG which will
satisfy both. From the datasheet, one can set RF = 620Ω to
be close to the recommended value for a gain of +2. It is
easier to solve for RG and R3 by starting with a good esti-
mate for one and iteratively solving Equation and Equation
(2) to arrive at the results. Here is one possible iteration
cycle for reference:
20136445
FIGURE 6. Single Supply Composite Video Driver for
Consumer Video Outputs
If the “Video In” signal is Composite Video with negative
going Sync tip, a variation of the previous configurations
should be used. This circuit produces a unipolar (above 0V)
DC coupled single supply video signal as shown in Figure 7.
19
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RF = 620Ω
TABLE 1. Finding Figure 7 External Resistor Values by Iteration
Application Information (Continued)
Estimate
Calculated
Equation (1) LHS
Comment
RG (Ω)
(from Equation (2))
Calculated
(Compare Equation (1) LHS Calculated to
RHS)
R3 (Ω)
1.69k
1.56k
1.37k
239
1k
0.988
1.15
1.45
4.18
1.59
Increase Equation (1) LHS by reducing RG
Increase Equation (1) LHS by reducing RG
Increase Equation (1) LHS by reducing RG
Reduce Equation (1) LHS by increasing RG
Close to target value of 1.5V/V for Equation (1)
820
620
390
560
1.30k
The final set of values for RG and R3 in Table 1 are values
which will result in the proper gain and correct video levels
(0V to 1V) at the output (VLOAD).
Because of the DC bias at the output, the load needs to be
AC coupled as well through CO. Some applications imple-
ment a small valued ceramic capacitor (not shown) in paral-
lel with CO which is electrolytic. The reason for this is that the
ceramic capacitor will tend to shunt the inductive behavior of
the Electrolytic capacitor at higher frequencies for an im-
proved overall low impedance output.
AC COUPLED VIDEO
Many monitors and displays accept AC coupled inputs. This
simplifies the amplification and buffering task in some re-
spects. As can be seen in Figure 8, R1 and R2 simply set the
input to the center of the input linear range while CIN AC
couples the video onto the op amp’s input. The op amp is set
for a closed loop gain of 2 with RF and RG. CG is there to
make sure the device output is also biased at mid-supply.
CG2 is intended to boost the high frequency gain in order to
improve the video frequency response. This value is to be
set and trimmed on the board to meet the application’s
specific system requirements.
20136449
FIGURE 8. AC Coupled Video Amplifier/Driver
SAG COMPENSATION
coupling scheme due to the low frequency limit of this circuit.
The −3 dB low frequency limit of the output circuit is given
by:
The capacitors shown in Figure 8 (except CG2), and espe-
cially CO, are the large electrolytic type which are consider-
ably costly and take up valuable real estate on the board. It
is possible to reduce the value of the output coupling capaci-
tor, CO, which is the largest of all, by using what is called
SAG compensation. SAG refers to what the output video
experiences due to the low frequency video content it con-
tains which cannot adequately go through the output AC
f_low_frequency (−3 dB)= 1/ (2*pi* 75*2(Ω) * CO)
= ∼ 4.82 Hz For CO = 220 µF
(3)
A possible implementation of the SAG compensation is
shown in Figure 9.
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20
Application Information (Continued)
20136450
FIGURE 9. AC Coupled Video Amplifier/Driver with SAG Compensation
In this circuit, the output coupling capacitor value and size is
greatly reduced at the expense of slightly higher op amp
output voltage drive. Note that C1 is not only part of the SAG
compensation, but it also sets the amplifier’s DC gain to 0 dB
so that the output is set to mid-rail for linearity purposes. Also
note that exceptionally high values are chosen for the R1 and
R2 biasing resistors (510 kΩ). The LMH6601 has extremely
low input bias current which allows this selection thereby
reducing the CIN value in this circuit such that CIN can even
be a non-polar capacitors which will reduce cost.
At high enough frequencies where both CO and C1 can be
considered to be shorted out, R3 shunts R4 and the closed
loop gain is determined by:
Closed_loop_Gain (V/V)= VL/VIN = (1+ (R3||R4)/ R5)
[RL/(RL+RO)]= 1V/V
(4)
At intermediate frequencies, where the CO, RO, RL path
experiences low frequency gain loss, the R3, R5, C1 path
provides feedback from the load side of CO. With the load
side gain reduced at these lower frequencies, the feedback
to the op amp inverting node reduces, causing an increase
at the op amp’s output as a response.
For NTSC video, low values of CO influence how much video
black level shift occurs during the vertical blanking interval
(∼1.5 ms) which has no video activity and thus is sensitive to
CO’s charge dissipation through the load which could cause
output SAG. An especially tough pattern is the NTSC pattern
called “Pulse & Bar.” With this pattern the entire top and
bottom portion of the field is black level video where for
about 8.5 ms CO is discharging through the load with no
video activity to replenish that charge.
20136451
FIGURE 10. Figure 9 Scope Photo Showing Video SAG
There is a subtlety with the additional output drive in the SAG
correction circuit, compared to a circuit with no SAG com-
pensation, especially when using lower power supply volt-
ages. This will be explained later after a brief introduction,
below, on the effects of AC coupling on output swing.
Figure 10 shows the output of the Figure 9 circuit with the
scope’s cursors pointing to the SAG.
With the circuit of Figure 9 and any other AC coupled pulse
amplifier, the waveform duty cycle variations exert additional
restrictions on voltage swing at any node. This is illustrated
in the waveforms shown in Figure 11.
21
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Application Information (Continued)
20136452
FIGURE 11. Headroom Considerations with AC Coupled Amplifiers
If a stage has a 3 VPP unclipped swing available at a given
node, as shown in Figure 11, the maximum allowable ampli-
tude for an arbitrary waveform is 1⁄
of 3V or 1.5 VPP. This is
2
due to the shift in the average value of the waveform as the
duty cycle varies. Figure 11 shows what would happen if a
2 VPP signal were applied. A low duty cycle waveform, such
as the one in Figure 11B, would have high positive excur-
sions. At low enough duty cycles, the waveform could get
clipped on the top, as shown, or a more subtle loss of
linearity could occur prior to full-blown clipping. The con-
verse of this occurs with high duty cycle waveforms and
negative clipping, as depicted in Figure 11C.
Now, let’s get back to discussing the SAG compensation
output swing subtlety hinted at earlier. For the Figure 9
circuit, with a 1 VPP Composite Video input, the op amp
output will swing 2 VPP because the stage gain is set to 2
V/V. With the output set to VCC/2 (2.5V in this case), the op
amp output voltage will range from 0.5V to 4.5V, assuming
video duty cycle variation of 100% to 0% respectively. In
reality, the duty cycle only approaches these extreme end
points and it never quite gets there. Figure 12 shows the
measured response of this circuit to show the worst case
swing at the op amp output pin. Note that the extra output
drive at the op amp output for SAG compensation, which
shows up as a tilt in the upper video waveform, could cause
clipping as the output swings even closer to the rails.
20136453
FIGURE 12. SAG Compensation Requires Higher
Swing at op amp Output
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22
sheet tables) as video signals could be as large as 2 VPP
when applied to the commonly used gain of +2 configuration.
Because of this relatively large swing, the op amp Slew Rate
(SR) limitation should also be considered. Table 2 shows
these requirements for various video line rates calculated
using a rudimentary technique and intended as a first order
estimate only.
Application Information (Continued)
HOW TO PICK THE RIGHT VIDEO AMPLIFIER
Apart from output current drive and voltage swing, the op
amp used for a video amplifier/cable driver should also
possess the minimum requirement for speed and slew rate.
For video type loads, it is best to consider Large Signal
Bandwidth (or LSBW in the National Semiconductor data
TABLE 2. Rise Time, −3 dB BW, and Slew Rate Requirements for Various Video Line Rates
Video
Standard
TV_NTSC
VGA
Line Rate
(HxV)
Refresh Rate
Horizontal
Active (KH%) Active (KV%)
Vertical
Pixel Time Rise Time LSBW
SR
(V/µs)
41
(Hz)
30
75
75
75
75
75
(ns)
118.3
33.0
20.3
12.4
7.3
(ns)
39.4
11.0
6.8
(MHz)
9
451x483
640x480
800x600
1024x768
1280x1024
1600x1200
84
80
76
77
75
74
92
95
96
95
96
96
32
146
237
387
655
973
SVGA
52
XGA
4.1
85
SXGA
2.4
143
213
UXGA
4.9
1.6
For any video line rate (HxV corresponding to the number of
Active horizontal and vertical lines), the speed requirements
can be estimated if the Horizontal Active (KH%) and Vertical
Active (KV%) numbers are known. These percentages cor-
respond to the percentages of the active number of lines
(horizontal or vertical) to the total number of lines as set by
VESA standards. Here are the general expressions and the
specific calculations for the SVGA line rate shown in Table 2.
The LMH6601 specifications show that it would be a suitable
choice for video amplifiers up to and including the SVGA line
rate as demonstrated above.
For more information about this topic and others relating to
video amplifiers, please see Application Note 1013:
http://www.national.com/an/AN/AN-1013.pdf#page=1
CURRENT TO VOLTAGE CONVERSION
(TRANSIMPEDANCE AMPLIFIER (TIA))
Being capable of high speed and having ultra low input bias
current makes the LMH6601 a natural choice for Current to
Voltage applications such as photodiode I-V conversion. In
these type of applications, as shown in Figure 13 below, the
photodiode is tied to the inverting input of the amplifier with
RF set to the proper gain (gain is measured in Ohms).
(5)
Requiring that an “On” pixel is illuminated to at least 90% of
its final value before changing state will result in the rise/fall
1
time equal to, at most,
⁄3 the pixel time as shown below:
(6)
Assuming a single pole frequency response roll-off charac-
teristic for the closed loop amplifier used, we have:
(7)
20136458
Rise/Fall times are 10%-90% transition times, which for a 2
VPP video step would correspond to a total voltage shift of
1.6V (80% of 2V). So, the Slew Rate requirement can be
calculated as follows:
FIGURE 13. Typical Connection of a Photodiode
Detector to an op amp
(8)
23
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Application Information (Continued)
With the LMH6601 input bias current in the femto-amperes
range, even large values of gain (RF) do not increase the
output error term appreciably. This allows circuit operation to
a lower light intensity level which is always of special impor-
tance in these applications. Most photo-diodes have a rela-
tively large capacitance (CD) which would be even larger for
a photo-diode designed for higher sensitivity to light because
of its larger area. Some applications may run the photodiode
with a reverse bias in order to reduce its capacitance with the
disadvantage of increased contributions from both dark cur-
rent and noise current. Figure 14 shows a typical photodiode
capacitance plot vs. reverse bias for reference.
20136460
FIGURE 15. Transimpedance Amplifier Graphical
Stability Analysis and Compensation
Figure 15 shows that placing a capacitor, CF, with the proper
value, across RF will create a pole in the NG function at fP.
For optimum performance, this capacitor is usually picked so
that NG is equal to the op amp’s open loop gain at fP. This
will cause a “flattening” of the NG slope beyond the point of
intercept of the two plots (open loop gain and NG) and will
results in a Phase Margin (PM) of 45˚ assuming fP and fZ are
at least a decade apart. This is because at the point of
intercept, the NG pole at fP will have a 45˚ phase lead
contribution which leaves 45˚ of PM. For reference, Figure
15 also shows the transimpedance gain (I-V (Ω))
20136459
FIGURE 14. Typical Capacitance vs. Reverse Bias
(Source: OSI Optoelectronics)
The diode capacitance (CD) along with the input capacitance
of the LMH6601 (CA) has a bearing on the stability of this
circuit and how it is compensated. With large transimped-
ance gain values (RF), the total combined capacitance on
the amplifier inverting input (CIN = CD + CA) will work against
RF to create a zero in the Noise Gain (NG) function (see
Figure 15). If left untreated, at higher frequencies where NG
equals the open loop transfer function there will be excess
phase shift around the loop (approaching 180˚) and there-
fore, the circuit could be unstable. This is illustrated in Figure
15.
Here is the theoretical expression for the optimum CF value
and the expected −3 dB bandwidth:
(9)
(10)
Table 3, below, lists the results, along with the assumptions
and conditions, of testing the LMH6601 with various photo-
diodes having different capacitances (CD) at a transimped-
ance gain (RF) of 10 kΩ.
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24
Application Information (Continued)
TABLE 3. Transimpedance Amplifier Figure 13 Compensation and Performance Results
CD
(pF)
10
CIN
(pF)
12
CF_Calculated
CF used
(pF)
1
−3 dB BW
−3 dB BW
Step Response
(pF)
1.1
2.3
7.2
Calculated (MHz) Measured (MHz) Overshoot (%)
14
7
15
7.0
2.5
6
4
9
50
52
3
500
502
8
2
CA = 2 pF
CAPACITIVE LOAD
GBWP = 155 MHz
VS = 5V
The LMH6601 can drive a capacitive load of up to 1000 pF
with correct isolation and compensation. Figure 17 illustrates
the in-loop compensation technique to drive a large capaci-
tive load.
TRANSIMPEDANCE AMPLIFIER NOISE
CONSIDERATIONS
When analyzing the noise at the output of the I-V converter,
it is important to note that the various noise sources (i.e. op
amp noise voltage, feedback resistor thermal noise, input
noise current, photodiode noise current) do not all operate
over the same frequency band. Therefore, when the noise at
the output is calculated, this should be taken into account.
The op amp noise voltage will be gained up in the region
between the noise gain’s “zero” and its “pole” (fz and fp in
Figure 15). The higher the values of RF and CIN, the sooner
the noise gain peaking starts and therefore its contribution to
the total output noise would be larger. It is obvious to note
that it is advantageous to minimize CIN (e.g. by proper
choice of op amp, by applying a reverse bias across the
diode at the expense of excess dark current and noise).
However, most low noise op amps have a higher input
capacitance compared to ordinary op amps. This is due to
the low noise op amp’s larger input stage.
20136468
FIGURE 17. In-Loop Compensation Circuit for Driving
a Heavy Capacitive Load
When driving a high capacitive load, an isolation resistor
(RS) should be connected in series between the op amp
output and the capacitive load to provide isolation and to
avoid oscillations. A small value capacitor (CF) is inserted
between the op amp output and the inverting input as shown
such that this capacitor becomes the dominant feedback
path at higher frequency. Together these components allow
heavy capacitive loading while keeping the loop stable.
OTHER APPLICATIONS
There are few factors which affect the driving capability of
the op amp:
•
•
Op amp internal architecture
Closed loop gain and output capacitor loading
Table 4 shows the measured step response for various
values of load capacitors (CL), series resistor (RS) and feed-
back resistor (CF) with gain of +2 (RF = RG = 604Ω) and RL
= 2 kΩ:
TABLE 4. LMH6601 Step Response Summary for the
Circuit of Figure 17
CL
(pF)
10
RS
(Ω)
0
CF
(pF)
1
t
rise/ tfall
(ns)
6*
Overshoot
(%)
8
20136463
50
0
1
7*
6
110
300
500
910
47
6
1
10
16
20
10
10
FIGURE 16. Charge Preamplifier Taking Advantage of
LMH6601’s Femto-Ampere Range Input Bias Current
10
10
10
12
80
192
33
65
* Response limited by input step generator rise time of 5 ns
25
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Application Information (Continued)
EVALUATION BOARD
Figure 18 shows the increase in rise/fall time (bandwidth
decrease) at VOUT with larger capacitive loads, illustrating
the trade-off between the two:
National Semiconductor provides the following evaluation
board as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the datasheet
plots were measured with this board:
Device
Package
Board Part #
LMH6601MG
SC70-6
LMH730165
This evaluation board can be shipped when a device sample
request is placed with National Semiconductor.
20136469
FIGURE 18. LMH6601 In-Loop Compensation
Response
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26
Physical Dimensions inches (millimeters) unless otherwise noted
6-Pin SC70
NS Package Number MA006A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor follows the provisions of the Product Stewardship Guide for Customers (CSP-9-111C2) and Banned Substances
and Materials of Interest Specification (CSP-9-111S2) for regulatory environmental compliance. Details may be found at:
www.national.com/quality/green.
Lead free products are RoHS compliant.
National Semiconductor
Americas Customer
Support Center
National Semiconductor
Europe Customer Support Center
Fax: +49 (0) 180-530 85 86
National Semiconductor
Asia Pacific Customer
Support Center
National Semiconductor
Japan Customer Support Center
Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
Tel: 1-800-272-9959
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
Email: ap.support@nsc.com
Email: jpn.feedback@nsc.com
Tel: 81-3-5639-7560
www.national.com
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