LMH6601Q [NSC]
250 MHz, 2.4V CMOS Operational Amplifier with Shutdown; 250兆赫， 2.4V CMOS具有关断运算放大器
| 型号： | LMH6601Q |
| 厂家： | 
National Semiconductor |
| 描述： | 250 MHz, 2.4V CMOS Operational Amplifier with Shutdown |
| 文件： | 总28页 (文件大小：1523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 9, 2009
LMH6601/LMH6601Q
250 MHz, 2.4V CMOS Operational Amplifier with Shutdown
General Description
Features
The LMH6601 is a low voltage (2.4V – 5.5V), high speed volt-
age feedback operational amplifier suitable for use in a variety
of consumer and industrial applications. With a bandwidth of
125 MHz at a gain of +2 and guaranteed high output current
of 100 mA, the LMH6601 is an ideal choice for video line driver
applications including HDTV. Low input bias current (50 pA
maximum), rail-to-rail output, and low current noise allow the
LMH6601 to be used in various industrial applications such
as transimpedance amplifiers, active filters, or high-
impedance buffers. The LMH6601 is an attractive solution for
systems which require high performance at low supply volt-
ages. The LMH6601 is available in a 6-pin SC70 package,
and includes a micropower shutdown feature.
VS = 3.3V, TA = 25°C, AV = 2 V/V, RL = 150Ω to V−, unless
specified.
125 MHz −3 dB small signal bandwidth
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■
■
■
■
■
■
■
■
75 MHz −3 dB large signal bandwidth
30 MHz large signal 0.1 dB gain flatness
260 V/μs slew rate
0.25%/0.25° differential gain/differential phase
Rail-to-rail output
2.4V – 5.5V single supply operating range
6-Pin SC70 Package
LMH6601Q is AEC-Q100 grade 3 qualified and is
manufactured on an automotive grade flow
Applications
Video amplifier
■
■
■
■
■
■
■
■
Charge amplifier
Set-top box
Sample & hold
Transimpedance amplifier
Line driver
High impedance buffer
Automotive
Response at a Gain of +2 for Various Supply Voltages
20136441
© 2009 National Semiconductor Corporation
201364
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Storage Temperature Range
Junction Temperature
Soldering Information
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
−65°C to +150°C
+150°C
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
235°C
260°C
ESD Tolerance (Note 4)
Human Body Model
Machine Model
VIN Differential
2 kV
200V
Operating Ratings (Note 1)
Supply Voltage (V+ – V−)
2.4V to 5.5V
−40°C to +85°C
±2.5V
±10 mA
Operating Temperature Range
Input Current
Package Thermal Resistance (θJA
)
Output Current
200 mA (Note 3)
Supply Voltage (V+ – V−)
6-pin SC70
414°C/W
6.0V
Voltage at Input/Output Pins
V++0.5V, V−−0.5V
5V Electrical Characteristics Single Supply with VS= 5V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2,
RL = 150Ω to V− unless otherwise specified. Boldface limits apply at temperature extremes. (Note 2)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 6) (Note 6) (Note 6)
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
VOUT = 0.25 VPP
130
250
2.5
0
MHz
SSBW_1
Peak
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
Peaking
dB
dB
Peak_1
LSBW
Peaking
–3 dB Bandwidth Large Signal
Peaking
VOUT = 2 VPP
81
MHz
dB
Peak_2
0.1 dB BW
GBWP_1k
GBWP_150
AVOL
VOUT = 2 VPP
0
0.1 dB Bandwidth
Gain Bandwidth Product
VOUT = 2 VPP
30
MHz
155
125
Unity Gain, RL = 1 kΩ to VS/2
MHz
Unity Gain, RL = 150Ω to VS/2
0.5V < VOUT < 4.5V
Large Signal Open Loop Gain
Full Power BW
56
66
30
dB
PBW
–1 dB, AV = +4, VOUT = 4.2 VPP
,
MHz
RL = 150Ω to VS/2
DG
DP
Differential Gain
0.06
0.10
%
4.43 MHz, 1.7V ≤ VOUT ≤ 3.3V,
RL = 150Ω to V−
Differential Phase
deg
4.43 MHz, 1.7V ≤ VOUT ≤ 3.3V
RL = 150Ω to V−
Time Domain Response
TRS/TRL
OS
Rise & Fall Time
0.25V Step
2.6
10
ns
%
Overshoot
Slew Rate
Settling Time
0.25V Step
SR
2V Step
275
50
V/μs
TS
1V Step, ±0.1%
ns
TS_1
PD
1V Step, ±0.02%
220
2.4
50
Propagation Delay
Input to Output, 250 mV Step, 50%
AV = −1, 10% Overshoot, 75Ω in Series
ns
CL
Cap Load Tolerance
pF
Distortion & Noise Performance
HD2
Harmonic Distortion (2nd)
Harmonic Distortion (3rd)
2 VPP, 10 MHz
−56
−61
−73
−64
−58
7
dBc
dBc
HD2_1
HD3
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
2 VPP, 10 MHz
HD3_1
THD
VN1
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
>10 MHz
Total Harmonic Distortion
Input Voltage Noise
nV/
VN2
1 MHz
10
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2
Symbol
Parameter
Condition
Min
Typ
Max
Units
fA/
(Note 6) (Note 6) (Note 6)
IN
Input Current Noise
>1 MHz
50
Static, DC Performance
VIO
Input Offset Voltage
±1
±2.4
mV
±5.0
DVIO
IB
Input Offset Voltage Average Drift (Note 8)
−5
5
μV/°C
pA
Input Bias Current
Input Offset Current
Input Resistance
(Note 9)
(Note 9)
50
25
IOS
RIN
2
pA
10
TΩ
pF
dB
0V ≤ VIN ≤ 3.5V
CIN
Input Capacitance
1.3
59
+PSRR
Positive Power Supply Rejection DC
Ratio
55
51
−PSRR
CMRR
Negative Power Supply Rejection DC
Ratio
53
50
61
68
dB
dB
Common Mode Rejection Ratio
DC
56
53
CMVR
ICC
Input Voltage Range
Supply Current
CMRR > 50 dB
V− -0.20
V+ - 1.5
V
–
9.6
Normal Operation
VOUT = VS/2
11.5
13.5
mA
nA
Shutdown
100
SD tied to ≤ 0.5V (Note 5)
RL = 150Ω to V–
VOH1
Output High Voltage
(Relative to V+)
–210
–480
–190
VOH2
VOH3
–190
–12
RL = 75Ω to VS/2
RL = 10 kΩ to V–
mV
mV
–60
–110
RL = 150Ω to V–
VOL1
Output Low Voltage
(Relative to V–)
+5
+45
+125
VOL2
VOL3
+120
+5
RL = 75Ω to VS/2
RL = 10 kΩ to V–
+45
+125
IO
Output Current
VOUT < 0.6V from Respective Source
150
180
Supply
Sink
mA
IO_1
Load
VOUT = VS/2,
±100
VID = ±18 mV (Note 10)
Output Load Rating
THD < −30 dBc, f = 200 kHz,
RL tied to VS/2, VOUT = 4 VPP
20
Ω
RO_Enabled Output Resistance
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
Miscellaneous Performance
Enabled, AV = +1
Shutdown
0.2
>100
5.0
Ω
MΩ
pF
Shutdown
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5) (Note 5)
0
0.5
5.0
V
V
Voltage Limit for Enable (Pin 5)
Logic Input Current (Pin 5)
Turn-on Glitch
(Note 5)
4.5
SD = 5V (Note 5)
10
2.2
1.4
520
60
pA
V
V_glitch
Ton
Turn-on Time
µs
ns
dB
Toff
Turn-off Time
IsolationOFF Off Isolation
T_OL Overload Recovery
1 MHz, RL = 1 kΩ
<20
ns
3
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3.3V Electrical Characteristics Single Supply with VS= 3.3V, AV = +2, RF = 604Ω, SD tied to V+,
VOUT = VS/2, RL = 150Ω to V− unless otherwise specified. Boldface limits apply at temperature extremes. (Note 2)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 6) (Note 6) (Note 6)
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
VOUT = 0.25 VPP
125
250
3
MHz
SSBW_1
Peak
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
Peaking
dB
dB
Peak_1
LSBW
Peaking
0.05
75
–3 dB Bandwidth Large Signal
Peaking
VOUT = 2 V PP
MHz
dB
Peak_2
0.1 dB BW
GBWP_1k
GBWP_150
AVOL
VOUT = 2 VPP
0
0.1 dB Bandwidth
Gain Bandwidth Product
VOUT = 2 VPP
30
MHz
115
105
Unity Gain, RL = 1 kΩ to VS/2
MHz
Unity Gain, RL = 150Ω to VS/2
0.3V < VOUT < 3V
Large Signal Open Loop Gain
Full Power BW
56
67
30
dB
PBW
–1 dB, AV = +4, VOUT = 2.8VPP
,
MHz
RL = 150Ω to VS/2
DG
DP
Differential Gain
0.06
0.23
%
4.43 MHz, 0.85V ≤ VOUT ≤ 2.45V,
RL = 150Ω to V−
Differential Phase
deg
4.43 MHz, 0.85V ≤ VOUT ≤ 2.45V
RL = 150Ω to V−
Time Domain Response
TRS/TRL
OS
Rise & Fall Time
0.25V Step
2.7
10
ns
%
Overshoot
Slew Rate
Settling Time
0.25V Step
SR
2V Step
260
70
V/μs
TS
1V Step, ±0.1%
ns
TS_1
PD
1V Step, ±0.02%
300
2.6
50
Propagation Delay
Input to Output, 250 mV Step, 50%
AV = −1, 10% Overshoot, 82Ω in Series
ns
CL
Cap Load Tolerance
pF
Distortion & Noise Performance
HD2
Harmonic Distortion (2nd)
2 VPP, 10 MHz
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
2 VPP, 10 MHz
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
>10 MHz
−61
−79
HD2_1
dBc
HD3
Harmonic Distortion (3rd)
−53
−69
HD3_2
dBc
dBc
THD
Total Harmonic Distortion
Input Voltage Noise
Input Current Noise
−66
VN1
VN2
IN
7
nV/
fA/
mV
1 MHz
10
50
>1 MHz
Static, DC Performance
VIO
Input Offset Voltage
±1
±2.6
±5.5
DVIO
IB
Input Offset Voltage Average Drift (Note 8)
−4.5
5
μV/°C
pA
Input Bias Current
Input Offset Current
Input Resistance
(Note 9)
(Note 9)
50
25
IOS
RIN
2
pA
15
TΩ
0V ≤ VIN ≤ 1.8V
CIN
Input Capacitance
1.4
pF
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4
Symbol
+PSRR
Parameter
Condition
Min
Typ
Max
Units
dB
(Note 6) (Note 6) (Note 6)
Positive Power Supply Rejection DC
Ratio
61
51
80
72
73
−PSRR
CMRR
Negative Power Supply Rejection DC
Ratio
57
52
dB
Common Mode Rejection Ratio
DC
58
dB
55
CMVR
ICC
Input Voltage Range
Supply Current
CMRR > 50 dB
V− -0.20
V+ -1.5
V
–
9.2
Normal Operation
VOUT = VS/2
11
13
mA
nA
Shutdown
100
SD tied to ≤ 0.33V (Note 5)
RL = 150Ω to V–
VOH1
Output High Voltage
(Relative to V+)
–210
–360
–190
VOH2
VOH3
–190
–10
RL = 75Ω to VS/2
RL = 10 kΩ to V−
mV
mV
–50
–100
RL = 150Ω to V–
VOL1
Output Low Voltage
(Relative to V–)
+4
+45
+125
VOL2
VOL3
+105
+4
RL = 75Ω to VS/2
RL = 10 kΩ to V–
+45
+125
IO
Output Current
VOUT < 0.6V from Respective Source
50
75
Supply
Sink
mA
IO_1
Load
VOUT = VS/2, VID = ±18 mV
(Note 10)
±75
Output Load Rating
THD < −30 dBc, f = 200 kHz,
25
Ω
RL tied to VS/2, VOUT = 2.6 VPP
Enabled, AV = +1
Shutdown
RO_Enabled Output Resistance
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
Miscellaneous Performance
0.2
>100
5.6
Ω
MΩ
pF
Shutdown
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5) (Note 5)
0
0.33
3.3
V
V
Voltage Limit for Enable (Pin 5)
Logic Input Current (Pin 5)
Turn-on Glitch
(Note 5)
2.97
SD = 3.3V (Note 5)
8
pA
V
V_glitch
Ton
1.6
3.5
500
60
Turn-on Time
µs
ns
dB
Toff
Turn-off Time
IsolationOFF Off Isolation
1 MHz, RL = 1 kΩ
5
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2.7V Electrical Characteristics Single Supply with VS = 2.7V, AV = +2, RF = 604Ω, SD tied to V+, VOUT
=
VS/2, RL = 150Ω to V− unless otherwise specified. Boldface limits apply at temperature extremes. (Note 2)
Symbol
Parameter
Condition
Min
Typ
Max
Units
(Note 6) (Note 6) (Note 6)
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
VOUT = 0.25 VPP
120
250
3.1
0.1
73
MHz
SSBW_1
Peak
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
Peaking
dB
dB
Peak_1
LSBW
Peaking
–3 dB Bandwidth Large Signal
Peaking
VOUT = 2 V PP
MHz
dB
Peak_2
0.1 dB BW
GBWP_1k
GBWP_150
AVOL
VOUT = 2 VPP
0
0.1 dB Bandwidth
Gain Bandwidth Product
VOUT = 2VPP
30
MHz
110
81
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150Ω to VS/2
0.25V < VOUT < 2.5V
MHz
Large Signal Open Loop Gain
Full Power BW
56
65
13
dB
PBW
–1 dB, AV = +4, VOUT = 2 VPP
,
MHz
RL = 150Ω to VS/2
DG
DP
Differential Gain
0.12
0.62
%
4.43 MHz, 0.45V ≤ VOUT ≤ 2.05V
RL = 150Ω to V−
Differential Phase
deg
4.43 MHz, 0.45V ≤ VOUT ≤ 2.05V
RL = 150Ω to V−
Time Domain Response
TRS/TRL
OS
Rise & Fall Time
0.25V Step
2.7
10
ns
%
Overshoot
Slew Rate
Settling Time
0.25V Step
SR
2V Step
260
147
410
3.4
V/μs
TS
1V Step, ±0.1%
1V Step, ±0.02%
Input to Output, 250 mV Step, 50%
ns
ns
TS_1
PD
Propagation Delay
Distortion & Noise Performance
HD2
HD3
VN1
VN2
IN
Harmonic Distortion (2nd)
Harmonic Distortion (3rd)
Input Voltage Noise
1 VPP, 10 MHz
1 VPP, 10 MHz
>10 MHz
−58
−60
8.4
12
dBc
dBc
nV/
fA/
1 MHz
Input Current Noise
>1 MHz
50
Static, DC Performance
VIO
Input Offset Voltage
±1
±3.5
±6.5
mV
DVIO
IB
Input Offset Voltage Average Drift (Note 8)
−6.5
5
μV/°C
pA
Input Bias Current
Input Offset Current
Input Resistance
(Note 9)
(Note 9)
50
IOS
RIN
2
25
pA
20
TΩ
0V ≤ VIN ≤ 1.2V
CIN
Input Capacitance
1.6
68
pF
+PSRR
Positive Power Supply Rejection DC
Ratio
58
53
dB
−PSRR
CMRR
CMVR
Negative Power Supply Rejection DC
Ratio
56
53
69
77
–
dB
dB
Common Mode Rejection Ratio
DC
57
52
V− -0.20
Input Voltage Range
CMRR > 50 dB
V+ -1.5
V
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Symbol
ICC
Parameter
Supply Current
Condition
Normal Operation
Min
Typ
Max
Units
(Note 6) (Note 6) (Note 6)
9.0
100
10.6
12.5
mA
nA
VOUT = VS/2
Shutdown
SD tied to ≤ 0.27V (Note 5)
RL = 150Ω to V–
VOH1
Output High Voltage
(Relative to V+)
–260
–420
–200
VOH2
VOH3
–200
–10
RL = 75Ω to VS/2
RL = 10 kΩ to V–
mV
mV
–50
100
RL = 150Ω to V–
VOL1
Output Low Voltage
(Relative to V–)
+4
+45
+125
VOL2
VOL3
+125
+4
RL = 75Ω to VS/2
RL = 10 kΩ to V–
+45
125
IO
Output Current
Source
Sink
25
62
VOUT ≤ 0.6V from Respective
Supply
mA
IO_1
VOUT = VS/2, VID = ±18 mV Source
(Note 10)
25
35
Sink
Load
Output Load Rating
Output Resistance
THD < −30 dBc, f = 200 kHz, RL tied to
VS/2, VOUT = 2.2 VPP
40
Ω
RO_Enable
Enabled, AV = +1
Shutdown
0.2
>100
5.6
Ω
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
Miscellaneous Performance
MΩ
pF
Shutdown
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5) (Note 5)
0
0.27
2.7
V
V
Voltage Limit for Enable (Pin 5)
Logic Input Current (Pin 5)
Turn-on Glitch
(Note 5)
2.43
SD = 2.7V (Note 5)
4
pA
V
V_glitch
Ton
1.2
5.2
760
60
Turn-on Time
µs
ns
dB
Toff
Turn-off Time
IsolationOFF Off Isolation
1 MHz, RL = 1 kΩ
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test conditions, see the Electrical Characteristics.
Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating
of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ >
TA.
Note 3: The maximum continuous output current (IOUT) is determined by device power dissipation limitations.
Note 4: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
Note 5: SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10% of total supply
voltage away from either supply rail.
Note 6: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 7: Negative input current implies current flowing out of the device.
Note 8: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Note 9: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 10: “VID” is input differential voltage (input overdrive).
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Connection Diagram
6-Pin SC70
20136401
Top View
Ordering Information
Package
Part Number
Package Marking
Transport Media
NSC Drawing
Features
1k Units Tape and
Reel
LMH6601MG
A95
3k Units Tape and
Reel
LMH6601MGX
LMH6601QMG
LMH6601QMGX
6-Pin SC70
MAA06A
1k Units Tape and
Reel
AEC-Q100 grade 3
qualified. Automotive
Grade Production
Flow**
AKA
3k Units Tape and
Reel
**Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection
methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC-Q100 standard. Automotive grade products
are identified with the letter Q. For more information, go to http://www.national.com/automotive.
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Typical Performance Characteristics Unless otherwise noted, all data is with AV = +2,
RF = RG = 604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T = 25°C.
Frequency Response for Various Output Amplitudes
Frequency Response for Various Output Amplitudes
20136414
20136413
Frequency Response for Various Output Amplitudes
−3 dB BW vs. Supply Voltage for Various Output Swings
20136420
20136415
Non-inverting Frequency Response for Various Gain
Inverting Frequency Response for Various Gain
20136416
20136417
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Frequency Response for Various Loads
Frequency Response for Various Supply Voltages
20136419
20136421
−3 dB BW vs. Ambient Temperature
Frequency Response for Various Cap Load
20136422
20136418
Frequency Response for Various Supply Voltage
Max Output Swing vs. Frequency
20136426
20136441
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Peak Output Swing vs. RL
Output Swing vs. Sink Current for Various Supply Voltages
20136427
20136464
Output Swing vs. Source Current for Various Supply
Voltages
HD2 vs. Frequency
20136404
20136465
HD3 vs. Frequency
THD vs. Output Swing
20136405
20136402
11
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THD vs. Output Swing
Slew Rate vs. Ambient Temperature
20136423
20136403
Settling Time (±1%) vs. Output Swing
Output Settling
20136412
20136411
Isolation Resistor & Settling Time vs. CL
Isolation Resistor & Settling Time vs. CL
20136429
20136428
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Closed Loop Output Impedance vs. Frequency for Various
Supply Voltages
Off Isolation vs. Frequency
20136408
20136410
Noise Voltage vs. Frequency
Open Loop Gain/ Phase
20136435
20136424
CMRR vs. Frequency
+PSRR vs. Frequency
20136425
20136439
13
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−PSRR vs. Frequency
Supply Current vs. Ambient Temperature
20136433
20136440
Supply Current vs. VCM
Supply Current vs. Supply Voltage
20136437
20136467
Offset Voltage vs. Ambient Temperature
for 3 Representative Units
Offset Voltage Distribution
20136436
20136434
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Offset Voltage vs. VCM (Typical Part)
Input Bias Current vs. Common Mode Voltage
20136438
20136442
Small Signal Step Response
Large Signal Step Response
20136430
20136431
Large Signal Step Response
Turn On/Off Waveform
20136466
20136432
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DG vs. VOUT for Various VS
DP vs. VOUT for Various VS
20136472
20136471
DG vs. VOUT (DC and AC Coupled Load Compared)
DP vs. VOUT (DC and AC Coupled Load Compared)
20136473
20136474
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Application Information
OPTIMIZING PERFORMANCE
With many op amps, additional device non-linearity and
sometimes less loop stability arises when the output has to
switch from current-source mode to current-sink mode or vice
versa. When it comes to achieving the lowest distortion and
the best Differential Gain/ Differential Phase (DG/ DP, broad-
cast video specs), the LMH6601 is optimized for single supply
DC coupled output applications where the load current is re-
turned to the negative rail (V−). That is where the output stage
is most linear (lowest distortion) and which corresponds to
unipolar current flowing out of this device. To that effect, it is
easy to see that the distortion specifications improve when
the output is only sourcing current which is the distortion-op-
timized mode of operation for the LMH6601. In application
where the LMH6601 output is AC coupled or when it is pow-
ered by separate dual supplies for V+ and V−, the output stage
supplies both source and sink current to the load and results
in less than optimum distortion (and DG/DP). Figure 1 com-
pares the distortion results between a DC and an AC coupled
load to show the magnitude of this difference. See the DG/DP
plots in the Typical Performance Characteristics section for a
comparison between DC and AC coupling of the video load.
20136470
FIGURE 2. Output Pull-Down Value for Dual Supply & AC
Coupling
Furthermore, with a combination of low closed loop gain set-
ting (i.e. AV = +1 for example where device bandwidth is the
highest), light output loading (RL > 1 kΩ) , and with a signifi-
cant capacitive load (CL > 10 pF) , the LMH6601 is most stable
if output sink current is kept to less than about 5 mA. The pull-
down method described in Figure 2 is applicable in these
cases as well where the current that would normally be sunk
by the op amp is diverted to the RP path instead.
SHUTDOWN CAPABILITY AND TURN ON/ OFF
BEHAVIOR
With the device in shutdown mode, the output goes into high
impedance (ROUT > 100 MΩ) mode. In this mode, the only
path between the inputs and the output pin is through the ex-
ternal components around the device. So, for applications
where there is active signal connection to the inverting input,
with the LMH6601 in shutdown, the output could show signal
swings due to current flow through these external compo-
nents. For non-inverting amplifiers in shutdown, no output
swings would occur, because of complete input-output isola-
tion, with the exception of capacitive coupling.
20136406
FIGURE 1. Distortion Comparison between DC & AC
Coupling of the Load
For maximum power saving, the LMH6601 supply current
drops to around 0.1 μA in shutdown. All significant power
consumption within the device is disabled for this purpose.
Because of this, the LMH6601 turn on time is measured in
micro-seconds whereas its turn off is fast (nano-seconds) as
would be expected from a high speed device like this.
In certain applications, it may be possible to optimize the
LMH6601 for best distortion (and DG/DP) even though the
load may require bipolar output current by adding a pull-down
resistor to the output. Adding an output pull-down resistance
of appropriate value could change the LMH6601 output load-
ing into source-only. This comes at the price of higher total
power dissipation and increased output current requirement.
The LMH6601 SD pin is a CMOS compatible input with a pico-
ampere range input current drive requirement. This pin needs
to be tied to a level or otherwise the device state would be
indeterminate. The device shutdown threshold is half way be-
tween the V+ and V− pin potentials at any supply voltage. For
example, with V+ tied to 10V and V− equal to 5V, you can
expect the threshold to be at 7.5V. The state of the device
(shutdown or normal operation) is guaranteed over tempera-
ture as longs as the SD pin is held to within 10% of the total
supply voltage.
Figure 2 shows how to calculate the pull-down resistor value
for both the dual supply and for the AC coupled load applica-
tions.
For V+ = 10V, V− = 5V, as an example:
•
•
Shutdown Range
Normal Operation Range
5V ≤ SD ≤ 5.5V
9.5V ≤ SD ≤ 10V
17
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OVERLOAD RECOVERY AND SWING CLOSE TO RAILS
With some op amps, when the output approaches either one
or both rails and saturation starts to set in, there is significant
increase in the transistor parasitic capacitances which leads
to loss of Phase Margin. That is why with these devices, there
are sometimes hints of instability with output close to the rails.
With the LMH6601, as can be seen in Figure 4, the output
waveform remains free of instability throughout its range of
voltages.
The LMH6601 can recover from an output overload in less
than 20 ns. See Figure 3 below for the input and output scope
photos:
SINGLE SUPPLY VIDEO APPLICATION
The LMH6601’s high speed and fast slew rate make it an ideal
choice for video amplifier and buffering applications. There
are cost benefits in having a single operating supply. Single
supply video systems can take advantage of the LMH6601’s
low supply voltage operation along with its ability to operate
with input common mode voltages at or slightly below the V
− rail. Additional cost savings can be achieved by eliminating
or reducing the value of the input and output AC coupling ca-
pacitors commonly employed in single supply video applica-
tions. This Application section shows some circuit techniques
used to help in doing just that.
20136407
DC COUPLED, SINGLE SUPPLY BASEBAND VIDEO
AMPLIFIER/DRIVER
FIGURE 3. LMH6601 Output Overload Recovery
Waveform
The LMH6601 output can swing very close to either rail to
maximize the output dynamic range which is of particular in-
terest when operating in a low voltage single supply environ-
ment. Under light output load conditions, the output can swing
as close as a few milli-volts of either rail. This also allows a
video amplifier to preserve the video black level for excellent
video integrity. In the example shown below in Figure 5, the
baseband video output is amplified and buffered by the
LMH6601 which then drives the 75Ω back terminated video
cable for an overall gain of +1 delivered to the 75Ω load. The
input video would normally have a level between 0V to ap-
proximately 0.75V.
In Figure 3, the input step function is set so that the output is
driven to one rail and then the other and then the output re-
covery is measured from the time the input crosses 0V to
when the output reaches this point.
Also, when the LMH6601 input voltage range is exceeded
near the V+ rail, the output does not experience output phase
reversal, as some op amps do. This is particularly advanta-
geous in applications where output phase reversal has to be
avoided at all costs, such as in servo loop control among oth-
ers. This adds to the LMH6601’s set of features which make
this device easy to use.
In addition, the LMH6601’s output swing close to either rail is
well-behaved as can be seen in the scope photo of Figure 4.
20136444
FIGURE 5. Single Supply Video Driver Capable of
Maintaining Accurate Video Black Level
20136443
FIGURE 4. LMH6601’s “Clean” Swing to Either Rail
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18
With the LMH6601 input common mode range including the
V− (ground) rail, there will be no need for AC coupling or level
shifting and the input can directly drive the non-inverting input
which has the additional advantage of high amplifier input
impedance. With LMH6601’s wide rail-to-rail output swing, as
stated earlier, the video black level of 0V is maintained at the
load with minimal circuit complexity and using no AC coupling
capacitors. Without true rail-to-rail output swing of the
LMH6601, and more importantly without the LMH6601’s abil-
ity of exceedingly close swing to V−, the circuit would not
operate properly as shown at the expense of more complex-
ity. This circuit will also work for higher input voltages. The
only significant requirement is that there is at least 1.8V from
the maximum input voltage to the positive supply (V+).
20136446
The Composite Video Output of some low cost consumer
video equipment consists of a current source which develops
the video waveform across a load resistor (usually 75Ω), as
shown in Figure 6 below. With these applications, the same
circuit configuration just described and shown in Figure 6 will
be able to buffer and drive the Composite Video waveform
which includes sync and video combined. However, with this
arrangement, the LMH6601 supply voltage needs to be at
least 3.3V or higher in order to allow proper input common
mode voltage headroom because the input can be as high as
1V peak.
FIGURE 7. Single Supply DC Coupled Composite Video
Driver for Negative Going Sync Tip
In the circuit of Figure 7, the input is shifted positive by means
of R1, R2, and RT in order to satisfy U1’s Common Mode input
range. The signal will loose 20% of its amplitude in the pro-
cess. The closed loop gain of U1 will need to be set to make
up for this 20% loss in amplitude. This gives rise to the gain
expression shown below which is based on a getting a 2
VPP output with a 0.8 VPP input:
(1)
R3 will produce a negative shift at the output due to VS (3.3V
in this case). R3 will need to be set so that the “Video In” sync
tip (−0.3V at RT or 0.61V at U1 non-inverting input) corre-
sponds to near 0V at the output.
(2)
Equation 1 and Equation 2 need to be solved simultaneously
to arrive at the values of R3, RF, and RG which will satisfy both.
From the datasheet, one can set RF = 620Ω to be close to the
recommended value for a gain of +2. It is easier to solve for
RG and R3 by starting with a good estimate for one and iter-
atively solving Equation and Equation 2 to arrive at the results.
Here is one possible iteration cycle for reference:
20136445
FIGURE 6. Single Supply Composite Video Driver for
Consumer Video Outputs
If the “Video In” signal is Composite Video with negative going
Sync tip, a variation of the previous configurations should be
used. This circuit produces a unipolar (above 0V) DC coupled
single supply video signal as shown in Figure 7.
RF = 620Ω
19
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TABLE 1. Finding Figure 7 External Resistor Values by Iteration
Estimate
Calculated
(from Equation 2)
R3 (Ω)
Equation 1 LHS
Calculated
Comment
(Compare Equation 1 LHS Calculated to RHS)
RG (Ω)
1k
1.69k
1.56k
1.37k
239
0.988
1.15
1.45
4.18
1.59
Increase Equation 1 LHS by reducing RG
Increase Equation 1 LHS by reducing RG
Increase Equation 1 LHS by reducing RG
Reduce Equation 1 LHS by increasing RG
Close to target value of 1.5V/V for Equation 1
820
620
390
560
1.30k
The final set of values for RG and R3 in Table 1 are values
which will result in the proper gain and correct video levels
(0V to 1V) at the output (VLOAD).
of the DC bias at the output, the load needs to be AC coupled
as well through CO. Some applications implement a small
valued ceramic capacitor (not shown) in parallel with CO
which is electrolytic. The reason for this is that the ceramic
capacitor will tend to shunt the inductive behavior of the Elec-
trolytic capacitor at higher frequencies for an improved overall
low impedance output.
AC COUPLED VIDEO
Many monitors and displays accept AC coupled inputs. This
simplifies the amplification and buffering task in some re-
spects. As can be seen in Figure 8, R1 and R2 simply set the
input to the center of the input linear range while CIN AC cou-
ples the video onto the op amp’s input. The op amp is set for
a closed loop gain of 2 with RF and RG. CG is there to make
sure the device output is also biased at mid-supply. Because
CG2 is intended to boost the high frequency gain in order to
improve the video frequency response. This value is to be set
and trimmed on the board to meet the application’s specific
system requirements.
20136449
FIGURE 8. AC Coupled Video Amplifier/Driver
SAG COMPENSATION
which cannot adequately go through the output AC coupling
scheme due to the low frequency limit of this circuit. The −3
dB low frequency limit of the output circuit is given by:
The capacitors shown in Figure 8 (except CG2), and especially
CO, are the large electrolytic type which are considerably
costly and take up valuable real estate on the board. It is pos-
sible to reduce the value of the output coupling capacitor,
CO, which is the largest of all, by using what is called SAG
compensation. SAG refers to what the output video experi-
ences due to the low frequency video content it contains
f_low_frequency (−3 dB)= 1/ (2*pi* 75*2(Ω) * CO)
= ∼ 4.82 Hz For CO = 220 μF
(3)
A possible implementation of the SAG compensation is
shown in Figure 9.
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20
20136450
FIGURE 9. AC Coupled Video Amplifier/Driver with SAG Compensation
In this circuit, the output coupling capacitor value and size is
reduced at the expense of a slightly more complicated cir-
cuitry. Note that C1 is not only part of the SAG compensation,
but it also sets the amplifier’s DC gain to 0 dB so that the
output is set to mid-rail for linearity purposes. Also note that
exceptionally high values are chosen for the R1 and R2 bi-
asing resistors (510 kΩ). The LMH6601 has extremely low
input bias current which allows this selection thereby reducing
the CIN value in this circuit such that CIN can even be a non-
polar capacitors which will reduce cost.
11 ms, CO is discharging through the load with no video ac-
tivity to replenish that charge.
Figure 10 shows the output of the Figure 9 circuit highlighting
the SAG.
At high enough frequencies where both CO and C1 can be
considered to be shorted out, R3 shunts R4 and the closed
loop gain is determined by:
Closed_loop_Gain (V/V)= VL/VIN = (1+ (R3||R4)/ R5)x
[RL/(RL+RO)]= 0.99V/V
(4)
At intermediate frequencies, where the CO, RO, RL path ex-
periences low frequency gain loss, the R3, R5, C1 path pro-
vides feedback from the load side of CO. With the load side
gain reduced at these lower frequencies, the feedback to the
op amp inverting node reduces, causing an increase at the
op amp's output as a response.
20136451
For NTSC video, low values of CO influence how much video
black level shift occurs during the vertical blanking interval
(∼1.5 ms) which has no video activity and thus is sensitive to
CO's charge dissipation through the load which could cause
output SAG. An especially tough pattern is the NTSC pattern
called “Pulse & Bar.” With this pattern the entire top and bot-
tom portion of the field is black level video where, for about
FIGURE 10. Figure 9 Scope Photo Showing Video SAG
With the circuit of Figure 9 and any other AC coupled pulse
amplifier, the waveform duty cycle variations exert additional
restrictions on voltage swing at any node. This is illustrated in
the waveforms shown in Figure 11.
21
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20136452
FIGURE 11. Headroom Considerations with AC Coupled Amplifiers
If a stage has a 3 VPP unclipped swing capability available at
HOW TO PICK THE RIGHT VIDEO AMPLIFIER
a given node, as shown in Figure 11, the maximum allowable
amplitude for an arbitrary waveform is ½ of 3V or 1.5 VPP. This
is due to the shift in the average value of the waveform as the
duty cycle varies. Figure 11 shows what would happen if a
2 VPP signal were applied. A low duty cycle waveform, such
as the one in Figure 11B, would have high positive excur-
sions. At low enough duty cycles, the waveform could get
clipped on the top, as shown, or a more subtle loss of linearity
could occur prior to full-blown clipping. The converse of this
occurs with high duty cycle waveforms and negative clipping,
as depicted in Figure 11C.
Apart from output current drive and voltage swing, the op amp
used for a video amplifier/cable driver should also possess
the minimum requirement for speed and slew rate. For video
type loads, it is best to consider Large Signal Bandwidth (or
LSBW in the National Semiconductor data sheet tables) as
video signals could be as large as 2 VPP when applied to the
commonly used gain of +2 configuration. Because of this rel-
atively large swing, the op amp Slew Rate (SR) limitation
should also be considered. Table 2 shows these require-
ments for various video line rates calculated using a rudimen-
tary technique and intended as a first order estimate only.
TABLE 2. Rise Time, −3 dB BW, and Slew Rate Requirements for Various Video Line Rates
Video
Standard
Line Rate Refresh Rate Horizontal Vertical Pixel Time Rise Time LSBW
SR
(V/μs)
41
(HxV) (Hz) Active (KH%) Active (KV%)
(ns)
118.3
33.0
20.3
12.4
7.3
(ns)
39.4
11.0
6.8
(MHz)
9
TV_NTSC
VGA
451x483
640x480
30
75
75
75
75
75
84
80
76
77
75
74
92
95
96
95
96
96
32
146
237
387
655
973
SVGA
XGA
800x600
52
1024x768
1280x1024
1600x1200
4.1
85
SXGA
UXGA
2.4
143
213
4.9
1.6
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22
For any video line rate (HxV corresponding to the number of
Active horizontal and vertical lines), the speed requirements
can be estimated if the Horizontal Active (KH%) and Vertical
Active (KV%) numbers are known. These percentages cor-
respond to the percentages of the active number of lines
(horizontal or vertical) to the total number of lines as set by
VESA standards. Here are the general expressions and the
specific calculations for the SVGA line rate shown in Table
2.
20136458
FIGURE 12. Typical Connection of a Photodiode Detector
to an op amp
(5)
Requiring that an “On” pixel is illuminated to at least 90% of
its final value before changing state will result in the rise/fall
time equal to, at most, ⅓ the pixel time as shown below:
With the LMH6601 input bias current in the femto-amperes
range, even large values of gain (RF) do not increase the out-
put error term appreciably. This allows circuit operation to a
lower light intensity level which is always of special impor-
tance in these applications. Most photo-diodes have a rela-
tively large capacitance (CD) which would be even larger for
a photo-diode designed for higher sensitivity to light because
of its larger area. Some applications may run the photodiode
with a reverse bias in order to reduce its capacitance with the
disadvantage of increased contributions from both dark cur-
rent and noise current. Figure 13 shows a typical photodiode
capacitance plot vs. reverse bias for reference.
(6)
Assuming a single pole frequency response roll-off charac-
teristic for the closed loop amplifier used, we have:
(7)
Rise/Fall times are 10%-90% transition times, which for a 2
VPP video step would correspond to a total voltage shift of
1.6V (80% of 2V). So, the Slew Rate requirement can be cal-
culated as follows:
(8)
The LMH6601 specifications show that it would be a suitable
choice for video amplifiers up to and including the SVGA line
rate as demonstrated above.
For more information about this topic and others relating to
video amplifiers, please see Application Note 1013:
http://www.national.com/an/AN/AN-1013.pdf#page=1
CURRENT TO VOLTAGE CONVERSION
(TRANSIMPEDANCE AMPLIFIER (TIA))
Being capable of high speed and having ultra low input bias
current makes the LMH6601 a natural choice for Current to
Voltage applications such as photodiode I-V conversion. In
these type of applications, as shown in Figure 12 below, the
photodiode is tied to the inverting input of the amplifier with
RF set to the proper gain (gain is measured in Ohms).
20136459
FIGURE 13. Typical Capacitance vs. Reverse Bias
(Source: OSI Optoelectronics)
23
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The diode capacitance (CD) along with the input capacitance
of the LMH6601 (CA) has a bearing on the stability of this cir-
cuit and how it is compensated. With large transimpedance
gain values (RF), the total combined capacitance on the am-
plifier inverting input (CIN = CD + CA) will work against RF to
create a zero in the Noise Gain (NG) function (see Figure
14). If left untreated, at higher frequencies where NG equals
the open loop transfer function there will be excess phase shift
around the loop (approaching 180°) and therefore, the circuit
could be unstable. This is illustrated in Figure 14.
Figure 14 shows that placing a capacitor, CF, with the proper
value, across RF will create a pole in the NG function at fP.
For optimum performance, this capacitor is usually picked so
that NG is equal to the op amp's open loop gain at fP. This will
cause a “flattening” of the NG slope beyond the point of in-
tercept of the two plots (open loop gain and NG) and will
results in a Phase Margin (PM) of 45° assuming fP and fZ are
at least a decade apart. This is because at the point of inter-
cept, the NG pole at fP will have a 45° phase lead contribution
which leaves 45° of PM. For reference, Figure 14 also shows
the transimpedance gain (I-V (Ω))
Here is the theoretical expression for the optimum CF value
and the expected −3 dB bandwidth:
(9)
(10)
Table 3, below, lists the results, along with the assumptions
and conditions, of testing the LMH6601 with various photodi-
odes having different capacitances (CD) at a transimpedance
gain (RF) of 10 kΩ.
20136460
FIGURE 14. Transimpedance Amplifier Graphical
Stability Analysis and Compensation
TABLE 3. Transimpedance Amplifier Figure 12 Compensation and Performance Results
CD
(pF)
10
CIN CF_Calculated CF used −3 dB BW −3 dB BW Step Response
Calculated (MHz) Measured (MHz)
Overshoot (%)
(pF)
12
(pF)
1.1
2.3
7.2
(pF)
1
14
7
15
7.0
2.5
6
4
9
50
52
3
500
502
8
2
CA = 2 pF
GBWP = 155 MHz
VS = 5V
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24
TRANSIMPEDANCE AMPLIFIER NOISE
CONSIDERATIONS
When analyzing the noise at the output of the I-V converter,
it is important to note that the various noise sources (i.e. op
amp noise voltage, feedback resistor thermal noise, input
noise current, photodiode noise current) do not all operate
over the same frequency band. Therefore, when the noise at
the output is calculated, this should be taken into account.
The op amp noise voltage will be gained up in the region be-
tween the noise gain’s “zero” and its “pole” (fz and fp in Figure
14). The higher the values of RF and CIN, the sooner the noise
gain peaking starts and therefore its contribution to the total
output noise would be larger. It is obvious to note that it is
advantageous to minimize CIN (e.g. by proper choice of op
amp, by applying a reverse bias across the diode at the ex-
pense of excess dark current and noise). However, most low
noise op amps have a higher input capacitance compared to
ordinary op amps. This is due to the low noise op amp’s larger
input stage.
20136468
FIGURE 16. In-Loop Compensation Circuit for Driving a
Heavy Capacitive Load
When driving a high capacitive load, an isolation resistor
(RS) should be connected in series between the op amp out-
put and the capacitive load to provide isolation and to avoid
oscillations. A small value capacitor (CF) is inserted between
the op amp output and the inverting input as shown such that
this capacitor becomes the dominant feedback path at higher
frequency. Together these components allow heavy capaci-
tive loading while keeping the loop stable.
OTHER APPLICATIONS
There are few factors which affect the driving capability of the
op amp:
•
•
Op amp internal architecture
Closed loop gain and output capacitor loading
Table 4 shows the measured step response for various values
of load capacitors (CL), series resistor (RS) and feedback re-
sistor (CF) with gain of +2 (RF = RG = 604Ω) and RL = 2 kΩ:
TABLE 4. LMH6601 Step Response Summary for the
Circuit of Figure 16
CL
(pF)
RS
(Ω)
0
CF
(pF)
trise/ tfall
(ns)
Overshoot
(%)
10
50
1
1
6*
7*
8
0
6
110
300
500
910
47
6
1
10
12
33
65
16
20
10
10
10
10
10
20136463
80
192
FIGURE 15. Charge Preamplifier Taking Advantage of
LMH6601’s Femto-Ampere Range Input Bias Current
* Response limited by input step generator rise time of 5 ns
Figure 17 shows the increase in rise/fall time (bandwidth de-
crease) at VOUT with larger capacitive loads, illustrating the
trade-off between the two:
CAPACITIVE LOAD
The LMH6601 can drive a capacitive load of up to 1000 pF
with correct isolation and compensation. Figure 16 illustrates
the in-loop compensation technique to drive a large capacitive
load.
25
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EVALUATION BOARD
National Semiconductor provides the following evaluation
board as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the datasheet
plots were measured with this board:
Device
Package
Board Part #
LMH6601MG
SC70-6
LMH730165
This evaluation board can be shipped when a device sample
request is placed with National Semiconductor.
20136469
FIGURE 17. LMH6601 In-Loop Compensation Response
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26
Physical Dimensions inches (millimeters) unless otherwise noted
6-Pin SC70
NS Package Number MA006A
27
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