LMH6601QMGX/NOPB [TI]
250 MHz, 2.4V CMOS Operational Amplifier with Shutdown 6-SC70 -40 to 85;
| 型号： | LMH6601QMGX/NOPB |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 250 MHz, 2.4V CMOS Operational Amplifier with Shutdown 6-SC70 -40 to 85 放大器 光电二极管 |
| 文件： | 总37页 (文件大小：1268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LMH6601, LMH6601-Q1
www.ti.com
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
LMH6601/LMH6601Q 250 MHz, 2.4V CMOS Operational Amplifier with Shutdown
Check for Samples: LMH6601, LMH6601-Q1
1
FEATURES
DESCRIPTION
The LMH6601 is a low voltage (2.4V – 5.5V), high
speed voltage feedback operational amplifier suitable
for use in a variety of consumer and industrial
applications. With a bandwidth of 125 MHz at a gain
of +2 and ensured high output current of 100 mA, the
LMH6601 is an ideal choice for video line driver
applications including HDTV. Low input bias current
(50 pA maximum), rail-to-rail output, and low current
noise allow the LMH6601 to be used in various
industrial applications such as transimpedance
amplifiers, active filters, or high-impedance buffers.
The LMH6601 is an attractive solution for systems
which require high performance at low supply
voltages. The LMH6601 is available in a 6-pin SC70
2
•
VS = 3.3V, TA = 25°C, AV = 2 V/V, RL = 150Ω to
V−, unless Specified.
•
•
•
•
•
•
•
•
•
125 MHz −3 dB Small Signal Bandwidth
75 MHz −3 dB Large Signal Bandwidth
30 MHz Large Signal 0.1 dB Gain Flatness
260 V/μs Slew Rate
0.25%/0.25° Differential Gain/Differential Phase
Rail-to-Rail Output
2.4V – 5.5V Single Supply Operating Range
6-Pin SC70 Package
LMH6601Q is AEC-Q100 Grade 3 Qualified and
is Manufactured on an Automotive Grade Flow
package, and includes
feature.
a
micropower shutdown
APPLICATIONS
7
6
•
•
•
•
•
•
•
•
Video Amplifier
Charge Amplifier
Set-Top Box
5
2.7V
Sample & Hold
4
Transimpedance Amplifier
Line Driver
5V
3
3.3V
High Impedance Buffer
Automotive
2
1
0
-1
1
10
100
1000
FREQUENCY (MHz
Figure 1. Response at a Gain of +2 for Various
Supply Voltages
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LMH6601, LMH6601-Q1
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
(1)
ABSOLUTE MAXIMUM RATINGS
ESD Tolerance
(2)
Human Body Model
Machine Model
2 kV
200V
±2.5V
VIN Differential
Input Current(3)
±10 mA
(4)
Output Current
200 mA
Supply Voltage (V+ – V−)
Voltage at Input/Output Pins
Storage Temperature Range
Junction Temperature
Soldering Information
6.0V
V++0.5V, V−−0.5V
−65°C to +150°C
+150°C
Infrared or Convection (20 sec.)
Wave Soldering (10 sec.)
235°C
260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications and the test conditions, see the
Electrical Characteristics.
(2) Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
(3) Negative input current implies current flowing out of the device.
(4) The maximum continuous output current (IOUT) is determined by device power dissipation limitations.
(1)
OPERATING RATINGS
Supply Voltage (V+ – V−)
2.4V to 5.5V
−40°C to +85°C
414°C/W
Operating Temperature Range
Package Thermal Resistance (θJA
)
6-pin SC70
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications and the test conditions, see the
Electrical Characteristics.
2
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
www.ti.com
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
5V ELECTRICAL CHARACTERISTICS
Single Supply with VS= 5V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150Ω to V− unless otherwise specified.
(1)
Boldface limits apply at temperature extremes.
(2)
(2)
(2)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
VOUT = 0.25 VPP
130
MHz
SSBW_1
Peak
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
250
2.5
0
Peaking
dB
dB
Peak_1
LSBW
Peaking
–3 dB Bandwidth Large Signal
Peaking
VOUT = 2 VPP
81
0
MHz
dB
Peak_2
0.1 dB BW
GBWP_1k
GBWP_150
AVOL
VOUT = 2 VPP
0.1 dB Bandwidth
Gain Bandwidth Product
VOUT = 2 VPP
30
155
125
66
30
MHz
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150Ω to VS/2
0.5V < VOUT < 4.5V
MHz
Large Signal Open Loop Gain
Full Power BW
56
dB
PBW
–1 dB, AV = +4, VOUT = 4.2 VPP
,
MHz
RL = 150Ω to VS/2
DG
DP
Differential Gain
4.43 MHz, 1.7V ≤ VOUT ≤ 3.3V,
RL = 150Ω to V−
0.06
0.10
%
Differential Phase
4.43 MHz, 1.7V ≤ VOUT ≤ 3.3V
RL = 150Ω to V−
deg
Time Domain Response
TRS/TRL
OS
Rise & Fall Time
0.25V Step
2.6
10
ns
%
Overshoot
Slew Rate
Settling Time
0.25V Step
SR
2V Step
275
50
V/μs
TS
1V Step, ±0.1%
1V Step, ±0.02%
ns
TS_1
PD
220
2.4
50
Propagation Delay
Input to Output, 250 mV Step, 50%
ns
CL
Cap Load Tolerance
AV = −1, 10% Overshoot, 75Ω in Series
pF
Distortion & Noise Performance
HD2
HD2_1
HD3
HD3_1
THD
VN1
Harmonic Distortion (2nd
)
2 VPP, 10 MHz
−56
−61
−73
−64
−58
7
dBc
dBc
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
2 VPP, 10 MHz
Harmonic Distortion (3rd)
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
4 VPP, 10 MHz, RL = 1 kΩ to VS/2
>10 MHz
Total Harmonic Distortion
Input Voltage Noise
nV/√Hz
fA/√Hz
VN2
1 MHz
10
IN
Input Current Noise
>1 MHz
50
Static, DC Performance
VIO
Input Offset Voltage
±1
±2.4
mV
±5.0
(3)
(4)
(4)
DVIO
IB
Input Offset Voltage Average Drift
Input Bias Current
−5
5
μV/°C
pA
50
25
IOS
Input Offset Current
2
pA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(4) This parameter is ensured by design and/or characterization and is not tested in production.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
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Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
www.ti.com
5V ELECTRICAL CHARACTERISTICS (continued)
Single Supply with VS= 5V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150Ω to V− unless otherwise specified.
Boldface limits apply at temperature extremes. (1)
(2)
(2)
(2)
Symbol
RIN
Parameter
Input Resistance
Condition
Min
Typ
10
Max
Units
TΩ
0V ≤ VIN ≤ 3.5V
CIN
Input Capacitance
1.3
59
pF
+PSRR
Positive Power Supply Rejection
Ratio
DC
55
51
dB
−PSRR
Negative Power Supply Rejection
Ratio
DC
53
50
61
68
dB
dB
CMRR
Common Mode Rejection Ratio
DC
56
53
CMVR
ICC
Input Voltage Range
Supply Current
CMRR > 50 dB
V− -0.20
–
V+ - 1.5
V
Normal Operation
VOUT = VS/2
9.6
11.5
13.5
mA
nA
Shutdown
SD tied to ≤ 0.5V
100
(5)
VOH1
Output High Voltage
(Relative to V+)
RL = 150Ω to V–
–210
–480
–190
VOH2
VOH3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
–190
–12
mV
mV
–60
–110
VOL1
Output Low Voltage
(Relative to V–)
RL = 150Ω to V–
+5
+45
+125
VOL2
VOL3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
+120
+5
+45
+125
IO
Output Current
VOUT < 0.6V from Respective Source
150
180
Supply
Sink
mA
IO_1
VOUT = VS/2,
VID = ±18 mV
±100
(6)
Load
Output Load Rating
THD < −30 dBc, f = 200 kHz,
20
Ω
RL tied to VS/2, VOUT = 4 VPP
RO_Enabled Output Resistance
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
Miscellaneous Performance
Enabled, AV = +1
Shutdown
0.2
>100
5.0
Ω
MΩ
pF
Shutdown
(5)
(5)
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5)
0
0.5
5.0
V
V
Voltage Limit for Enable (Pin 5)
Logic Input Current (Pin 5)
Turn-on Glitch
4.5
(5)
SD = 5V
10
2.2
1.4
520
60
pA
V
V_glitch
Ton
Turn-on Time
µs
ns
dB
ns
Toff
Turn-off Time
IsolationOFF
T_OL
Off Isolation
1 MHz, RL = 1 kΩ
Overload Recovery
<20
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
(6) “VID” is input differential voltage (input overdrive).
4
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
www.ti.com
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
3.3V ELECTRICAL CHARACTERISTICS
Single Supply with VS= 3.3V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150Ω to V− unless otherwise specified.
(1)
Boldface limits apply at temperature extremes.
(2)
(2)
(2)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
VOUT = 0.25 VPP
125
MHz
SSBW_1
Peak
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
250
3
Peaking
dB
dB
Peak_1
LSBW
Peaking
0.05
75
–3 dB Bandwidth Large Signal
Peaking
VOUT = 2 V PP
MHz
dB
Peak_2
0.1 dB BW
GBWP_1k
GBWP_150
AVOL
VOUT = 2 VPP
0
0.1 dB Bandwidth
Gain Bandwidth Product
VOUT = 2 VPP
30
MHz
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150Ω to VS/2
0.3V < VOUT < 3V
115
105
67
MHz
Large Signal Open Loop Gain
Full Power BW
56
dB
PBW
–1 dB, AV = +4, VOUT = 2.8VPP
,
30
MHz
RL = 150Ω to VS/2
DG
DP
Differential Gain
4.43 MHz, 0.85V ≤ VOUT ≤ 2.45V,
RL = 150Ω to V−
0.06
0.23
%
Differential Phase
4.43 MHz, 0.85V ≤ VOUT ≤ 2.45V
RL = 150Ω to V−
deg
Time Domain Response
TRS/TRL
OS
Rise & Fall Time
0.25V Step
2.7
10
ns
%
Overshoot
Slew Rate
Settling Time
0.25V Step
SR
2V Step
260
70
V/μs
TS
1V Step, ±0.1%
ns
TS_1
PD
1V Step, ±0.02%
300
2.6
50
Propagation Delay
Input to Output, 250 mV Step, 50%
AV = −1, 10% Overshoot, 82Ω in Series
ns
CL
Cap Load Tolerance
pF
Distortion & Noise Performance
HD2
Harmonic Distortion (2nd
)
2 VPP, 10 MHz
−61
−79
dBc
HD2_1
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
HD3
Harmonic Distortion (3rd)
2 VPP, 10 MHz
−53
−69
dBc
dBc
HD3_2
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
THD
Total Harmonic Distortion
Input Voltage Noise
2 VPP, 10 MHz
RL = 1 kΩ to VS/2
−66
VN1
VN2
IN
>10 MHz
1 MHz
7
nV/√Hz
fA/√Hz
10
50
Input Current Noise
>1 MHz
Static, DC Performance
VIO
Input Offset Voltage
±1
±2.6
±5.5
mV
(3)
DVIO
Input Offset Voltage Average Drift See
−4.5
μV/°C
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
www.ti.com
3.3V ELECTRICAL CHARACTERISTICS (continued)
Single Supply with VS= 3.3V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150Ω to V− unless otherwise specified.
Boldface limits apply at temperature extremes. (1)
(2)
(2)
(2)
Symbol
Parameter
Input Bias Current
Condition
Min
Typ
5
Max
50
Units
pA
(4)
IB
See
See
(4)
IOS
Input Offset Current
Input Resistance
Input Capacitance
2
25
pA
RIN
0V ≤ VIN ≤ 1.8V
15
TΩ
pF
CIN
1.4
80
+PSRR
Positive Power Supply Rejection
Ratio
DC
61
51
dB
−PSRR
Negative Power Supply Rejection
Ratio
DC
57
52
72
73
dB
dB
CMRR
Common Mode Rejection Ratio
DC
58
55
CMVR
ICC
Input Voltage Range
Supply Current
CMRR > 50 dB
V− -0.20
–
V+ -1.5
V
Normal Operation
VOUT = VS/2
9.2
11
13
mA
nA
Shutdown
SD tied to ≤ 0.33V
100
(5)
VOH1
Output High Voltage
(Relative to V+)
RL = 150Ω to V–
–210
–360
–190
VOH2
VOH3
RL = 75Ω to VS/2
RL = 10 kΩ to V−
–190
–10
mV
mV
–50
–100
VOL1
Output Low Voltage
(Relative to V–)
RL = 150Ω to V–
+4
+45
+125
VOL2
VOL3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
+105
+4
+45
+125
IO
Output Current
VOUT < 0.6V from Respective Source
50
75
Supply
Sink
mA
(6)
IO_1
VOUT = VS/2, VID = ±18 mV
±75
Load
Output Load Rating
THD < −30 dBc, f = 200 kHz,
25
Ω
RL tied to VS/2, VOUT = 2.6 VPP
RO_Enabled Output Resistance
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
Miscellaneous Performance
Enabled, AV = +1
Shutdown
0.2
>100
5.6
Ω
MΩ
pF
Shutdown
(5)
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5)
See
0
0.33
3.3
V
V
(5)
Voltage Limit for Enable (Pin 5)
Logic Input Current (Pin 5)
Turn-on Glitch
See
2.97
(5)
SD = 3.3V
8
pA
V
V_glitch
Ton
1.6
3.5
500
60
Turn-on Time
µs
ns
dB
Toff
Turn-off Time
IsolationOFF
Off Isolation
1 MHz, RL = 1 kΩ
(4) This parameter is ensured by design and/or characterization and is not tested in production.
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
(6) “VID” is input differential voltage (input overdrive).
6
Submit Documentation Feedback
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
www.ti.com
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
2.7V ELECTRICAL CHARACTERISTICS
Single Supply with VS = 2.7V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150Ω to V− unless otherwise specified.
(1)
Boldface limits apply at temperature extremes.
(2)
(2)
(2)
Symbol
Parameter
Condition
Min
Typ
Max
Units
Frequency Domain Response
SSBW
–3 dB Bandwidth Small Signal
VOUT = 0.25 VPP
120
MHz
SSBW_1
Peak
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP, AV = +1
VOUT = 0.25 VPP
250
3.1
0.1
73
0
Peaking
dB
dB
Peak_1
LSBW
Peaking
–3 dB Bandwidth Large Signal
Peaking
VOUT = 2 V PP
MHz
dB
Peak_2
0.1 dB BW
GBWP_1k
GBWP_150
AVOL
VOUT = 2 VPP
0.1 dB Bandwidth
Gain Bandwidth Product
VOUT = 2VPP
30
110
81
65
13
MHz
Unity Gain, RL = 1 kΩ to VS/2
Unity Gain, RL = 150Ω to VS/2
0.25V < VOUT < 2.5V
MHz
Large Signal Open Loop Gain
Full Power BW
56
dB
PBW
–1 dB, AV = +4, VOUT = 2 VPP
,
MHz
RL = 150Ω to VS/2
DG
DP
Differential Gain
4.43 MHz, 0.45V ≤ VOUT ≤ 2.05V
RL = 150Ω to V−
0.12
0.62
%
Differential Phase
4.43 MHz, 0.45V ≤ VOUT ≤ 2.05V
RL = 150Ω to V−
deg
Time Domain Response
TRS/TRL
OS
Rise & Fall Time
0.25V Step
2.7
10
ns
%
Overshoot
Slew Rate
Settling Time
0.25V Step
SR
2V Step
260
147
410
3.4
V/μs
TS
1V Step, ±0.1%
1V Step, ±0.02%
Input to Output, 250 mV Step, 50%
ns
ns
TS_1
PD
Propagation Delay
Distortion & Noise Performance
HD2
HD3
VN1
VN2
IN
Harmonic Distortion (2nd
Harmonic Distortion (3rd)
)
1 VPP, 10 MHz
1 VPP, 10 MHz
>10 MHz
−58
−60
8.4
12
dBc
dBc
Input Voltage Noise
nV/√Hz
fA/√Hz
1 MHz
Input Current Noise
>1 MHz
50
Static, DC Performance
VIO
Input Offset Voltage
±1
±3.5
±6.5
mV
(3)
DVIO
IB
Input Offset Voltage Average Drift See
−6.5
5
μV/°C
pA
(4)
Input Bias Current
Input Offset Current
Input Resistance
Input Capacitance
See
See
50
(4)
IOS
2
25
pA
RIN
0V ≤ VIN ≤ 1.2V
20
1.6
68
TΩ
CIN
pF
+PSRR
Positive Power Supply Rejection
Ratio
DC
58
53
dB
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
(3) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(4) This parameter is ensured by design and/or characterization and is not tested in production.
Copyright © 2006–2013, Texas Instruments Incorporated
Submit Documentation Feedback
7
Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
www.ti.com
2.7V ELECTRICAL CHARACTERISTICS (continued)
Single Supply with VS = 2.7V, AV = +2, RF = 604Ω, SD tied to V+, VOUT = VS/2, RL = 150Ω to V− unless otherwise specified.
Boldface limits apply at temperature extremes. (1)
(2)
(2)
(2)
Symbol
−PSRR
Parameter
Condition
Min
56
53
Typ
69
Max
Units
dB
Negative Power Supply Rejection
Ratio
DC
CMRR
Common Mode Rejection Ratio
DC
57
52
V− -0.20
77
–
dB
CMVR
ICC
Input Voltage Range
Supply Current
CMRR > 50 dB
V+ -1.5
V
Normal Operation
VOUT = VS/2
9.0
10.6
12.5
mA
nA
Shutdown
SD tied to ≤ 0.27V
100
(5)
VOH1
Output High Voltage
(Relative to V+)
RL = 150Ω to V–
–260
–420
–200
VOH2
VOH3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
–200
–10
mV
mV
–50
100
VOL1
Output Low Voltage
(Relative to V–)
RL = 150Ω to V–
+4
+45
+125
VOL2
VOL3
RL = 75Ω to VS/2
RL = 10 kΩ to V–
+125
+4
+45
125
IO
Output Current
V
OUT ≤ 0.6V from Respective Source
25
62
Supply
Sink
mA
IO_1
VOUT = VS/2, VID = ±18 mV
Source
Sink
25
35
(6)
Load
Output Load Rating
Output Resistance
THD < −30 dBc, f = 200 kHz, RL tied to
VS/2, VOUT = 2.2 VPP
40
Ω
RO_Enable
Enabled, AV = +1
Shutdown
0.2
>100
5.6
Ω
RO_Disabled Output Resistance
CO_Disabled Output Capacitance
Miscellaneous Performance
MΩ
pF
Shutdown
(5)
VDMAX
VDMIN
Ii
Voltage Limit for Disable (Pin 5)
See
0
0.27
2.7
V
V
(5)
Voltage Limit for Enable (Pin 5)
Logic Input Current (Pin 5)
Turn-on Glitch
See
2.43
(5)
SD = 2.7V
4
pA
V
V_glitch
Ton
1.2
5.2
760
60
Turn-on Time
µs
ns
dB
Toff
Turn-off Time
IsolationOFF
Off Isolation
1 MHz, RL = 1 kΩ
(5) SD logic is CMOS compatible. To ensure proper logic level and to minimize power supply current, SD should typically be less than 10%
of total supply voltage away from either supply rail.
(6) “VID” is input differential voltage (input overdrive).
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SNOSAK9E –JUNE 2006–REVISED MARCH 2013
CONNECTION DIAGRAM
6
+
1
V
OUTPUT
5
SD
-
2
3
V
-
+
4
-IN
+IN
Figure 2. 6-Pin SC70-Top View
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TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, all data is with AV = +2, RF = RG = 604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T =
25°C.
Frequency Response for Various Output Amplitudes
Frequency Response for Various Output Amplitudes
3
3
80
80
V
= 3.3V
V
= 5V
S
S
GAIN
GAIN
0
-3
40
0
0
-3
40
0.25 V
PP
0
0.25 V
PHASE
PP
PHASE
-6
-40
-40
-80
-120
-160
-200
-6
1 V
PP
-9
-80
-9
1 V
PP
2 V
PP
-12
-120
-160
-200
-12
-15
-18
2 V
PP
-15
-18
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 3.
Figure 4.
−3 dB BW
vs.
Frequency Response for Various Output Amplitudes
Supply Voltage for Various Output Swings
150
3
80
V
= 2.7V
A = +2
V
S
GAIN
0.25 V
PP
0
-3
40
0.25 V
PP
125
0
PHASE
-40
-80
-120
-160
-200
-6
100
75
1 V
PP
1 V
PP
-9
2 V
PP
-12
-15
-18
2 V
PP
50
2.5
3
3.5
4
4.5
5
1
10
100
1000
V
(V)
S
FREQUENCY (MHz)
Figure 5.
Figure 6.
Non-inverting Frequency Response for Various Gain
Inverting Frequency Response for Various Gain
3
60
3
0
60
A
= +1
V
GAIN
GAIN
A
V
= +2
0
40
40
A
= -1
= -2
= -5
V
A
= +5
V
-3
20
-3
20
PHASE
PHASE
A
= +10
V
A
A
V
-6
0
-6
0
-9
-20
-40
-60
-80
-100
-9
-20
-40
-60
-80
-100
V
A
= +1
V
-12
-15
-18
-21
-12
-15
-18
-21
A
= +2
V
A
= +5
V
A
= -10
V
A
= +10
V
V
= 0.25 V
PP
V
= 0.25 V
OUT PP
OUT
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7.
Figure 8.
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SNOSAK9E –JUNE 2006–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T =
25°C.
Frequency Response for Various Loads
Frequency Response for Various Supply Voltages
6
6
30
2.7V
V
= 0.25 V
PP
PHASE
GAIN
OUT
-
3
0
3
0
R
TIED TO V
L
3.3V
5V
0
-30
1 kW
-3
-3
-60
50W
150W
-6
-6
-90
-9
-9
-120
-150
-180
-210
2.7V
3.3V
5V
100
-12
-15
-18
-12
-15
-18
A
V
= +1
V
= 0.25 V
OUT
PP
1
10
100
1000
1
10
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 9.
Figure 10.
−3 dB BW
vs.
Ambient Temperature
Frequency Response for Various Cap Load
6
140
130
20 pF
10 pF
3
5V
5 pF
0
-3
0 pF
120
110
3.3V
-6
-9
100
20 pF
0 pF
-12
-15
-18
90
80
A
V
= +2
V
V
= 0.25 V
PP
OUT
-
= 2 V
OUT
PP
R
= 1 kW || C to V
L
L
100
-40 -20
0
20
40
60
80
1
10
100
1000
TEMPERATURE (°C)
FREQUENCY (MHz)
Figure 11.
Figure 12.
Max Output Swing
vs.
Frequency Response for Various Supply Voltage
Frequency
7
6
5
4
3
2
1
0
6
5
2.7V
4
THD < -30 dBc
5V
3
3.3V
2
1
V
= 5V
= +2
S
A
V
0
R
L
= 150W to V /2
S
-1
10k
100k
1M
10M
100M
1
10
100
1000
FREQUENCY (Hz)
FREQUENCY (MHz
Figure 13.
Figure 14.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T =
25°C.
Peak Output Swing
Output Swing
vs.
RL
vs.
Sink Current for Various Supply Voltages
2.5
2
1
5V
3.3V
3.3V
5V
1.5
1
2.7V
0.1
A
V
= +5 V/V
R
to V /2
S
L
V
_DC = V /2
OUT
0.5
S
UNDISORTED OUTPUT SWING
(LIMITED BY SOURCE CURRENT)
0.01
0
20
40
60
80
100
0
10 20 30 40 50 60 70 80 90 100
(W)
I
(mA)
SINK
R
L
Figure 15.
Figure 16.
Output Swing
HD2
vs.
Frequency
vs.
Source Current for Various Supply Voltages
-30
-35
10
V
= 2 V
OUT
PP
-40
-45
-50
-55
-60
-65
-70
-75
1
3.3V
2.7V
5V
5V
0.1
-80
-85
-90
3.3V
0.01
1
100
10
0.1
0
20
40
60
80
100
FREQUENCY (MHz)
I
(mA)
SOURCE
Figure 17.
Figure 18.
HD3
vs.
Frequency
THD
vs.
Output Swing
-30
-35
-40
V
= 2 V
OUT
PP
R
L
= 1 kW to V /2
S
V
= 5V
S
-50
-60
-40
-45
-50
-55
-60
-65
10 MHz
2.7V
-70
-80
3.3V
-70
-75
-80
-85
-90
1 MHz
-90
5V
-100
1
100
10
0
0.5
1
1.5
2
2.5
3
3.5
)
4
4.5 5
0.1
FREQUENCY (MHz)
OUTPUT (V
PP
Figure 19.
Figure 20.
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SNOSAK9E –JUNE 2006–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T =
25°C.
THD
vs.
Output Swing
Slew Rate
vs.
Ambient Temperature
310
290
-20
-30
-40
R
= 1 kW to V /2
L
S
5V, FALLING
V
= 3.3V
S
270
3.3V, FALLING
5V, RISING
-50
-60
250
230
210
3.3V RISING
10 MHz
-70
-80
190
170
A
V
= +2
V
-90
1 MHz
= 2 V
PP
OUT
150
-40 -20
-100
0
20
40
60 80 100
0
0.5
1
2
2.5
3
1.5
TEMPERATURE (°C)
OUTPUT (V
)
PP
Figure 21.
Figure 22.
Settling Time (±1%)
vs.
Output Swing
Output Settling
80
70
60
A
= -1
V
R
= 150W to V /2
L
S
V
= 5V
S
50
40
30
20
10
V
= 5V
S
R
= 150W to V /2
L
S
A
V
= -1
V
= 1 V
PP
OUT
0
0
TIME (20 ns/DIV)
0.5
1
1.5
2
2.5
(V
3
3.5
4
4.5 5
V
)
OUT PP
Figure 23.
Figure 24.
Isolation Resistor & Settling Time
Isolation Resistor & Settling Time
vs.
CL
25
vs.
CL
25
250
200
250
200
SETTLING TIME
SETTLING TIME
20
20
10% OVERSHOOT
10% OVERSHOOT
ACROSS C
L
150
100
50
15
10
5
150
100
50
15
10
ACROSS C
L
A
= -1
A = -1
V
V
R
= R = 1 kW
F
R
= R = 1 kW
F
L
L
V
V
= 5V
V
V
= 3.3V
S
O
S
O
= 1 V STEP
PP
= 1 V STEP
PP
5
0
ISOLATION RESISTOR
50 100 150
(pF)
ISOLATION RESISTOR
50 100 150
(pF)
0
0
250
0
0
200
0
200
250
C
L
C
L
Figure 25.
Figure 26.
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T =
25°C.
Closed Loop Output Impedance
vs.
Off Isolation
vs.
Frequency for Various Supply Voltages
Frequency
0
100
10
1
V
A
= 5V
= +2
A
= +1
S
V
V
-10
-20
R
R
= R = 510W
F
L
G
= 100 kW
-30
-40
-50
-60
-70
2.7V
3.3V
5V
-80
-90
0.1
100k
1M
10M
100k
10M
100M
100M
100
10k
1M
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 27.
Figure 28.
Noise Voltage
vs.
Frequency
Open Loop Gain/ Phase
10000
1000
100
10
250
200
150
100
50
60
50
40
30
20
10
0
PHASE
2.7V
3.3V
0
GAIN
5V
1
10
1M
100M
500M
1k
100k
10M
10k
10k
100
1k
100k 1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 29.
Figure 30.
CMRR
vs.
Frequency
+PSRR
vs.
Frequency
80
70
90
80
70
60
50
40
30
20
10
0
3.3V
2.7V
60
50
40
30
20
10
0
5V
1M
100M
1k
10k
100k
10M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 31.
Figure 32.
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SNOSAK9E –JUNE 2006–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T =
25°C.
−PSRR
vs.
Frequency
Supply Current vs. Ambient Temperature
10
80
70
60
50
40
30
20
10
0
3.3V
2.7V
9.8
5V
9.6
9.4
5V
3.3V
9.2
9
2.7V
8.8
8.6
8.4
8.2
-40 -20
0
20
40
60
80 100
10k
100k
1M
10M
100M
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 33.
Figure 34.
Supply Current
Supply Current
vs.
Supply Voltage
vs.
VCM
18
12
10
8
V
V
= 5V
S
125°C
16
14
12
10
-
MEASURE FROM V
CM
85°C
-40°C
25°C
6
8
6
4
2
0
25°C
-40°C
4
2
0
5
0
0.5
1
1.5
2
2.5
(V)
3
3.5
4
4.5
1.5
2
2.5
3
3.5
(V)
4
4.5
V
CM
V
S
Figure 35.
Figure 36.
Offset Voltage
vs.
Ambient Temperature
for 3 Representative Units
Offset Voltage Distribution
1.00
0.80
0.60
7
6.5
6
V
S
= 2.7V
UNIT 2
5.5
5
0.40
0.20
4.5
4
UNIT 1
3.5
3
0.00
-0.20
-0.40
-0.60
-0.80
2.5
2
UNIT 3
V
S
= 3.3V
1.5
1
0.5
0
-1.8 -1.4 -1 -0.6 -0.2 0.2 0.6
(mV)
1 1.4 1.8 2.2
-40 -20
0
20
40
60 80 100
V
IO
TEMPERATURE (°C)
Figure 37.
Figure .
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T =
25°C.
Offset Voltage
vs.
VCM (Typical Part)
Input Bias Current
vs.
Common Mode Voltage
4
2
1000
100
10
125°C
85°C
25°C
125°
0
-2
-4
-6
OPERATION IS NOT
RECOMMENDED
-40°C
1
.1
25°C
-8
V
V
= 3.3V
S
-
MEASURED FROM V
V = 5V
S
CM
.01
-10
0
0.5
1
1.5
(V)
2
2.5
-1
0
1
2
3
4
5
6
V
CM
V
(V)
CM
Figure 38.
Figure 39.
Small Signal Step Response
Large Signal Step Response
2.5
2
1.5
V
A
V
= 0.25 V
PP
V
A
V
= 2 V
PP
OUT
OUT
= +2
= +2
V
S
V
S
= 2.7V
= 2.7V
1.4
1.3
1.2
1.5
1
0.5
0
1.1
0
20
40
60
80
100
0
20
40
60
80
100
TIME (ns)
TIME (ns)
Figure 40.
Figure 41.
Large Signal Step Response
Turn On/Off Waveform
2.5
-
R
L
= 100W to V
A
= +1
V
0V
0V
2
1.5
1
V
= ±1.65V
S
R
L
= 150W to V /2
S
0.5
2.5 ms/DIV
0
10
20
30
TIME (ns)
Figure 42.
Figure 43.
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SNOSAK9E –JUNE 2006–REVISED MARCH 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted, all data is with AV = +2, RF = RG = 604Ω, VS = 3.3V, VOUT = VS/2, SD tied to V+, RL = 150Ω to V−, T =
25°C.
DG
vs.
DP
vs.
VOUT for Various VS
VOUT for Various VS
0.2
0.1
0.2
0.1
-
V = 5V
S
R
= 150W TO V
L
DC COUPLED
DG MEASURED RELATIVE
0
TO V
OUT
= V /2 IN EACH
S
CASE
-0.1
V
= 2.5V
S
V
= 3.3V
-
S
0
-0.1
-0.2
-0.2
-0.3
V
= 5V
S
R
L
= 150W TO V
V
= 3.3V
S
DC COUPLED
DP MEASURED
-0.4
V
= 2.5V
RELATIVE TO V
=
S
OUT
-0.5
-0.6
V /2 IN EACH CASE
S
-2.5 -2 -1.5 -1 -0.5
0
0.5
1
1.5
2
-2.5 -2 -0.5 -1 -0.5
0
0.5
1
1.5
2
V
FROM V /2 (V)
V
FROM V /2 (V)
OUT
S
OUT
S
Figure 44.
Figure 45.
DG
vs.
DP
vs.
VOUT (DC and AC Coupled Load Compared)
VOUT (DC and AC Coupled Load Compared)
0.4
1
V
= 5V
S
0.8
R
L
= 150W
DG MEASURED
AC COUPLED
0.6
0.3
0.2
RELATIVE TO V
IN EACH CASE
= V /2
S
OUT
0.4
DC COUPLED
0.2
0
0.1
0
-0.2
AC COUPLED
-0.4
-0.6
-0.8
-1
V
= 5V
S
R
= 150W
L
-0.1
-0.2
DC COUPLED
DP MEASURED RELATIVE TO
V
= V /2 IN EACH CASE
OUT
S
-1
-0.6
-0.2
0.2
0.6
1
1
-1
-0.6
-0.2
0.2
0.6
V
FROM V /2 (V)
S
V
FROM V /2 (V)
OUT
OUT
S
Figure 46.
Figure 47.
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APPLICATION INFORMATION
OPTIMIZING PERFORMANCE
With many op amps, additional device non-linearity and sometimes less loop stability arises when the output has
to switch from current-source mode to current-sink mode or vice versa. When it comes to achieving the lowest
distortion and the best Differential Gain/ Differential Phase (DG/ DP, broadcast video specs), the LMH6601 is
optimized for single supply DC coupled output applications where the load current is returned to the negative rail
(V−). That is where the output stage is most linear (lowest distortion) and which corresponds to unipolar current
flowing out of this device. To that effect, it is easy to see that the distortion specifications improve when the
output is only sourcing current which is the distortion-optimized mode of operation for the LMH6601. In
application where the LMH6601 output is AC coupled or when it is powered by separate dual supplies for V+ and
V−, the output stage supplies both source and sink current to the load and results in less than optimum distortion
(and DG/DP). Figure 48 compares the distortion results between a DC and an AC coupled load to show the
magnitude of this difference. See the DG/DP plots, Figure 44 through Figure 47, in TYPICAL PERFORMANCE
CHARACTERISTICS, for a comparison between DC and AC coupling of the video load.
-20
V
V
V
= 3.3V
S
-30
-40
-50
-60
-70
-80
-90
-100
= 2 V
PP
OUT
OUT
_DC = V /2
S
HD3, AC COUPLED
HD2, AC COUPLED
HD3, DC COUPLED
HD2, DC COUPLED
0.1
1
10
100
FREQUENCY (MHz)
Figure 48. Distortion Comparison between DC & AC Coupling of the Load
In certain applications, it may be possible to optimize the LMH6601 for best distortion (and DG/DP) even though
the load may require bipolar output current by adding a pull-down resistor to the output. Adding an output pull-
down resistance of appropriate value could change the LMH6601 output loading into source-only. This comes at
the price of higher total power dissipation and increased output current requirement.
Figure 49 shows how to calculate the pull-down resistor value for both the dual supply and for the AC coupled
load applications.
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+
+
V
V
I
L-MAX
C
O
V
V
O
O
LMH6601
LMH6601
R
P
R
L
R
P
R
L
-
V
-
V
(a) DUAL SUPPLY
(b) AC COUPLED LOAD
«
∆
∆
≈
V-
VO_MIN
≈
∆
-1
R
RP
RP
Ç
Ç
L ∆VO_MIN
IL_MAX
«
V
is the most
O_MIN
negative swing at output
V
is the most
O_MIN
negative swing at output
and I
is maximum load
L_MAX
current with direction shown
Figure 49. Output Pull-Down Value for Dual Supply & AC Coupling
Furthermore, with a combination of low closed loop gain setting (i.e. AV = +1 for example where device
bandwidth is the highest), light output loading (RL > 1 kΩ) , and with a significant capacitive load (CL > 10 pF) ,
the LMH6601 is most stable if output sink current is kept to less than about 5 mA. The pull-down method
described in Figure 49 is applicable in these cases as well where the current that would normally be sunk by the
op amp is diverted to the RP path instead.
SHUTDOWN CAPABILITY AND TURN ON/ OFF BEHAVIOR
With the device in shutdown mode, the output goes into high impedance (ROUT > 100 MΩ) mode. In this mode,
the only path between the inputs and the output pin is through the external components around the device. So,
for applications where there is active signal connection to the inverting input, with the LMH6601 in shutdown, the
output could show signal swings due to current flow through these external components. For non-inverting
amplifiers in shutdown, no output swings would occur, because of complete input-output isolation, with the
exception of capacitive coupling.
For maximum power saving, the LMH6601 supply current drops to around 0.1 μA in shutdown. All significant
power consumption within the device is disabled for this purpose. Because of this, the LMH6601 turn on time is
measured in micro-seconds whereas its turn off is fast (nano-seconds) as would be expected from a high speed
device like this.
The LMH6601 SD pin is a CMOS compatible input with a pico-ampere range input current drive requirement.
This pin needs to be tied to a level or otherwise the device state would be indeterminate. The device shutdown
threshold is half way between the V+ and V− pin potentials at any supply voltage. For example, with V+ tied to
10V and V− equal to 5V, you can expect the threshold to be at 7.5V. The state of the device (shutdown or normal
operation) is ensured over temperature as longs as the SD pin is held to within 10% of the total supply voltage.
For V+ = 10V, V− = 5V, as an example:
•
•
Shutdown Range 5V ≤ SD ≤ 5.5V
Normal Operation Range 9.5V ≤ SD ≤ 10V
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OVERLOAD RECOVERY AND SWING CLOSE TO RAILS
The LMH6601 can recover from an output overload in less than 20 ns. See Figure 50 below for the input and
output scope photos:
V
= ±2.5V
S
INPUT (4 V
)
OUTPUT (1V/DIV)
PP
TIME (10 ns/DIV)
Figure 50. LMH6601 Output Overload Recovery Waveform
In Figure 50, the input step function is set so that the output is driven to one rail and then the other and then the
output recovery is measured from the time the input crosses 0V to when the output reaches this point.
Also, when the LMH6601 input voltage range is exceeded near the V+ rail, the output does not experience output
phase reversal, as some op amps do. This is particularly advantageous in applications where output phase
reversal has to be avoided at all costs, such as in servo loop control among others. This adds to the LMH6601’s
set of features which make this device easy to use.
In addition, the LMH6601’s output swing close to either rail is well-behaved as can be seen in the scope photo of
Figure 51.
0V
0V
V
S
= ±2.5V
1 ms/DIV
Figure 51. LMH6601’s “Clean” Swing to Either Rail
With some op amps, when the output approaches either one or both rails and saturation starts to set in, there is
significant increase in the transistor parasitic capacitances which leads to loss of Phase Margin. That is why with
these devices, there are sometimes hints of instability with output close to the rails. With the LMH6601, as can
be seen in Figure 51, the output waveform remains free of instability throughout its range of voltages.
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SINGLE SUPPLY VIDEO APPLICATION
The LMH6601’s high speed and fast slew rate make it an ideal choice for video amplifier and buffering
applications. There are cost benefits in having a single operating supply. Single supply video systems can take
advantage of the LMH6601’s low supply voltage operation along with its ability to operate with input common
mode voltages at or slightly below the V− rail. Additional cost savings can be achieved by eliminating or reducing
the value of the input and output AC coupling capacitors commonly employed in single supply video applications.
This APPLICATION INFORMATION shows some circuit techniques used to help in doing just that.
DC COUPLED, SINGLE SUPPLY BASEBAND VIDEO AMPLIFIER/DRIVER
The LMH6601 output can swing very close to either rail to maximize the output dynamic range which is of
particular interest when operating in a low voltage single supply environment. Under light output load conditions,
the output can swing as close as a few milli-volts of either rail. This also allows a video amplifier to preserve the
video black level for excellent video integrity. In the example shown below in Figure 52, the baseband video
output is amplified and buffered by the LMH6601 which then drives the 75Ω back terminated video cable for an
overall gain of +1 delivered to the 75Ω load. The input video would normally have a level between 0V to
approximately 0.75V.
V
= 2.7V
S
VIDEO IN (0-0.75V)
75W CABLE
+
V
LOAD
LMH6601
R
75W
-
S
R
75W
T
R
75W
L
R
620W
F
R
620W
G
Figure 52. Single Supply Video Driver Capable of Maintaining Accurate Video Black Level
With the LMH6601 input common mode range including the V− (ground) rail, there will be no need for AC
coupling or level shifting and the input can directly drive the non-inverting input which has the additional
advantage of high amplifier input impedance. With LMH6601’s wide rail-to-rail output swing, as stated earlier, the
video black level of 0V is maintained at the load with minimal circuit complexity and using no AC coupling
capacitors. Without true rail-to-rail output swing of the LMH6601, and more importantly without the LMH6601’s
ability of exceedingly close swing to V−, the circuit would not operate properly as shown at the expense of more
complexity. This circuit will also work for higher input voltages. The only significant requirement is that there is at
least 1.8V from the maximum input voltage to the positive supply (V+).
The Composite Video Output of some low cost consumer video equipment consists of a current source which
develops the video waveform across a load resistor (usually 75Ω), as shown in Figure 53 below. With these
applications, the same circuit configuration just described and shown in Figure 53 will be able to buffer and drive
the Composite Video waveform which includes sync and video combined. However, with this arrangement, the
LMH6601 supply voltage needs to be at least 3.3V or higher in order to allow proper input common mode voltage
headroom because the input can be as high as 1V peak.
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VIDEO DAC
CURRENT
OUTPUT
V
S
= 3.3V
COMPOSITE
VIDEO IN 0-1V
+
V
LOAD
i
O
LMH6601
U1
75W
R
S
75W
-
R
L
75W
R
620W
F
R
620W
G
Figure 53. Single Supply Composite Video Driver for Consumer Video Outputs
If the “Video In” signal is Composite Video with negative going Sync tip, a variation of the previous configurations
should be used. This circuit produces a unipolar (above 0V) DC coupled single supply video signal as shown in
Figure 54.
3.3V
R
30 kW
1
V
S
= 3.3V
0.8V
PP
0.61V œ 1.41V
0V - 2V
V
LOAD
+
LMH6601
R
10 kW
U1
2
R
75W
-
S
R
L
3.3V
75W
R
3
1.3 kW
VIDEO IN
-0.3V to 0.75V
R
620W
F
R
T
75W
R
560W
G
Figure 54. Single Supply DC Coupled Composite Video Driver for Negative Going Sync Tip
In the circuit of Figure 54, the input is shifted positive by means of R1, R2, and RT in order to satisfy U1’s
Common Mode input range. The signal will loose 20% of its amplitude in the process. The closed loop gain of U1
will need to be set to make up for this 20% loss in amplitude. This gives rise to the gain expression shown below
which is based on a getting a 2 VPP output with a 0.8 VPP input:
2V
R
F
-1 = 1.5V/V
=
0.8V
R ||R
G
3
(1)
R3 will produce a negative shift at the output due to VS (3.3V in this case). R3 will need to be set so that the
“Video In” sync tip (−0.3V at RT or 0.61V at U1 non-inverting input) corresponds to near 0V at the output.
«
∆
«
∆
∆
≈
≈
1 +
≈
RF
R3
0.61
RF
RG
RF
RG
∆
∆
∆
1 +
=
= 0.227
3.3V œ 0.61 ∆
∆
«
≈
«
(2)
Equation 1 and Equation 2 need to be solved simultaneously to arrive at the values of R3, RF, and RG which will
satisfy both. From the datasheet, one can set RF = 620Ω to be close to the recommended value for a gain of +2.
It is easier to solve for RG and R3 by starting with a good estimate for one and iteratively solving Equation 1 and
Equation 2 to arrive at the results. Here is one possible iteration cycle for reference:
RF = 620Ω
(3)
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Table 1. Finding Figure 54 External Resistor Values by Iteration
Estimate
RG (Ω)
Calculated
(from Equation 2)
R3 (Ω)
Equation 1 LHS
Calculated
Comment
(Compare Equation 1 LHS Calculated to RHS)
1k
1.69k
1.56k
1.37k
239
0.988
1.15
1.45
4.18
1.59
Increase Equation 1 LHS by reducing RG
Increase Equation 1 LHS by reducing RG
Increase Equation 1 LHS by reducing RG
Reduce Equation 1 LHS by increasing RG
Close to target value of 1.5V/V for Equation 1
820
620
390
560
1.30k
The final set of values for RG and R3 in Table 1 are values which will result in the proper gain and correct video
levels (0V to 1V) at the output (VLOAD).
AC COUPLED VIDEO
Many monitors and displays accept AC coupled inputs. This simplifies the amplification and buffering task in
some respects. As can be seen in Figure 55, R1 and R2 simply set the input to the center of the input linear
range while CIN AC couples the video onto the op amp’s input. The op amp is set for a closed loop gain of 2 with
RF and RG. CG is there to make sure the device output is also biased at mid-supply. Because of the DC bias at
the output, the load needs to be AC coupled as well through CO. Some applications implement a small valued
ceramic capacitor (not shown) in parallel with CO which is electrolytic. The reason for this is that the ceramic
capacitor will tend to shunt the inductive behavior of the Electrolytic capacitor at higher frequencies for an
improved overall low impedance output.
CG2 is intended to boost the high frequency gain in order to improve the video frequency response. This value is
to be set and trimmed on the board to meet the application’s specific system requirements.
5V
R
5V
1
C
IN
0.47 mF
510 kW
R
O
CABLE
V
75W
IN
+
LMH6601
V
OUT
R
IN
75W
R
2
510 kW
U1
C
-
O
R
L
220 mF
75W
R
F
620W
R
G
C
G2
620W
+
C
G
47 mF
Figure 55. AC Coupled Video Amplifier/Driver
SAG COMPENSATION
The capacitors shown in Figure 55 (except CG2), and especially CO, are the large electrolytic type which are
considerably costly and take up valuable real estate on the board. It is possible to reduce the value of the output
coupling capacitor, CO, which is the largest of all, by using what is called SAG compensation. SAG refers to what
the output video experiences due to the low frequency video content it contains which cannot adequately go
through the output AC coupling scheme due to the low frequency limit of this circuit. The −3 dB low frequency
limit of the output circuit is given by:
f_low_frequency (−3 dB)= 1/ (2*pi* 75*2(Ω) * CO) = ∼ 4.82 Hz For CO = 220 μF
(4)
A possible implementation of the SAG compensation is shown in Figure 56.
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V
_5V
CC
R
V
_5V
1
CC
C
IN
C
68 mF
+
O
510 kW
R
0.47 mF
O
75W
CABLE
V
IN
+
V
-
O
LMH6601
V
L
R
2
510 kW
R
T
75W
U1
-
R
75W
L
R
4
R
1 kW
3
2 kW
C
1
22 mF
-
+
R
5
680W
Figure 56. AC Coupled Video Amplifier/Driver with SAG Compensation
In this circuit, the output coupling capacitor value and size is reduced at the expense of a slightly more
complicated circuitry. Note that C1 is not only part of the SAG compensation, but it also sets the amplifier’s DC
gain to 0 dB so that the output is set to mid-rail for linearity purposes. Also note that exceptionally high values
are chosen for the R1 and R2 biasing resistors (510 kΩ). The LMH6601 has extremely low input bias current
which allows this selection thereby reducing the CIN value in this circuit such that CIN can even be a non-polar
capacitors which will reduce cost.
At high enough frequencies where both CO and C1 can be considered to be shorted out, R3 shunts R4 and the
closed loop gain is determined by:
Closed_loop_Gain (V/V)= VL/VIN = (1+ (R3||R4)/ R5)x [RL/(RL+RO)]= 0.99V/V
(5)
At intermediate frequencies, where the CO, RO, RL path experiences low frequency gain loss, the R3, R5, C1 path
provides feedback from the load side of CO. With the load side gain reduced at these lower frequencies, the
feedback to the op amp inverting node reduces, causing an increase at the op amp's output as a response.
For NTSC video, low values of CO influence how much video black level shift occurs during the vertical blanking
interval (∼1.5 ms) which has no video activity and thus is sensitive to CO's charge dissipation through the load
which could cause output SAG. An especially tough pattern is the NTSC pattern called “Pulse & Bar.” With this
pattern the entire top and bottom portion of the field is black level video where, for about 11 ms, CO is
discharging through the load with no video activity to replenish that charge.
Figure 57 shows the output of the Figure 56 circuit highlighting the SAG.
Figure 57. AC Coupled Video Amplifier/Driver Output Scope Photo Showing Video SAG
With the circuit of Figure 56 and any other AC coupled pulse amplifier, the waveform duty cycle variations exert
additional restrictions on voltage swing at any node. This is illustrated in the waveforms shown in Figure 58.
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4.0V (+) CLIPPING
2.5V
(A)
50% DUTY CYCLE
NO CLIPPING
2V
p-p
1.0V (-) CLIPPING
4.0V (+) CLIPPING
(B)
2V
p-p
LOW DUTY CYCLE
CLIPPED POSITIVE
2.5V
1.0V (-) CLIPPING
4.0V (+) CLIPPING
2.5V
(C)
HIGH DUTY CYCLE
CLIPPED NEGATIVE
2V
p-p
1.0V (-) CLIPPING
Figure 58. Headroom Considerations with AC Coupled Amplifiers
If a stage has a 3 VPP unclipped swing capability available at a given node, as shown in Figure 58, the maximum
allowable amplitude for an arbitrary waveform is ½ of 3V or 1.5 VPP. This is due to the shift in the average value
of the waveform as the duty cycle varies. Figure 58 shows what would happen if a 2 VPP signal were applied. A
low duty cycle waveform, such as the one in Figure 58B, would have high positive excursions. At low enough
duty cycles, the waveform could get clipped on the top, as shown, or a more subtle loss of linearity could occur
prior to full-blown clipping. The converse of this occurs with high duty cycle waveforms and negative clipping, as
depicted in Figure 58C.
HOW TO PICK THE RIGHT VIDEO AMPLIFIER
Apart from output current drive and voltage swing, the op amp used for a video amplifier/cable driver should also
possess the minimum requirement for speed and slew rate. For video type loads, it is best to consider Large
Signal Bandwidth (or LSBW in the Texas Instruments data sheet tables) as video signals could be as large as 2
VPP when applied to the commonly used gain of +2 configuration. Because of this relatively large swing, the op
amp Slew Rate (SR) limitation should also be considered. Table 2 shows these requirements for various video
line rates calculated using a rudimentary technique and intended as a first order estimate only.
Table 2. Rise Time, −3 dB BW, and Slew Rate Requirements for Various Video Line Rates
Video
Standard
Line Rate
(HxV)
Refresh Rate Horizontal
Vertical
Active (KV%)
Pixel Time
(ns)
Rise Time
(ns)
LSBW
(MHz)
SR
(V/μs)
(Hz)
Active
(KH%)
TV_NTSC
VGA
451x483
640x480
30
75
75
75
75
75
84
80
76
77
75
74
92
95
96
95
96
96
118.3
33.0
20.3
12.4
7.3
39.4
11.0
6.8
9
41
32
146
237
387
655
973
SVGA
XGA
800x600
52
1024x768
1280x1024
1600x1200
4.1
85
SXGA
UXGA
2.4
143
213
4.9
1.6
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For any video line rate (HxV corresponding to the number of Active horizontal and vertical lines), the speed
requirements can be estimated if the Horizontal Active (KH%) and Vertical Active (KV%) numbers are known.
These percentages correspond to the percentages of the active number of lines (horizontal or vertical) to the total
number of lines as set by VESA standards. Here are the general expressions and the specific calculations for the
SVGA line rate shown in Table 2.
1
x KH x KV
REFRESH_RATE
5
x 1 x 10
PIXEL_TIME (ns) =
H x V
1
x 76 x 96
75 Hz
5
=
x 1 x 10 = 20.3 ns
800 x 600
(6)
Requiring that an “On” pixel is illuminated to at least 90% of its final value before changing state will result in the
rise/fall time equal to, at most, ⅓ the pixel time as shown below:
PIXEL_TIME
20.3 ns
6.8 ns
=
=
RISE/FALL_TIME =
3
3
(7)
Assuming a single pole frequency response roll-off characteristic for the closed loop amplifier used, we have:
0.35
0.35
52 MHz
=
=
-3 dB_BW =
RISE/FALL_TIME
6.8 ns
(8)
Rise/Fall times are 10%-90% transition times, which for a 2 VPP video step would correspond to a total voltage
shift of 1.6V (80% of 2V). So, the Slew Rate requirement can be calculated as follows:
1.6V
1.6V
x 1 x 103
237(V/ms)
=
=
SR(V/ms) =
RISE/FALL_TIME (ns)
6.8 ns
(9)
The LMH6601 specifications show that it would be a suitable choice for video amplifiers up to and including the
SVGA line rate as demonstrated above.
For more information about this topic and others relating to video amplifiers, see Application Note 1013
(SNVA031).
CURRENT TO VOLTAGE CONVERSION (TRANSIMPEDANCE AMPLIFIER (TIA))
Being capable of high speed and having ultra low input bias current makes the LMH6601 a natural choice for
Current to Voltage applications such as photodiode I-V conversion. In these type of applications, as shown in
Figure 59 below, the photodiode is tied to the inverting input of the amplifier with RF set to the proper gain (gain
is measured in Ohms).
C
F
R
F
-
D
LMH6601
1
V
OUT
U1
C
D
C
A
+
V
BIAS
Figure 59. Typical Connection of a Photodiode Detector to an op amp
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With the LMH6601 input bias current in the femto-amperes range, even large values of gain (RF) do not increase
the output error term appreciably. This allows circuit operation to a lower light intensity level which is always of
special importance in these applications. Most photo-diodes have a relatively large capacitance (CD) which would
be even larger for a photo-diode designed for higher sensitivity to light because of its larger area. Some
applications may run the photodiode with a reverse bias in order to reduce its capacitance with the disadvantage
of increased contributions from both dark current and noise current. Figure 60 shows a typical photodiode
capacitance plot vs. reverse bias for reference.
600
T = 23°C
PIN-RD100
500
400
300
200
PIN-RD100A
PIN-RD15
PIN-RD07
100
0
0.1
1
10
100
REVERSED BIAS VOLTAGE (V)
Figure 60. Typical Capacitance vs. Reverse Bias (Source: OSI Optoelectronics)
The diode capacitance (CD) along with the input capacitance of the LMH6601 (CA) has a bearing on the stability
of this circuit and how it is compensated. With large transimpedance gain values (RF), the total combined
capacitance on the amplifier inverting input (CIN = CD + CA) will work against RF to create a zero in the Noise
Gain (NG) function (see Figure 61). If left untreated, at higher frequencies where NG equals the open loop
transfer function there will be excess phase shift around the loop (approaching 180°) and therefore, the circuit
could be unstable. This is illustrated in Figure 61.
OP AMP OPEN
LOOP GAIN
I-V GAIN (W)
NOISE GAIN (NG)
1 + sR (C + C )
IN
F
F
1 + sR C
F
F
C
IN
1 +
C
F
0 dB
1
GBWP
1
FREQUENCY
f
@
f
=
z
P
2pR C
F F
2pR C
IN
F
Figure 61. Transimpedance Amplifier Graphical Stability Analysis and Compensation
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Figure 61 shows that placing a capacitor, CF, with the proper value, across RF will create a pole in the NG
function at fP. For optimum performance, this capacitor is usually picked so that NG is equal to the op amp's
open loop gain at fP. This will cause a “flattening” of the NG slope beyond the point of intercept of the two plots
(open loop gain and NG) and will results in a Phase Margin (PM) of 45° assuming fP and fZ are at least a decade
apart. This is because at the point of intercept, the NG pole at fP will have a 45° phase lead contribution which
leaves 45° of PM. For reference, Figure 61 also shows the transimpedance gain (I-V (Ω))
Here is the theoretical expression for the optimum CF value and the expected −3 dB bandwidth:
CIN
CF =
2p(GBWP)RF
(10)
GBWP
@
f
-3 dB
2pR C
F
IN
(11)
Table 3, below, lists the results, along with the assumptions and conditions, of testing the LMH6601 with various
photodiodes having different capacitances (CD) at a transimpedance gain (RF) of 10 kΩ.
Table 3. Transimpedance Amplifier Figure 59 Compensation and Performance Results
CD
(pF)
CIN
(pF)
CF_Calculated
(pF)
CF used
(pF)
−3 dB BW
Calculated (MHz)
−3 dB BW
Measured (MHz)
Step Response
Overshoot (%)
10
50
12
52
1.1
2.3
7.2
1
3
8
14
7
15
7.0
2.5
6
4
9
500
502
2
CA = 2 pF GBWP = 155 MHz VS = 5V
(12)
TRANSIMPEDANCE AMPLIFIER NOISE CONSIDERATIONS
When analyzing the noise at the output of the I-V converter, it is important to note that the various noise sources
(i.e. op amp noise voltage, feedback resistor thermal noise, input noise current, photodiode noise current) do not
all operate over the same frequency band. Therefore, when the noise at the output is calculated, this should be
taken into account.
The op amp noise voltage will be gained up in the region between the noise gain’s “zero” and its “pole” (fz and fp
in Figure 61). The higher the values of RF and CIN, the sooner the noise gain peaking starts and therefore its
contribution to the total output noise would be larger. It is obvious to note that it is advantageous to minimize CIN
(e.g. by proper choice of op amp, by applying a reverse bias across the diode at the expense of excess dark
current and noise). However, most low noise op amps have a higher input capacitance compared to ordinary op
amps. This is due to the low noise op amp’s larger input stage.
28
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Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
www.ti.com
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
OTHER APPLICATIONS
R
R
C
C
= 10 MW to 10 GW
F
= 1 MW or SMALLER FOR HIGH COUNTING RATES
S
= 1 pF
F
= 1 pF to 10 mF
D
V
= Q/C WHERE Q is CHARGE
F
OUT
CREATED BY ONE PHOTON or PARTICLE
ADJUST V FOR MAXIMUM SNR
BIAS
C
F
R
F
C
10 kW
R
S
D
-
LMH6601
V
+
-
OUT
U1
+
1000 pF
D
1
V
BIAS
Figure 62. Charge Preamplifier Taking Advantage of LMH6601’s Femto-Ampere Range Input Bias Current
CAPACITIVE LOAD
The LMH6601 can drive a capacitive load of up to 1000 pF with correct isolation and compensation. Figure 63
illustrates the in-loop compensation technique to drive a large capacitive load.
R
R
F
G
C
F
-
R
S
V
OUT
LMH6601
V
IN
U1
+
R
2 kW
L
C
L
Figure 63. In-Loop Compensation Circuit for Driving a Heavy Capacitive Load
When driving a high capacitive load, an isolation resistor (RS) should be connected in series between the op amp
output and the capacitive load to provide isolation and to avoid oscillations. A small value capacitor (CF) is
inserted between the op amp output and the inverting input as shown such that this capacitor becomes the
dominant feedback path at higher frequency. Together these components allow heavy capacitive loading while
keeping the loop stable.
There are few factors which affect the driving capability of the op amp:
•
•
Op amp internal architecture
Closed loop gain and output capacitor loading
Table 4 shows the measured step response for various values of load capacitors (CL), series resistor (RS) and
feedback resistor (CF) with gain of +2 (RF = RG = 604Ω) and RL = 2 kΩ:
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LMH6601, LMH6601-Q1
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
www.ti.com
Table 4. LMH6601 Step Response Summary for the Circuit of Figure 63
CL
(pF)
RS
(Ω)
CF
(pF)
trise/ tfall
(ns)
Overshoot
(%)
10
50
0
0
1
1
6(1)
7(1)
10
8
6
110
300
500
910
47
6
1
16
20
10
10
10
10
10
12
80
192
33
65
(1) Response limited by input step generator rise time of 5 ns
Figure 64 shows the increase in rise/fall time (bandwidth decrease) at VOUT with larger capacitive loads,
illustrating the trade-off between the two:
70
60
50
40
30
20
10
0
10
100
CAP LOAD C (pF)
1000
L
Figure 64. LMH6601 In-Loop Compensation Response
EVALUATION BOARD
Texas Instruments provides the following evaluation board as a guide for high frequency layout and as an aid in
device testing and characterization. Many of the datasheet plots were measured with this board:
Device
Package
Board Part #
LMH6601MG
SC70-6
LMH730165
30
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Product Folder Links: LMH6601 LMH6601-Q1
LMH6601, LMH6601-Q1
www.ti.com
SNOSAK9E –JUNE 2006–REVISED MARCH 2013
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
Page
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 30
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Product Folder Links: LMH6601 LMH6601-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
LMH6601MG/NOPB
LMH6601MGX/NOPB
LMH6601QMG/NOPB
LMH6601QMGX/NOPB
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SC70
SC70
SC70
SC70
DCK
6
6
6
6
1000
Green (RoHS
& no Sb/Br)
CU SN
CU SN
CU SN
CU SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
A95
A95
ACTIVE
ACTIVE
ACTIVE
DCK
DCK
DCK
3000
1000
3000
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
AKA
AKA
Green (RoHS
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF LMH6601, LMH6601-Q1 :
Catalog: LMH6601
•
Automotive: LMH6601-Q1
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6601MG/NOPB
LMH6601MGX/NOPB
LMH6601QMG/NOPB
LMH6601QMGX/NOPB
SC70
SC70
SC70
SC70
DCK
DCK
DCK
DCK
6
6
6
6
1000
3000
1000
3000
178.0
178.0
178.0
178.0
8.4
8.4
8.4
8.4
2.25
2.25
2.25
2.25
2.45
2.45
2.45
2.45
1.2
1.2
1.2
1.2
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
21-Mar-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
LMH6601MG/NOPB
LMH6601MGX/NOPB
LMH6601QMG/NOPB
LMH6601QMGX/NOPB
SC70
SC70
SC70
SC70
DCK
DCK
DCK
DCK
6
6
6
6
1000
3000
1000
3000
210.0
210.0
210.0
210.0
185.0
185.0
185.0
185.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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