CDCVF2310PW [TI]
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER; 2.5 V至3.3 V高性能时钟缓冲器
| 型号： | CDCVF2310PW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER |
| 文件： | 总16页 (文件大小：736K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCVF2310
www.ti.com
SCAS666C–JUNE 2001–REVISED JANUARY 2008
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
1
FEATURES
PW PACKAGE
(TOP VIEW)
•
High-Performance 1:10 Clock Driver
Operates up to 200 MHz at VDD 3.3 V
Pin-to-Pin Skew < 100 ps at VDD 3.3 V
VDD Range: 2.3 V to 3.6 V
•
•
•
•
•
•
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
VDD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
VDD
1G
CLK
VDD
VDD
2Y0
2Y1
GND
GND
2Y2
2Y3
VDD
VDD
2G
2
3
Operating Temperature Range –40°C to 85°C
Output Enable Glitch Suppression
4
5
6
Distributes One Clock Input to Two Banks of
Five Outputs
7
8
•
•
25-Ω On-Chip Series Damping Resistors
9
Packaged in 24-Pin TSSOP
10
11
12
APPLICATIONS
2Y4
•
General-Purpose Applications
DESCRIPTION
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless
of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a
low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on
the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a
2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable
sequence to distribute full period clock signals.
The CDCVF2310 is characterized for operation from –40°C to 85°C.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCVF2310
www.ti.com
SCAS666C–JUNE 2001–REVISED JANUARY 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTIONAL BLOCK DIAGRAM
3
1Y0
25 Ω
4
1Y1
25 Ω
5
1Y2
25 Ω
8
1Y3
25 Ω
9
1Y4
25 Ω
11
Logic Control
Logic Control
1G
2G
13
24
21
20
17
16
12
2Y0
2Y1
2Y2
2Y3
2Y4
25 Ω
25 Ω
25 Ω
25 Ω
CLK
25 Ω
2
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Product Folder Link(s): CDCVF2310
CDCVF2310
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SCAS666C–JUNE 2001–REVISED JANUARY 2008
FUNCTION TABLE
INPUT
OUTPUT
1G
L
2G
L
CLK
1Y[0:4]
2Y[0:4]
L
↓
↓
↓
↓
L
H
L
L
CLK(1)
L
H
H
L
CLK(1)
CLK(1)
H
CLK(1)
(1) After detecting one negative edge on the CLK input, the output
follows the input CLK if the control pin is held high.
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
1G
11
I
Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the
1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
2G
13
I
Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the
2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
1Y[0:4]
2Y[0:4]
CLK
3, 4, 5, 8, 9
21, 20, 17, 16, 12
24
O
O
I
Buffered output clocks
Buffered output clocks
Input reference frequency
Ground
GND
1, 6, 7, 18, 19
2, 10, 14, 15, 22, 23
VDD
DC power supply, 2.3 V – 3.6 V
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SCAS666C–JUNE 2001–REVISED JANUARY 2008
DETAILED DESCRIPTION
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the
clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative
edge triggered by the input clock) (see Figure 1).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for
predictable operation.
CLK
G
n
n
Y
t
t
h(en)
su(en)
a) Enable Mode
CLK
G
n
n
Y
t
t
h(dis)
su(dis)
b) Disable Mode
Figure 1. Enable and Disable Mode Relative to CLK↓
4
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CDCVF2310
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SCAS666C–JUNE 2001–REVISED JANUARY 2008
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
Supply voltage range, VDD
–0.5 V to 4.6 V
–0.5 V to VDD + 0.5 V
–0.5 V to VDD + 0.5 V
±50 mA
(2)(3)
Input voltage range, VI
(2)(3)
Output voltage range, VO
Input clamp current, IIK (VI < 0 or VI> VDD
)
Output clamp current, IOK (VO < 0 or VO > VDD
)
±50 mA
Continuous total output current, IO (VO = 0 to VDD
Package thermal impedance, θJA(4): PW package
Storage temperature range Tstg
)
±50 mA
120°C/W
–65°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51.
(1)
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
2.3
2.5
3.3
Supply voltage, VDD
V
3.6
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
0.8
V
Low-level input voltage, VIL
0.7
2
1.7
0
High-level input voltage, VIH
Input voltage, VI
V
VDD
12
6
V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
High-level output current, IOH
mA
12
6
Low-level output current, IOL
mA
Operating free-air temperature, TA
–40
85
°C
(1) Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VIK
II
VDD = 3 V,
II = –18 mA
–1.2
±5
V
Input current
VI = 0 V or VDD
µA
µA
pF
pF
(2)
IDD
CI
Static device current
Input capacitance
Output capacitance
CLK = 0 V or VDD
,
IO = 0 mA
80
VDD = 2.3 V to 3.6 V,
VDD = 2.3 V to 3.6 V,
VI = 0 V or VDD
VI = 0 V or VDD
2.5
2.8
CO
(1) All typical values are at respective nominal VDD
.
(2) For ICC over frequency, see Figure 6.
VDD = 3.3 V ±0.3 V
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VDD = min to max,
IOH = –100 µA
IOH = –12 mA
IOH = –6 mA
VDD – 0.2
VOH
High-level output voltage
2.1
2.4
V
VDD = 3 V
(1) All typical values are at respective nominal VDD
.
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VDD = 3.3 V ±0.3 V (continued)
PARAMETER
TEST CONDITIONS
IOL = –100 µA
MIN TYP(1)
MAX UNIT
VDD = min to max,
VDD = 3 V
0.2
VOL
IOH
IOL
Low-level output voltage
High-level output current
Low-level output current
IOL = 12 mA
IOL = 6 mA
VO = 1 V
0.8
V
0.55
VDD = 3 V,
–28
–36
VDD = 3.3 V,
VDD = 3.6 V,
VDD = 3 V,
VO = 1.65 V
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
mA
mA
–14
14
28
VDD = 3.3 V,
VDD = 3.6 V,
36
VDD = 2.5 V ±0.2 V
PARAMETER
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VDD = min to max,
VDD = 2.3 V
IOH = –100 µA
IOH = –6 mA
IOL = 100 µA
IOL = 6 mA
VO = 1 V
VDD – 0.2
VOH
High-level output voltage
Low-level output voltage
V
1.8
–17
17
VDD = min to max,
VDD = 2.3 V
0.2
V
VOL
0.55
VDD = 2.3 V,
VDD = 2.5 V,
VDD = 2.7 V,
VDD = 2.3 V,
VDD = 2.5 V,
VDD = 2.7 V,
IOH
High-level output current
Low-level output current
VO = 1.25 V
VO = 2.375 V
VO = 1.2 V
VO = 1.25 V
VO = 0.3 V
–25
25
mA
–10
IOL
mA
10
(1) All typical values are at respective nominal VDD
.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
MIN NOM
MAX
UNIT
VDD = 3 V to 3.6 V
0
0
200
170
fclk
Clock frequency
MHz
VDD = 2.3 V to 2.7 V
JITTER CHARACTERISTICS
Characterized using CDCVF2310 Performance EVM when VDD=3.3 V. Outputs not under test are terminated to 50 Ω.
PARAMETER
TEST CONDITIONS
12 kHz to 5 MHz, fout = 30.72 MHz
12 kHz to 20 MHz, fout = 125 MHz
MIN
TYP
52
MAX
UNIT
tjitter
Additive phase jitter from input to output 1Y0
fs rms
45
6
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SCAS666C–JUNE 2001–REVISED JANUARY 2008
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
VDD = 3.3 V ±0.3 V (see Figure 2)
PARAMETER
TEST CONDITIONS
f = 0 MHz to 200 MHz
MIN
TYP
MAX UNIT
tPLH
tPHL
tsk(o)
tsk(p)
tsk(pp)
tr
CLK to Yn
1.3
2.8
ns
For circuit load, see Figure 2.
Output skew (Ym to Yn) (1) (see Figure 4)
Pulse skew (see Figure 5)
100
250
500
2
ps
ps
Part-to-part skew
ps
Rise time (see Figure 3)
VO = 0.4 V to 2 V
VO = 2 V to 0.4 V
0.7
0.7
0.1
0.1
0.4
0.4
V/ns
V/ns
ns
tf
Fall time (see Figure 3)
2
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time, G_high before CLK ↓
Disable setup time, G_low before CLK ↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
ns
ns
ns
(1) The tsk(o) specification is only valid for equal loading of all outputs.
VDD = 2.5 V ±0.2 V (see Figure 2)
PARAMETER
TEST CONDITIONS
f = 0 MHz to 170 MHz
MIN
TYP
MAX UNIT
tPLH
tPHL
tsk(o)
tsk(p)
tsk(pp)
tr
CLK to Yn
1.5
3.5
ns
For circuit load, see Figure 2.
Output skew (Ym to Yn) (1) (see Figure 4 )
Pulse skew (see Figure 5)
170
400
600
1.4
ps
ps
Part-to-part skew
ps
Rise time (see Figure 3)
VO = 0.4 V to 1.7 V
VO = 1.7 V to 0.4 V
0.5
0.5
0.1
0.1
0.4
0.4
V/ns
V/ns
ns
tf
Fall time (see Figure 3)
1.4
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time, G_high before CLK ↓
Disable setup time, G_low before CLK ↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
ns
ns
ns
(1) The tsk(o) specification is only valid for equal loading of all outputs.
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C
L
= 25 pF on Y
500 Ω
n
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, ZO = 50 Ω,
tr < 1.2 ns, tf < 1.2 ns.
Figure 2. Test Load Circuit
Copyright © 2001–2008, Texas Instruments Incorporated
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SCAS666C–JUNE 2001–REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION (continued)
V
DD
CLK
50% V
0 V
DD
t
t
PHL
PLH
V
OH
1.7 V or 2 V
Y
n
50% V
DD
0.4 V
0.4 V
V
OL
t
r
t
f
Figure 3. Voltage Waveforms Propagation Delay Times
V
DD
CLK
0 V
V
OH
50% V
Any Y
Any Y
DD
V
V
OL
OH
50% V
DD
V
OL
t
t
sk(o)
sk(o)
Figure 4. Output Skew
V
DD
50% V
CLK
DD
0 V
t
t
PHL
PLH
V
OH
V
OL
Y
n
50% V
DD
NOTE: t
= | t
− t
PHL
|
sk(p)
PLH
Figure 5. Pulse Skew
8
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SCAS666C–JUNE 2001–REVISED JANUARY 2008
PARAMETER MEASUREMENT INFORMATION (continued)
SUPPLY CURRENT
vs
FREQUENCY
220
200
180
160
140
120
100
80
V
= 2.3 V to 3.6 V
DD
V
T
A
= 3.6 V
= –40°C
DD
C (Y ) = 25 pF || 500 Ω
L
n
All Outputs Switching
= –40°C to 85°C
V
T
= 3.6 V
= 85°C
DD
T
A
A
V
DD
= 2.3 V
60
T
A
= 85°C
V
T
A
= 2.3 V
= –40°C
DD
40
20
0
0
20
40
60
80
100
120
140
160
180
200
f – Frequency – MHz
Figure 6.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
CDCVF2310PW
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
24
24
24
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
CKV2310
CDCVF2310PWG4
CDCVF2310PWR
CDCVF2310PWRG4
ACTIVE
ACTIVE
ACTIVE
PW
PW
PW
60
Green (RoHS
& no Sb/Br)
-40 to 85
CKV2310
CKV2310
CKV2310
2000
2000
Green (RoHS
& no Sb/Br)
-40 to 85
Green (RoHS
& no Sb/Br)
-40 to 85
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF CDCVF2310 :
Enhanced Product: CDCVF2310-EP
•
NOTE: Qualified Version Definitions:
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CDCVF2310PWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 24
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 38.0
CDCVF2310PWR
2000
Pack Materials-Page 2
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