CDCVF2310PWLE [TI]
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| 型号： | CDCVF2310PWLE |
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CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
2.5-V TO 3.3-V HIGH-PERFORMANCE CLOCK BUFFER
•
High-Performance 1:10 Clock Driver for
General-Purpose Applications. Operates up to
200 MHz at VDD 3.3 V
PW PACKAGE
(TOP VIEW)
•
•
•
•
•
Pin-to-Pin Skew < 100 ps at VDD 3.3 V
VDD Range: 2.3 V to 3.6 V
1
24
23
22
21
20
19
18
17
16
15
14
13
GND
CLK
2
V
DD
V
V
DD
3
1Y0
1Y1
1Y2
GND
GND
1Y3
Operating Temperature Range –40°C to 85°C
Output Enable Glitch Suppression
DD
4
2Y0
2Y1
GND
GND
2Y2
2Y3
5
Distributes One Clock Input to Two Banks of
Five Outputs
6
7
8
•
•
25-Ω On-Chip Series Damping Resistors
9
1Y4
Packaged in 24-Pin TSSOP
10
11
12
V
DD
V
V
DD
1G
2Y4
DD
2G
DESCRIPTION
The CDCVF2310 is a high-performance, low-skew clock buffer that operates up to 200 MHz. Two banks of five
outputs each provide low-skew copies of CLK. After power up, the default state of the outputs is low regardless
of the state of the control pins. For normal operation, the outputs of bank 1Y[0:4] or 2Y[0:4] can be placed in a
low state when the control pins (1G or 2G, respectively) are held low and a negative clock edge is detected on
the CLK input. The outputs of bank 1Y[0:4] or 2Y[0:4] can be switched into the buffer mode when the control pins
(1G and 2G) are held high and a negative clock edge is detected on the CLK input. The device operates in a
2.5-V and 3.3-V environment. The built-in output enable glitch suppression ensures a synchronized output enable
sequence to distribute full period clock signals.
The CDCVF2310 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2001–2004, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
FUNCTIONAL BLOCK DIAGRAM
3
4
1Y0
1Y1
1Y2
1Y3
1Y4
25 Ω
25 Ω
25 Ω
25 Ω
5
8
9
25 Ω
11
Logic Control
1G
13
Logic Control
2G
21
20
17
16
12
2Y0
2Y1
2Y2
2Y3
2Y4
24
25 Ω
CLK
25 Ω
25 Ω
25 Ω
25 Ω
2
CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
FUNCTION TABLE
INPUT
OUTPUT
1G
L
2G
L
CLK
1Y[0:4]
2Y[0:4]
L
↓
↓
↓
↓
L
H
L
L
CLK(1)
L
H
H
L
CLK(1)
CLK(1)
H
CLK(1)
(1) After detecting one negative edge on the CLK input, the output
follows the input CLK if the control pin is held high.
Terminal Functions
TERMINAL
NO.
I/O
DESCRIPTION
NAME
1G
11
I
Output enable control for 1Y[0:4] outputs. This output enable is active-high, meaning the
1Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
2G
13
I
Output enable control for 2Y[0:4] outputs. This output enable is active-high, meaning the
2Y[0:4] clock outputs follow the input clock (CLK) if this pin is logic high.
1Y[0:4]
2Y[0:4]
CLK
3, 4, 5, 8, 9
21, 20, 17, 16, 12
24
O
O
I
Buffered output clocks
Buffered output clocks
Input reference frequency
Ground
GND
1, 6, 7, 18, 19
2, 10, 14, 15, 22, 23
VDD
DC power supply, 2.3 V – 3.6 V
3
CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
DETAILED DESCRIPTION
Output Enable Glitch Suppression Circuit
The purpose of the glitch suppression circuitry is to ensure the output enable sequence is synchronized with the
clock input such that the output buffer is enabled or disabled on the next full period of the input clock (negative
edge triggered by the input clock) (see Figure 1).
The G input must fulfill the timing requirements (tsu, th) according to the Switching Characteristics table for
predictable operation.
CLK
G
n
n
Y
t
t
h(en)
su(en)
a) Enable Mode
CLK
G
n
n
Y
t
t
h(dis)
su(dis)
b) Disable Mode
Figure 1. Enable and Disable Mode Relative to CLK↓
4
CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
(1)
Supply voltage range, VDD
–0.5 V to 4.6 V
–0.5 V to VDD + 0.5 V
–0.5 V to VDD + 0.5 V
±50 mA
(2)(3)
Input voltage range, VI
(2)(3)
Output voltage range, VO
Input clamp current, IIK (VI < 0 or VI> VDD
)
Output clamp current, IOK (VO < 0 or VO > VDD
)
±50 mA
Continuous total output current, IO (VO = 0 to VDD
Package thermal impedance, θJA(4): PW package
Storage temperature range Tstg
)
±50 mA
120°C/W
–65°C to 150°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51.
(1)
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
2.3
2.5
3.3
Supply voltage, VDD
V
3.6
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
0.8
V
Low-level input voltage, VIL
0.7
2
1.7
0
High-level input voltage, VIH
Input voltage, VI
V
VDD
12
6
V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
VDD = 3 V to 3.6 V
VDD = 2.3 V to 2.7 V
High-level output current, IOH
mA
12
6
Low-level output current, IOL
mA
Operating free-air temperature, TA
–40
85
°C
(1) Unused inputs must be held high or low to prevent them from floating.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage
TEST CONDITIONS
MIN TYP(1)
MAX UNIT
VIK
II
VDD = 3 V,
II = –18 mA
–1.2
±5
V
Input current
VI = 0 V or VDD
µA
µA
pF
pF
(2)
IDD
CI
Static device current
Input capacitance
Output capacitance
CLK = 0 V or VDD
,
IO = 0 mA
80
VDD = 2.3 V to 3.6 V,
VDD = 2.3 V to 3.6 V,
VI = 0 V or VDD
VI = 0 V or VDD
2.5
2.8
CO
(1) All typical values are at respective nominal VDD
.
(2) For ICC over frequency, see Figure 6.
5
CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
VDD = 3.3 V ±0.3 V
PARAMETER
TEST CONDITIONS
IOH = –100 µA
MIN TYP(1)
VDD – 0.2
MAX UNIT
VDD = min to max,
VDD = 3 V
VOH
VOL
IOH
IOL
High-level output voltage
Low-level output voltage
High-level output current
Low-level output current
IOH = –12 mA
IOH = –6 mA
IOL = –100 µA
IOL = 12 mA
IOL = 6 mA
2.1
2.4
V
VDD = min to max,
VDD = 3 V
0.2
0.8
V
0.55
VDD = 3 V,
VO = 1 V
–28
28
VDD = 3.3 V,
VDD = 3.6 V,
VDD = 3 V,
VO = 1.65 V
VO = 3.135 V
VO = 1.95 V
VO = 1.65 V
VO = 0.4 V
–36
36
mA
mA
–14
14
VDD = 3.3 V,
VDD = 3.6 V,
(1) All typical values are at respective nominal VDD
.
VDD = 2.5 V ±0.2 V
PARAMETER
TEST CONDITIONS
MIN TYP(1)
VDD – 0.2
MAX UNIT
VDD = min to max,
VDD = 2.3 V
IOH = –100 µA
IOH = –6 mA
IOL = 100 µA
IOL = 6 mA
VO = 1 V
VOH
High-level output voltage
Low-level output voltage
V
1.8
–17
17
VDD = min to max,
VDD = 2.3 V
0.2
V
VOL
0.55
VDD = 2.3 V,
VDD = 2.5 V,
VDD = 2.7 V,
VDD = 2.3 V,
VDD = 2.5 V,
VDD = 2.7 V,
IOH
High-level output current
Low-level output current
VO = 1.25 V
VO = 2.375 V
VO = 1.2 V
VO = 1.25 V
VO = 0.3 V
–25
25
mA
–10
IOL
mA
10
(1) All typical values are at respective nominal VDD
.
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature
MIN NOM
MAX
UNIT
VDD = 3 V to 3.6 V
0
0
200
170
fclk
Clock frequency
MHz
VDD = 2.3 V to 2.7 V
6
CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
VDD = 3.3 V ±0.3 V (SEE FIGURE 2)
PARAMETER
TEST CONDITIONS
f = 0 MHz to 200 MHz
MIN
TYP
MAX UNIT
tPLH
tPHL
tsk(o)
tsk(p)
tsk(pp)
tr
CLK to Yn
1.3
2.8
ns
For circuit load, see Figure 2.
Output skew (Ym to Yn) (1) (see Figure 4)
Pulse skew (see Figure 5)
100
250
500
2
ps
ps
Part-to-part skew
ps
Rise time (see Figure 3)
VO = 0.4 V to 2 V
VO = 2 V to 0.4 V
0.7
0.7
0.1
0.1
0.4
0.4
V/ns
V/ns
ns
tf
Fall time (see Figure 3)
2
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time, G_high before CLK ↓
Disable setup time, G_low before CLK ↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
ns
ns
ns
(1) The tsk(o) specification is only valid for equal loading of all outputs.
VDD = 2.5 V ±0.2 V (SEE FIGURE 2)
PARAMETER
TEST CONDITIONS
f = 0 MHz to 170 MHz
MIN
TYP
MAX UNIT
tPLH
tPHL
tsk(o)
tsk(p)
tsk(pp)
tr
CLK to Yn
1.5
3.5
ns
For circuit load, see Figure 2.
Output skew (Ym to Yn) (1) (see Figure 4 )
Pulse skew (see Figure 5)
170
400
600
1.4
ps
ps
Part-to-part skew
ps
Rise time (see Figure 3)
VO = 0.4 V to 1.7 V
VO = 1.7 V to 0.4 V
0.5
0.5
0.1
0.1
0.4
0.4
V/ns
V/ns
ns
tf
Fall time (see Figure 3)
1.4
tsu(en)
tsu(dis)
th(en)
th(dis)
Enable setup time, G_high before CLK ↓
Disable setup time, G_low before CLK ↓
Enable hold time, G_high after CLK ↓
Disable hold time, G_low after CLK ↓
ns
ns
ns
(1) The tsk(o) specification is only valid for equal loading of all outputs.
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
C
L
= 25 pF on Y
500 Ω
n
A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 200 MHz, ZO = 50 Ω,
tr < 1.2 ns, tf < 1.2 ns.
Figure 2. Test Load Circuit
7
CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
V
DD
CLK
50% V
0 V
DD
t
t
PHL
PLH
V
OH
1.7 V or 2 V
Y
n
50% V
DD
0.4 V
0.4 V
V
OL
t
r
t
f
Figure 3. Voltage Waveforms Propagation Delay Times
V
DD
CLK
0 V
V
OH
50% V
Any Y
DD
V
V
OL
OH
50% V
DD
Any Y
V
OL
t
t
sk(o)
sk(o)
Figure 4. Output Skew
V
DD
50% V
DD
CLK
0 V
t
t
PHL
PLH
V
OH
V
OL
Y
n
50% V
DD
NOTE: t
= | t
− t
PHL
|
sk(p)
PLH
Figure 5. Pulse Skew
8
CDCVF2310
www.ti.com
SCAS666B–JUNE 2001–REVISED JANUARY 2004
PARAMETER MEASUREMENT INFORMATION (continued)
SUPPLY CURRENT
vs
FREQUENCY
220
V
= 2.3 V to 3.6 V
DD
V
T
A
= 3.6 V
= –40°C
DD
200
180
160
140
120
100
80
C (Y ) = 25 pF || 500 Ω
L
n
All Outputs Switching
= –40°C to 85°C
V
T
= 3.6 V
= 85°C
DD
T
A
A
V
DD
= 2.3 V
60
T
A
= 85°C
V
T
A
= 2.3 V
= –40°C
DD
40
20
0
0
20
40
60
80
100
120
140
160
180
200
f – Frequency – MHz
Figure 6.
9
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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