CDCVF2505 [TI]
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER; 3.3 V时钟锁相环时钟驱动器
| 型号： | CDCVF2505 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER |
| 文件： | 总10页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640D – JULY 2000 – REVISED JULY 2002
D OR PW PACKAGE
(TOP VIEW)
Phase-Lock Loop Clock Driver for
Synchronous DRAM and General-Purpose
Applications
CLKIN
1Y1
CLKOUT
1Y3
1
2
3
4
8
7
6
5
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
1Y0
V
3.3 V
DD
Low Jitter (Cycle-cycle): <|150 ps| Over the
Range 66 MHz–200 MHz
GND
1Y2
Distributes One Clock Input to One Bank of
Five Outputs (CLKOUT Is Used to Tune the
Input-Output Delay)
Three-States Outputs When There Is no
Input Clock
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC
Packages
Consumes Less Than 100 µA (Typically) in
Power Down Mode
Internal Feedback Loop Is Used to
Synchronize the Outputs to the Input Clock
25-Ω On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates
the Need for External Components
description
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock
signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that
make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50
percent, independentofdutycycleatCLKIN. Thedeviceautomaticallygoesinpower-downmodewhennoinput
signal is applied to CLKIN.
Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop
filter for the PLLs is included on-chip, minimizing component count, space, and cost.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This stabilization is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640D – JULY 2000 – REVISED JULY 2002
FUNCTION TABLE
INPUT
OUTPUTS
1Y (0:3) CLKOUT
CLKIN
L
H
L
H
Z
L
H
Z
†
<10 MHz
†
Typically, below 2 MHz the device goes in power-down mode in
which the PLL is turned off and the outputs enter into Hi-Z mode. If
a >10-MHz signal is applied at CLKIN the PLL turns on, reacquires
lock, andstabilizesafterapproximately100µs. Theoutputswillthen
be enabled.
functional block diagram
8
3
CLKOUT
1Y0
PLL
1
25 Ω
CLKIN
25 Ω
2
5
Power Down
1Y1
1Y2
25 Ω
25 Ω
25 Ω
7
1Y3
3-State
Edge Detect
Typical <10 MHz
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640D – JULY 2000 – REVISED JULY 2002
Terminal Functions
TERMINAL
NAME
1Y[0–3]
I/O
DESCRIPTION
NO.
2, 3, 5, 7
O
Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25-Ω
series damping resistor.
CLKIN
1
I
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver.
CLKIN is used to provide the reference signal to the integrated PLL that generates the clock output
signals. CLKIN must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once
the circuit is powered up and a valid signal is applied, a stabilization time (100 µs) is required for the
PLL to phase lock the feedback signal to CLKIN.
CLKOUT
GND
8
O
Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is
made inside the chip and an external feedback loop should NOT be connected. CLKOUT can be
loaded with a capacitor to achieve zero delay between CLKIN and the Y outputs.
4
6
Power Ground
V
Power 3.3-V Supply
DD3.3V
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.3 V
DD
Input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
DD
DD
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IK
I
I
DD
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O DD
Continuous total output current, I (V = 0 to V
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
O
DD
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165.5°C/W
JA
PWR package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230.5°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.3 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
DD
3
3.3
3.6
High-level input voltage, V
0.7 V
V
IH
DD
Low-level input voltage, V
0.3 V
V
IL
DD
Input voltage, V
0
V
DD
V
I
High-level output current, I
–12
12
mA
mA
°C
OH
Low-level output current, I
OL
Operating free-air temperature, T
–40
85
A
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640D – JULY 2000 – REVISED JULY 2002
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN NOM
MAX
200
UNIT
f
Clock frequency
24
MHz
clk
24 MHz – 85 MHz (see Note 4)
86 MHz – 200 MHz
30%
85%
60%
100
Input clock duty cycle
40%
50%
Stabilization time (see Note 5)
µs
NOTES: 4. Ensured by design but not 100% production tested.
5. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications
forpropagationdelay, skew, andjitterparametersgivenintheswitchingcharacteristicstablearenotapplicable. Thisparameterdoes
not apply for input modulation under SSC application.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Input voltage
TEST CONDITIONS
I = –18 mA
V
MIN TYP
MAX
UNIT
DD
V
IK
3 V
MIN to MAX
3 V
–1.2
V
I
I
I
I
I
I
I
= –100 µA
= –12 mA
= –6 mA
= 100 µA
= 12 mA
= 6 mA
V
DD
–0.2
2.1
OH
OH
OH
OL
OL
OL
V
OH
High-level output voltage
Low-level output voltage
V
V
3 V
2.4
MIN to MAX
3 V
0.2
0.8
V
OL
3 V
0.55
V
V
V
V
= 1 V
3 V
–27
O
O
O
O
I
High-level output current
Low-level output current
mA
mA
OH
= 1.65 V
= 2 V
3.3 V
3 V
–36
40
27
I
I
OL
= 1.65 V
3.3 V
Input current
V = 0 V or V
I
5
µA
I
DD
DD
C
Input capacitance
V = 0 V or V
I
3.3 V
3.3 V
4.2
2.8
5.2
pF
i
Yn
C
Output capacitance
V = 0 V or V
I
pF
o
DD
CLKOUT
†
All typical values are at respective nominal V
and 25°C.
DD
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 25 pF, V = 3.3 V 0.3 V (see Note 5)
L
DD
†
PARAMETER
TEST CONDITIONS
CLKIN to Yn, f= 66 MHz to 200 MHz
Yn to Yn
MIN
MAX
150
150
150
400
55%
2
UNIT
ps
TYP
t
t
Propagation delay (normalized (see Figure 3)
Output skew (see Note 6)
–150
pd
ps
sk(o)
f = 66 MHz to 200 MHz
f = 24 MHz to 50 MHz
70
t
Jitter (cycle to cycle) (see Figure 5)
ps
c(jit_cc)
200
odc
Output duty cycle (see Figure 4)
f = 24 MHz to 200 MHz at 50% V
DD
45%
0.5
t
t
Rise time
Fall time
V
= 0.4 V to 2 V
= 2 V to 0.4 V
ns
ns
r
O
O
V
0.5
2
f
†
All typical values are at respective nominal V
and 25°C.
DD
specification is only valid for equal loading of all outputs.
NOTE 6: The t
sk(o)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640D – JULY 2000 – REVISED JULY 2002
ESD information
ESD MODELS
LIMIT
2.0 kV
300 V
1 kV
Human Body Model (HBM)
Machine Model (MM)
Charge Device Model (CDM)
thermal information
THERMAL AIR FLOW (CFM)
UNIT
CDCVF2505 8-PIN SOIC
0
150
250
500
R
R
R
R
High K
Low K
High K
Low K
97
87
83
77
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJC
θJC
165
126
113
97
39
42
THERMAL AIR FLOW (CFM)
CDCVF2505 8-PIN TSSOP
UNIT
0
150
142
185
250
138
170
500
132
150
R
R
R
R
High K
Low K
High K
Low K
149
230
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJC
θJC
65
69
TYPICAL CHARACTERISTICS
t
, PROPAGATION DELAY TIME
vs
t
PROPAGATION DELAY TIME
vs
pd
pd,
DELTA LOAD (TYPICAL VALUES @ 3.3 V, 25°C)
FREQUENCY (TYPICAL VALUES @ 3.3 V, 25°C)
500
1400
Load: CLKOUT = 12 pF || 500 Ω,
= 25 pF || 500 Ω
Y
n
= 25 pF || 500 Ω
Y
n
1050
700
400
300
350
0
200
–350
–700
100
0
–1050
–1400
–30
–20
–10
0
10
20
30
25
50
75
100
125
150
175
200
Delta Load – pF
f – Frequency – MHz
Figure 2
Figure 1
NOTE: Delta Load = CLKOUT Load – Yn Load
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640D – JULY 2000 – REVISED JULY 2002
TYPICAL CHARACTERISTICS
t
, TYPICAL PROPAGATION DELAY TIME
DUTY CYCLE
vs
pd
vs
FREQUENCY(TUNED FOR MINIMUM DELAY)
FREQUENCY
55
150
100
50
Load: CLKOUT = 12 pF || 500 Ω,
Yn = 25 pF || 500 Ω
Load: CLKOUT = 21 pF || 500 Ω,
Yn = 25 pF || 500 Ω
52.5
0
50
–50
–100
–150
47.5
45
0
50
100
150
200
25
50
75
100
125
150
175
200
f – Frequency – MHz
f – Frequency – MHz
Figure 3
Figure 4
CYCLE–CYCLE JITTER
I
, SUPPLY CURRENT
vs
FREQUENCY
CC
vs
FREQUENCY
500
400
300
200
100
120
Typical Values @ 3.3 V,
Worst Case @ V
CC
= 3.6 V, T = 85°C,
A
T
= 25°C
Load: Y and CLKOUT = 25 pF || 500 Ω
A
100
80
60
40
20
0
0
25
50
75
100
125
150
175
200
0
20 40 60 80 100 120 140 160 180 200
f – Frequency – MHz
f – Frequency – MHz
Figure 5
Figure 6
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDCVF2505
3.3-V CLOCK PHASE-LOCK LOOP CLOCK DRIVER
SCAS640D – JULY 2000 – REVISED JULY 2002
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500 Ω
Yn = 25 pF || 500 Ω
CLKOUT = 12 pF || 500 Ω
Figure 7. Test Load Circuit
3 V
0 V
CLKIN
50% V
DD
t
pd
V
V
OH
2 V
0.4 V
2 V
1Y0 – 1Y3
50% V
DD
0.4 V
OL
t
t
f
r
Figure 8. Voltage Threshold for Measurements, Propagation Delay (t
)
pd
Any Y
50 % V
DD
t
sk(o)
Any Y
50 % V
DD
Figure 9. Output Skew
t
t
c2
c1
t
= t – t
c(jit_CC) c1 c2
Figure 10. Cycle-to-Cycle Jitter
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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