CDCVF2505IDRQ1 [TI]
3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER; 3.3 V时钟锁相环时钟驱动器
| 型号： | CDCVF2505IDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER |
| 文件： | 总10页 (文件大小：225K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDCVF2505-Q1
www.ti.com ........................................................................................................................................................................................... SCAS867–DECEMBER 2008
3.3-V CLOCK PHASE-LOCKED LOOP CLOCK DRIVER
1
FEATURES
•
Qualified for Automotive Applications
•
•
Consumes Less Than 100 µA (Typically) in
Power Down Mode
•
Phase-Locked Loop Clock Driver for
Synchronous DRAM and General-Purpose
Applications
Internal Feedback Loop Is Used to
Synchronize the Outputs to the Input Clock
•
•
•
Spread-Spectrum Clock Compatible
•
•
25-Ω On-Chip Series Damping Resistors
Operating Frequency: 24 MHz to 200 MHz
Integrated RC PLL Loop Filter Eliminates the
Need for External Components
Low Jitter (Cycle-to-Cycle): <150 ps Over the
Range 66 MHz to 200 MHz
D PACKAGE
(TOP VIEW)
•
•
Distributes One Clock Input to One Bank of
Five Outputs (CLKOUT Is Used to Tune the
Input-Output Delay)
1
2
3
4
8
7
6
5
CLKIN
1Y1
CLKOUT
1Y3
Three-States Outputs When There Is No Input
Clock
VDD 3.3 V
1Y0
GND
1Y2
•
•
Operates From Single 3.3-V Supply
Available in 8-Pin SOIC Package
DESCRIPTION
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to
precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal
(CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it
ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50
percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input
signal is applied to CLKIN.
Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter
for the PLLs is included on-chip, minimizing component count, space, and cost.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of
the feedback signal to the reference signal. This stabilization is required following power up and application of a
fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is characterized for operation from –40°C to 85°C.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
ORDERABLE PART NUMBER
TOP-SIDE MARKING
CKV05Q
–40°C to 85°C
SOIC – D
Reel of 2500
CDCVF2505IDRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
CDCVF2505-Q1
SCAS867–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
FUNCTION TABLE
INPUT
OUTPUTS
CLKIN
1Y[0–3]
CLKOUT
L
H
L
H
Z
L
H
Z
<10 MHz(1)
(1) Below 2 MHz (typical) the device goes into power-down mode,
during which the PLL is turned off and the outputs enter into Hi-Z
mode. If a >10-MHz signal is applied at CLKIN, the PLL turns on,
reacquires lock, and stabilizes after approximately 100 µs. The
outputs are then enabled.
FUNCTIONAL BLOCK DIAGRAM
8
3
CLKOUT
PLL
1
25 W
CLKIN
1Y0
25 W
2
5
Power Down
1Y1
1Y2
25 W
25 W
7
1Y3
25 W
3-State
Edge Detect
Typical <10 MHz
TERMINAL FUNCTIONS
NAME
1Y0
NO.
3
I/O
DESCRIPTION
1Y1
2
Clock outputs. These outputs are low-skew copies of CLKIN. Each output has an integrated 25-Ω series
damping resistor.
O
1Y2
5
1Y3
7
Clock input. CLKIN provides the clock signal to be distributed by the CDCVF2505 clock driver. CLKIN is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLKIN must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and
a valid signal is applied, a stabilization time (100 µs) is required for the PLL to phase lock the feedback signal
to CLKIN.
CLKIN
1
I
Feedback output. CLKOUT completes the internal feedback loop of the PLL. This connection is made inside
the chip and an external feedback loop should NOT be connected. CLKOUT can be loaded with a capacitor
to achieve zero delay between CLKIN and the Y outputs.
CLKOUT
8
O
GND
4
6
Power Ground
Power 3.3-V supply
VDD3.3V
2
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CDCVF2505-Q1
www.ti.com ........................................................................................................................................................................................... SCAS867–DECEMBER 2008
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VDD
VI
Supply voltage range
–0.5 V to 4.3 V
–0.5 V to VDD + 0.5 V
–0.5 V to VDD + 0.5 V
±50 mA
Input voltage range(2)(3)
Output voltage range(2)(3)
Input clamp current
VO
IIK
VI < 0 or VI > VDD
VO < 0 or VO > VDD
VO = 0 to VDD
IOK
IO
Output clamp current
±50 mA
Continuous total output current
Package thermal impedance(4)
Storage temperature range
±50 mA
θJA
Tstg
97.1°C/W
–65°C to 150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) This value is limited to 4.3 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
ELECTROSTATIC DISCHARGE INFORMATION
ESD MODEL
LIMIT
2000 V
300 V
HBM
MM
Human-Body Model
Machine Model
CDM Charged-Device Model
1000 V
RECOMMENDED OPERATING CONDITIONS
MIN NOM
MAX UNIT
VDD
VIH
VIL
VI
Supply voltage
3
3.3
3.6
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.7 × VDD
0.3 × VDD
VDD
V
0
V
IOH
IOL
TA
High-level output current
Low-level output current
Operating free-air temperature
–12
mA
mA
°C
12
–40
85
TIMING REQUIREMENTS
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
MIN NOM
24
MAX UNIT
fclk
Clock frequency
200 MHz
24 MHz to 85 MHz(1)
86 MHz to 200 MHz
30
40
85
%
Input clock duty cycle
Stabilization time(2)
50
60
100
µs
(1) Specified by design.
(2) Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for
propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
Copyright © 2008, Texas Instruments Incorporated
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SCAS867–DECEMBER 2008........................................................................................................................................................................................... www.ti.com
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Input voltage
TEST CONDITIONS
II = –18 mA
VDD
3 V
MIN TYP(1)
MAX UNIT
VIK
–1.2
V
IOH = –100 µA
IOH = –12 mA
IOH = –6 mA
IOL = 100 µA
IOL = 12 mA
IOL = 6 mA
MIN to MAX
3 V
VDD – 0.2
VOH
High-level output voltage
Low-level output voltage
2.1
2.4
V
3 V
MIN to MAX
3 V
0.2
0.8
VOL
V
3 V
0.55
VO = 1 V
3 V
–27
27
IOH
High-level output current
Low-level output current
mA
mA
VO = 1.65 V
VO = 2 V
3.3 V
3 V
–36
40
IOL
VO = 1.65 V
VI = 0 V or VDD
VI = 0 V or VDD
3.3 V
II
Input current
±5
µA
Ci
Input capacitance
3.3 V
3.3 V
4.2
2.8
5.2
pF
Yn
Co
Output capacitance
VI = 0 V or VDD
pF
CLKOUT
(1) All typical values are at nominal VDD and TA = 25°C.
SWITCHING CHARACTERISTICS(1)
over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF, VDD = 3.3 V ± 0.3 V (unless
otherwise noted)
PARAMETER
Propagation delay, normalized (see Figure 1)
Output skew(3)
TEST CONDITIONS
CLKIN to Yn, f = 66 MHz to 200 MHz
Yn to Yn
MIN TYP(2)
MAX UNIT
tpd
–150
150
150
150
400
55
ps
ps
tsk(o)
f = 66 MHz to 200 MHz
f = 24 MHz to 50 MHz
f = 24 MHz to 200 MHz at 50% VDD
VO = 0.4 V to 2 V
70
tc(jit_cc) Jitter (cycle to cycle) (see Figure 5)
ps
200
odc
tr
Output duty cycle (see Figure 4)
45
0.5
0.5
%
ns
ns
Rise time
Fall time
2
tf
VO = 2 V to 0.4 V
2
(1) Not production tested
(2) All typical values are at nominal VDD and TA = 25°C.
(3) The tsk(o) specification is only valid for equal loading of all outputs.
4
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TYPICAL CHARACTERISTICS
t
PROPAGATION DELAY TIME
vs
tPD, PROPAGATION DELAY TIME
pd,
vs
DELTA LOAD (TYPICAL VALUES at 3.3 V, 25°C)
CLOCK FREQUENCY, f = 100 MHz
FREQUENCY (TYPICAL VALUES at 3.3 V, 25°C)
500
Load: CLKOUT = 12 pF || 500 W,
= 25 pF || 500 W
1400
1050
700
Y
n
Y
n
= 25 pF
Y = 3 pF
n
400
300
CLKOUT =Y
=
n
25 pF || 500 W
3 pF || 500 W
350
CLKOUT
3 pF to 25 pF
0
200
-13
-4
-350
CLKOUT
-700
100
0
3 pF to 25 pF
-1050
-1400
25
50
75
100
125
f – Frequency – MHz
150
175
200
-30
-20
-10
0
10
20
30
Delta Load – pF
NOTE: Delta Load = CLKOUT Load – Yn Load
Figure 1.
Figure 2.
DUTY CYCLE
vs
tpd,TYPICAL PROPAGATION DELAY TIME
vs
FREQUENCY (TUNED FOR MINIMUM DELAY)
FREQUENCY
150
100
50
55
Load: CLKOUT = 21 pF || 500 W,
Yn = 25 pF || 500 W
Load: CLKOUT = 12 pF || 500 W,
Yn = 25 pF || 500 W
52.5
0
50
-50
-100
-150
47.5
45
0
50
100
150
200
25
50
75
100
125
f – Frequency – MHz
150
175
200
f – Frequency – MHz
Figure 3.
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
CYCLE-to-CYCLE JITTER
vs
FREQUENCY
ICC, SUPPLY CURRENT
vs
FREQUENCY
500
400
300
200
100
120
Worst Case at VCC = 3.6 V,T = 85°C,
Typical Values at 3.3 V,
= 25°C
A
Load:Y and CLKOUT = 25 pF || 500 W
T
A
100
80
60
40
20
0
0
0
20 40 60 80 100 120 140 160 180 200
f – Frequency – MHz
25
50
75
100
125
150
175
200
f – Frequency – MHz
Figure 5.
Figure 6.
6
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www.ti.com ........................................................................................................................................................................................... SCAS867–DECEMBER 2008
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500 W
Yn = 25 pF || 500 W
CLKOUT = 12 pF || 500 W
Figure 7. Test Load Circuit
3 V
0 V
50% V
DD
CLKIN
t
pd
V
V
OH
2 V
0.4 V
2 V
1Y0–1Y3
50% V
DD
0.4 V
OL
t
t
f
r
Figure 8. Voltage Threshold for Measurements, Propagation Delay (tpd)
AnyY
50 % V
DD
t
sk(o)
AnyY
50 % V
DD
Figure 9. Output Skew
t
c1
t
c2
t
= t – t
c1 c2
c(jit_CC)
Figure 10. Cycle-to-Cycle Jitter
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Jan-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
CDCVF2505IDRQ1
ACTIVE
SOIC
D
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
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OTHER QUALIFIED VERSIONS OF CDCVF2505-Q1 :
Catalog: CDCVF2505
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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