CDC516DGG [TI]
3.3-V PHASE-LOCK LOOP CLOCK DRIVER; 3.3 -V锁相环时钟驱动器
| 型号： | CDC516DGG |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER |
| 文件： | 总11页 (文件大小：161K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
DGG PACKAGE
(TOP VIEW)
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
Distributes One Clock Input to Four Banks
of Four Outputs
V
1Y0
1Y1
GND
GND
1Y2
1Y3
V
V
CC
1
2
3
4
5
6
7
8
9
48
47
46
45
44
43
42
41
40
CC
4Y0
4Y1
GND
GND
4Y2
4Y3
Separate Output Enable for Each Output
Bank
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
No External RC Network Required
V
Operates at 3.3-V V
CC
Packaged in Plastic 48-Pin Thin Shrink
Small-Outline Package
CC
CC
1G
4G
GND 10
AV
39 GND
AV
11
12
38
37
CC
CC
CLK
FBIN
description
AGND 13
AGND 14
GND 15
2G 16
36 AGND
35 FBOUT
34 GND
33 3G
The CDC516 is a high-performance, low-skew,
low-jitter, phase-lock loop clock driver. It uses a
phase-lock loop (PLL) to precisely align, in both
frequency and phase, the feedback output
(FBOUT) to the clock (CLK) input signal. It is
specifically designed for use with synchronous
V
17
32
V
CC
CC
2Y0 18
2Y1 19
GND 20
GND 21
2Y2 22
2Y3 23
31 3Y0
30 3Y1
29 GND
28 GND
27 3Y2
26 3Y3
DRAMs. The CDC516 operates at 3.3-V V
and
CC
is designed to drive up to five clock loads per
output.
Four banks of four outputs provide 16 low-skew,
low-jitter copies of the input clock. Output signal
duty cycles are adjusted to 50 percent,
independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled
separately via the 1G, 2G, 3G, and 4G control
inputs. When the G inputs are high, the outputs
switchinphaseandfrequencywithCLK;whenthe
G inputs are low, the outputs are disabled to the
logic-low state.
V
24
25
V
CC
CC
Unlike many products containing PLLs, the CDC516 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC516 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL may be bypassed for test purposes by strapping AV
to ground.
CC
The CDC516 is characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
FUNCTION TABLE
INPUTS
3G
OUTPUTS
1Y
(0:3)
2Y
(0:3)
3Y
4Y
1G
2G
4G
CLK
FBOUT
(0:3)
(0:3)
X
L
X
L
X
L
X
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
L
L
L
H
L
L
L
H
H
L
L
L
H
H
L
L
L
H
L
L
L
H
L
L
H
H
H
H
L
L
H
H
H
H
L
L
L
H
L
L
L
H
L
L
H
H
L
L
H
H
L
L
H
L
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
L
L
L
H
L
L
H
H
L
L
H
H
L
L
H
L
L
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
L
H
H
H
H
H
H
AVAILABLE OPTIONS
PACKAGE
SMALL OUTLINE
T
A
(PW)
0°C to 70°C
CDC516DGGR
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
functional block diagram
9
1G
2
1Y0
3
1Y1
6
1Y2
7
1Y3
16
2G
18
2Y0
19
2Y1
22
2Y2
23
2Y3
33
3G
31
3Y0
30
3Y1
27
3Y2
26
3Y3
40
4G
47
4Y0
46
12
4Y1
CLK
PLL
43
37
4Y2
FBIN
42
4Y3
11
AV
CC
35
FBOUT
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
Terminal Functions
TERMINAL
TYPE
DESCRIPTION
NAME
NO.
Clock input. CLK provides the clock signal to be distributed by the CDC516 clock driver. CLK is used
toprovidethereferencesignaltotheintegratedPLLthatgeneratestheclockoutputsignals. CLKmust
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
CLK
12
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
FBIN
1G
37
9
I
I
I
I
I
Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same
frequency as CLK.
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
2G
16
33
40
Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are
disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same
frequency as CLK.
3G
Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are
disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same
frequency as CLK.
4G
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL.
FBOUT
1Y(0:3)
2Y(0:3)
3Y(0:3)
4Y(0:3)
35
O
O
O
O
O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G.
These outputs can be disabled to a logic-low state by deasserting the 1G control input.
2, 3, 6, 7
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G.
These outputs can be disabled to a logic-low state by deasserting the 2G control input.
18, 19, 22, 26
31, 30, 27, 26
47, 46, 43, 42
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G.
These outputs can be disabled to a logic-low state by deasserting the 3G control input.
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G.
These outputs can be disabled to a logic-low state by deasserting the 4G control input.
Analog power supply. AV
CC
provides the power reference for the analog circuitry. In addition, AV
CC
AV
CC
11, 38
Power
can be used to bypass the PLL for test purposes. When AV
is strapped to ground, the PLL is
CC
bypassed and CLK is buffered directly to the device outputs.
AGND
13, 14, 36
Ground Analog ground. AGND provides the ground reference for the analog circuitry.
Power Power supply
1, 8, 17, 24,
25, 32, 41, 48
V
CC
4, 5, 10, 15,
GND
20, 21, 28, 29, Ground Ground
34, 39, 44, 45
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
I
Voltage range applied to any output in the high
or low state, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
OK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through each V
Maximum power dissipation at T = 55°C (in still air) (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.85 W
Storage temperature range, T
O
O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
CC
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
recommended operating conditions (see Note 4)
MIN
3
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
2
V
IH
0.8
V
IL
0
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Operating free-air temperature
–20
20
mA
mA
°C
OH
OL
T
A
70
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
V
CC
MIN TYP
MAX
UNIT
V
IK
I = –18 mA
I
3 V
–1.2
V
I
I
I
I
= –100 µA
= –20 mA
= 100 µA
= 20 mA
MIN to MAX
3 V
V
CC
–0.2
2.4
OH
OH
OL
OL
V
V
V
OH
MIN to MAX
3 V
0.2
0.55
±5
V
OL
I
I
V = V
or GND
or GND
3.6 V
µA
µA
µA
pF
pF
I
I
CC
CC
§
V = V
I = 0, Outputs: low or high
O
3.6 V
20
CC
I
∆I
CC
One input at V
CC
– 0.6 V,
Other inputs at V
or GND
3.3 V to 3.6 V
3.3 V
500
CC
C
C
V = V
or GND
4
6
i
I
CC
= V or GND
CC
V
3.3 V
o
O
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
For I
of AV , see Figure 5. For dynamic digital I , see Figure 6.
CC
CC CC
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
25
MAX
125
60%
1
UNIT
f
Clock frequency
MHz
clock
Input clock duty cycle
40%
†
Stabilization time
ms
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency, fixed-phasereferencesignalmustbepresentatCLK. Untilphaselockisobtained, thespecificationsforpropagationdelay, skew,
and jitter parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
‡
temperature, C = 30 pF (see Note 5 and Figures 1 and 2)
L
V
= 3.3 V
± 0.165 V
V
= 3.3 V
CC
CC
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
t
phase error
reference
66 MHz < CLKIN↑ < 100 MHz
CLKIN↑ = 100 MHz
FBIN↑
FBIN↑
–80...400
240
ps
ps
(see Figure 3)
t
, – jitter,
(see Note 6)
phase error
170
360
§
t
Any Y or FBOUT
F(clkin > 66 MHz)
F(clkin ≤ 66 MHz)
F(clkin > 66 MHz)
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
Any Y or FBOUT
200
100
55%
57%
1.6
ps
ps
sk(o)
Jitter
–100
45%
43%
0.7
(pk-pk)
Duty cycle
t
r
1.1
0.8
1.5
1.3
ns
ns
t
f
0.5
1.5
‡
§
These parameters are not production tested.
The t specification is only valid for equal loading of all outputs.
sk(o)
NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is 70 ps to 460 ps for the 5% V
range.
CC
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
50% V
50% V
CC
CC
t
pd
From Output
Under Test
V
V
OH
2 V
0.4 V
2 V
Output
500
50% V
CC
0.4 V
30 pF
OL
t
t
f
r
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 1.2 ns, t ≤ 1.2 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
PARAMETER MEASUREMENT INFORMATION
CLKIN
FBIN
t
phase error
FBOUT
Any Y
t
sk(o)
Any Y
Any Y
t
sk(o)
Figure 2. Phase Error and Skew Calculations
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
TYPICAL CHARACTERISTICS
PHASE ERROR
vs
CLOCK FREQUENCY
OUTPUT DUTY CYCLE
vs
CLOCK FREQUENCY
50
40
57%
55%
V
T
= 3.3 V
V
C
= 3.3 V
DD
= 25°C
DD
= 30 pF
A
L
30
20
10
0
53%
51%
49%
47%
45%
43%
–10
–20
–30
–40
–50
35
55
75
95
115
135
30
50
70
90
110
130
f
– Clock Frequency – MHz
clk
f
– Clock Frequency – MHz
clk
Figure 3
Figure 4
ANALOG SUPPLY CURRENT
vs
DYNAMIC SUPPLY CURRENT
vs
CLOCK FREQUENCY
CLOCK FREQUENCY
9
500
V
DD
A
= 3.3 V
= 25°C
V
= 3.6 V
CC
8
7
450
400
350
T
Bias = 0/3 V
C
T
A
= 30 pF to GND
= 25°C
L
6
5
4
3
2
300
250
200
150
100
1
0
50
0
25 35 45 55 65 75 85 95 105 115 125
0
20
40
60
80
100
120
140
f
– Clock Frequency – MHz
clk
f
– Clock Frequency – MHz
clk
Figure 5
Figure 6
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS575A – JULY 1996 – REVISED JANUARY 1998
MECHANICAL INFORMATION
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
PINS **
48
56
64
DIM
0,27
0,17
M
0,08
0,50
48
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
25
A MIN
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
24
A
0,25
0°–8°
0,75
0,50
Seating Plane
0,10
1,20 MAX
0,05 MIN
4040078/D 08/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-153
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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