CDC536DL [TI]
3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS; 具有三态输出的3.3V锁相环时钟驱动器
| 型号： | CDC536DL |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH 3-STATE OUTPUTS |
| 文件： | 总12页 (文件大小：171K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
DB OR DL PACKAGE
(TOP VIEW)
Low-Output Skew for Clock-Distribution
and Clock-Generation Applications
Operates at 3.3-V V
CC
AV
AV
CC
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
CC
Distributes One Clock Input to Six Outputs
AGND
CLKIN
SEL
OE
GND
1Y1
AGND
FBIN
TEST
CLR
One Select Input Configures Three Outputs
to Operate at One-Half or Double the Input
Frequency
No External RC Network Required
V
CC
2Y1
GND
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
V
GND
CC
V
CC
Application for Synchronous DRAM,
High-Speed Microprocessor
1Y2 10
V
19 2Y2
GND
11
12
18
17
CC
Negative-Edge-Triggered Clear for
Half-Frequency Outputs
GND
V
CC
16 2Y3
1Y3 13
14
TTL-Compatible Inputs and Outputs
15 GND
V
CC
Outputs Drive 50-Ω Parallel-Terminated
Transmission Lines
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
Distributed V
Switching Noise
and Ground Pins Reduce
CC
Packaged in Plastic 28-Pin Shrink Small
Outline Package
description
TheCDC536isahigh-performance, low-skew, low-jitterclockdriver. Itusesaphase-lockloop(PLL)toprecisely
align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is specifically
designed for use with synchronous DRAMs and popular microprocessors operating at speeds from 50 MHz to
100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC536 operates at 3.3-V
V
and is designed to drive a 50- transmission line.
CC
The feedback input (FBIN) is used to synchronize the output clocks in frequency and phase to the input clock
(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between
CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL)
input configures three Y outputs to operate at one-half or double the CLKIN frequency depending on which pin
is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the
duty cycle at the input clock.
Output-enable(OE)isprovidedforoutputcontrol. WhenOEishigh, theoutputsareinthehigh-impedancestate.
When OE is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass
the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC536 does not require external RC networks. The loop filter for
the PLL is included on-chip, minimizing component count, board space, and cost.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
description (continued)
Because it is based on PLL circuitry, the CDC536 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN as well as following any changes to the PLL reference or
feedback signals. Such changes occur upon change of the select inputs, enabling the PLL via TEST, and upon
enable of all outputs via OE.
The CDC536 is characterized for operation from 0°C to 70°C.
detailed description of output configurations
The voltage-controlled oscillator (VCO) in the CDC536 has a frequency range of 100 MHz to 200 MHz, twice
the operating frequency range of the CDC536 outputs. The output of the VCO is divided by two and by four to
provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. The SEL0
and SEL1 inputs determine which of the two signals are buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency of this output matches that of the CLKIN signals. In the case that a VCO/2 output is wired to FBIN,
the VCO must operate at twice the CLKIN frequency, resulting in device outputs that operate at the same or
one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at the same or
twice the CLKIN frequency.
output configuration A
Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to
the FBIN input. The input frequency range for the CLKIN input is 50 MHz to 100 MHz when using output
configuration A. Outputs configured as 1/2× outputs operate at half the CLKIN frequency, while outputs
configured as 1× outputs operate at the same frequency as the CLKIN input.
Table 1. Output Configuration A
INPUTS
SEL
OUTPUTS
1/2×
1×
FREQUENCY FREQUENCY
L
None
1Yn
All
H
2Yn
NOTE: n = 1, 2, 3
output configuration B
Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to
FBIN. The input frequency range for the CLKIN input is 25 MHz to 50 MHz when using output configuration B.
Outputs configured as 1× outputs operate at the CLKIN frequency, while outputs configured as 2× outputs
operate at double the frequency of the CLKIN input.
Table 2. Output Configuration B
INPUTS
SEL
OUTPUTS
1×
2×
FREQUENCY FREQUENCY
L
All
None
2Yn
H
1Yn
NOTE: n = 1, 2, 3
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
functional block diagram
5
OE
24
CLR
26
FBIN
2
Phase-Lock Loop
2
3
CLKIN
25
TEST
4
SEL
7
1Y1
10
1Y2
13
1Y3
22
2Y1
19
2Y2
16
2Y3
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
Clockinput. CLKINprovidestheclocksignaltobedistributedbytheCDC536clock-drivercircuit. CLKINisused
to provide the reference signal to the integrated phase-lock loop that generates the clock output signals. CLKIN
must have a fixed frequency and fixed phase in order for the phase-lock loop to obtain phase lock. Once the
circuit is powered up and a valid CLKIN signal is applied, a stabilization time is required for the phase-lock loop
to phase lock the feedback signal to its reference signal.
CLKIN
3
I
CLR
24
26
I
I
CLR is used for testing purposes only.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of the
six clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks to obtain zero
phase delay between the FBIN and differential CLKIN inputs.
FBIN
Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE is
high, all outputs are in the high-impedance state. Since the feedback signal for the phase-lock loop is taken
directly from an output, placing the outputs in the high-impedance state interrupts the feedback loop; therefore,
when a high-to-low transition occurs at OE, enabling the output buffers, a stabilization time is required before
the phase-lock loop obtains phase lock.
OE
5
I
Output configuration select. SEL selects the output configuration for each output bank (e.g. 1×, 1/2×, or 2×).
(see Tables 1 and 2).
SEL
4
I
I
TEST is used to bypass the phase-lock loop circuitry for factory testing of the device. When TEST is low, all
outputsoperateusingthePLLcircuitry. WhenTESTishigh, theoutputsareplacedinatestmodethatbypasses
the PLL circuitry. TEST should be grounded for normal operation.
TEST
25
These outputs are configured by SEL to transmit one-half or one-fourth the frequency of the VCO. The
relationship between the CLKIN frequency and the output frequency is dependent on SEL. The duty cycle of
the Y output signals is nominally 50%, independent of the duty cycle of the CLKIN signal.
1Y1–1Y3 7, 10, 13
2Y1–2Y3 22, 19, 16
O
O
These outputs transmit one-half the frequency of the VCO. The relationship between the CLKIN frequency and
the output frequency is dependent on the frequency of the output being fed back to FBIN. The duty cycle of the
Y output signals is nominally 50% independent of the duty cycle of the CLKIN signal.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V (see Note 1) . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 mA
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
OK
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . 0.68 W
A
DL package . . . . . . . . . . . . . . . . . . . . 0.7 W
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 75 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteintheABTAdvancedBiCMOSTechnologyData
Book, literature number SCBD002.
recommended operating conditions (see Note 3)
MIN
3
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
CC
High-level input voltage
Low-level input voltage
Input voltage
2
V
IH
0.8
5.5
–32
32
V
IL
0
0
V
I
I
I
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
OH
OL
T
A
70
NOTE 3: Unused inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
A
PARAMETER
TEST CONDITIONS
UNIT
V
MIN
MAX
V
V
V
V
V
V
V
V
V
V
V
= 3 V,
I = –18 mA
–1.2
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
‡
= MIN to MAX ,
I
I
I
I
= –100 µA
= – 32 mA
= 100 µA
= 32 mA
V
–0.2
OH
OH
OL
OL
CC
V
OH
= 3 V,
2
= 3 V,
0.2
0.5
±10
±1
10
–10
2
V
OL
V
= 3 V,
‡
= 0 or MAX ,
V = 3.6 V
I
I
I
µA
= 3.6 V,
= 3.6 V,
= 3.6 V,
V = V
or GND
CC
I
I
I
V
= 3 V
= 0
µA
µA
OZH
O
O
V
OZL
Outputs high
Outputs low
V
CC
= 3.6 V,
I
= 0,
O
I
2
mA
CC
V = V
or GND
I
CC
Outputs disabled
2
C
C
V = V
or GND
6
pF
pF
i
I
CC
V
O
= V or GND
CC
9
o
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN
25
MAX
50
UNIT
When VCO is operating at four times the CLKIN frequency
When VCO is operating at double the CLKIN frequency
f
Clock frequency
MHz
clock
50
100
60%
50
Input clock duty cycle
40%
After SEL
After OE↓
50
†
Stabilization time
µs
After power up
After CLKIN
50
50
†
TimerequiredfortheintegratedPLLcircuittoobtainphaselockofitsfeedbacksignaltoitsreferencesignal. Inorderforphaselocktobeobtained,
a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 30 pF (see Note 4 and Figures 1 and 2)
L
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
MIN
MAX
UNIT
f
100
MHz
max
Duty cycle
Y
Y
Y
45%
55%
‡
t
CLKIN↑
CLKIN↑
–500 +500
ps
ps
ns
ns
ns
ns
phase error
Jitter
200
0.5
1
(pk-pk)
‡
t
t
t
t
sk(o)
sk(pr)
1.4
1.4
r
f
‡
Thepropagationdelay,t
are only valid for equal loading of all outputs.
,isdependentonthefeedbackpathfromanyoutputtoFBIN.Thet
phaseerror
,t
,andt specifications
sk(pk)
phaseerror sk(o)
NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
Input
1.5 V
1.5 V
t
phase error
From Output
Under Test
V
V
OH
2 V
0.8 V
2 V
Output
500
1.5 V
0.8 V
C
= 30 pF
L
OL
(see note A)
t
r
t
f
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT FOR OUTPUTS
NOTES: A.
C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
CLKIN
t
t
phase error 1
Outputs
Operating
at 1/2 CLKIN
Frequency
phase error 2
t
t
phase error 3
t
phase error 7
phase error 4
Outputs
Operating
at CLKIN
t
t
t
phase error 5
phase error 8
Frequency
t
phase error 9
phase error 6
NOTES: A. Output skew, t , is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
(n = 1, 2, . . . 6)
(n = 7, 8, 9)
phase error n
phase error n
B. Process skew, t , is calculated as the greater of:
sk(pr)
– The difference between the maximum and minimum t
operating conditions.
(n = 1, 2, . . . 6) across multiple devices under identical
phase error n
– The difference between the maximum and minimum t
operating conditions.
(n = 7, 8, 9) across multiple devices under identical
phase error n
Figure 2. Skew Waveforms and Calculations
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
CLKIN
t
phase error 10
Outputs
Operating
at CLKIN
Frequency
t
phase error 11
t
t
phase error 12
phase error 13
Outputs
Operating
at 2× CLKIN
Frequency
t
phase error 14
t
phase error 15
NOTES: A. Output skew, t
, is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
(n = 10, 11, . . . 15)
phase error n
B. Process skew, t , is calculated as the greater of:
sk(pr)
– The difference between the maximum and minimum t
operating conditions.
(n = 10, 11, . . . 15) across multiple devices under identical
phase error n
Figure 3. Waveforms for Calculation of t
and t
sk(pr)
sk(o)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
MECHANICAL INFORMATION
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
DIM
3,30
2,70
6,50
5,90
6,50
5,90
7,50
6,90
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
9,90
12,30
4040065 /C 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS378F – APRIL 1994 – REVISED OCTOBER 1998
MECHANICAL INFORMATION
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PIN SHOWN
0.025 (0,635)
0.012 (0,305)
0.008 (0,203)
0.005 (0,13)
25
M
48
0.006 (0,15) NOM
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–8°
1
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/C 03/97
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
相关型号：
CDC5801ADBQG4
Low Jitter Clock Multiplier & Divider w/Programmable Delay & Phase Alignment 24-SSOP -40 to 85
TI
©2020 ICPDF网 联系我们和版权申明