CDC5801A [TI]
LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE AND PHASE ALIGNMENT; 低抖动时钟乘法器和除法器与可编程的，相位校准
| 型号： | CDC5801A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW JITTER CLOCK MULTIPLIER AND DIVIDER WITH PROGRAMMABLE AND PHASE ALIGNMENT |
| 文件： | 总18页 (文件大小：333K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
D
Low Jitter Clock Multiplier by x4, x6, x8.
Input Frequency Range (19 MHz to
125 MHz). Supports Output Frequency
From 150 MHz to 500 MHz
D
D
D
Applications: Video Graphics, Gaming
Products, Datacom, Telecom
Accepts LVCMOS, LVTTL Inputs for
REFCLK Terminal
D
D
Fail-Safe Power Up Initialization
Accepts Other Single-Ended Signal Levels
at REFCLK Terminal by Programming
Low Jitter Clock Divider by /2, /3, /4. Input
Frequency Range (50 MHz to 125 MHz).
Supports Ranges of Output Frequency
From 12.5 MHz to 62.5 MHz
Proper V REF Voltage Level (For
DD
Example, HSTL 1.5 if V REF = 1.6 V)
DD
D
Supports Industrial Temperature Range of
°
°
−40 C to 85 C
D
D
D
D
D
D
D
D
2.6 mUI Programmable Bidirectional Delay
Steps
DBQ PACKAGE
(TOP VIEW)
Typical 8-ps Phase Jitter (12 kHz to 20 MHz)
at 500 MHz
Typical 2.1-ps RMS Period Jitter (Entire
Frequency Band) at 500 MHz
V
REF
P0
P1
V
1
24
23
22
21
20
19
18
17
16
15
14
DD
REFCLK
2
V
P
O
3
One Single-Ended Input and One
Differential Output Pair
DD
DD
GNDP
GND
GNDO
CLKOUT
NC
4
5
Output Can Drive LVPECL, LVDS, and
LVTTL
LEADLAG
DLYCTRL
GNDPA
6
CLKOUTB
GNDO
7
Three Power Operating Modes to Minimize
Power
8
V
V
PA
V
O
9
DD
DD
Low Power Consumption (Typical 200 mW
at 500 MHz)
PD
MULT0/DIV0
MULT1/DIV1
10
11
DD
STOPB
Packaged in a Shrink Small-Outline
Package (DBQ)
PWRDNB 12
13 P2
NC − No internal connection
D
No External Components Required for PLL
D
Spread Spectrum Clock Tracking Ability to
Reduce EMI
description
The CDC5801A device provides clock multiplication and division from a single-ended reference clock
(REFCLK) to a differential output pair (CLKOUT/CLKOUTB). The multiply and divide terminals (MULT/DIV0:1)
provide selection for frequency multiplication and division ratios, generating CLKOUT/CLOUTKB frequencies
ranging from 12.5 MHz to 500 MHz with a clock input reference (REFCLK) ranging from 19 MHz to 125 MHz.
See Table 1 and Table 2 for detail frequency support.
The implemented phase aligner provides the possibility to phase align (zero delay) between
CLKOUT/CLKOUTB and REFCLK or any other CLK in the system by feeding the clocks that need to be aligned
to the DLYCTRL and the LEADLAG terminals.
The phase aligner also allows the user to delay or advance the CLKOUT/CLKOUTB with steps of 2.6 mUI (unit
interval). For every rising edge on the DLYCTRL terminal, the output clocks are delayed by 2.6-mUI step size
as long as there is low on the LEADLAG terminal. Similarly, for every rising edge on the DLYCTRL terminal, the
output clocks are advanced by 2.6-mUI step size as long as there is high on the LEADLAG terminal. The
CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all
power up conditions. As the phase between REFCLK and CLKOUT/CLKOUTB is random after power up, the
application may implement a self calibration routine at power up to produce a certain phase start position, before
programming a fixed delay with the clock on the DLYCTRL terminal.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2005, Texas Instruments Incorporated
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1
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SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
Depending on the selection of the mode terminals (P0:2), the device behaves as a multiplier (by 4, 6, or 8) with
the phase aligner bypassed or as a multiplier or divider with programmable delay and phase aligner functionality.
Through the select terminals (P0:2) user can also bypass the phase aligner and the PLL (test mode) and output
the REFCLK directly on the CLKOUT/CLKOUTB terminals. Through P0:2 terminals the outputs could be in a
high impedance state. This device has another unique capability to be able to function with a wide band of
voltages on the REFCLK terminal by varying the voltage on the V REF terminal.
DD
The CDC5801A has a fail-safe power up initialization state-machine which supports proper operation under all
power up conditions.
The CDC5801A device is characterized for operation over free-air temperatures of −40°C to 85°C.
functional block diagram
PWRDWNB
P0
P1
P2
STOPB
Control Logic
PLLCLK
Phase Aligner
Bypass MUX
PLL
REFCLK
CLKOUT
B
Phase
Aligner
CLKOUTB
Divider
Ratio
VDDREF/2
φ
D
A
VDDPD/2
2
MULT0/DIV0
MULT1/DIV1
DLYCTRL LEADLAG
2
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SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
†
FUNCTION TABLE
MODE
P0
P1
P2
CLKOUT/CLKOUTB
Multiplication with programmable
delay and phase alignment active
0
0
0
REFCLK multiplied by ratio per Table 1 selected by MULT/DIV terminals. Outputs
are delayed or advanced based on DLYCTRL and LEADLAG terminal
configuration.
‡
Division with programmable delay
and phase alignment active
0
1
0
0
1
0
REFCLK divided by ratio per Table 2 selected by MULT/DIV terminals. Outputs
are delayed or advanced based on DLYCTRL and LEADLAG terminal
configuration.
‡
Multiplication only mode (phase
In this mode one can only multiply as per Table 1. Programmable delay capability
and divider capability is deactivated. PLL is running.
§
aligner bypassed)
Test mode
1
0
1
1
0
PLL and phase aligner both bypassed. REFCLK is directly channeled to output.
Hi-Z
Hi-Z mode
X
†
‡
§
X = don’t care, Hi-Z = high impedance
Please see Table 4 and Table 5 for explanation for the programmability and phase alignment functions.
In this mode the DLYCTRL and LEADLAG terminals must be strapped high or low. Lowest possible jitter is achieved in this mode, but a delay
of 200 ps to 2 ns expected typically from REFCLK to CLKOUT depending on the output frequency.
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
20
18
7
CLKOUT
CLKOUTB
DLYCTRL
O
O
I
Output clock
Output clock (complement)
Every rising edge on this terminal delays/advances the CLKOUT/CLKOUTB signal by 1/384th of the
CLKOUT/CLKOUTB period. (e.g., for a 90 degree delay or advancement one needs to provide 96 rising
edges). See Table 4.
GND
5
17, 21
4
GND for V REF and V PD
DD DD
GNDO
GNDP
GNDPA
LEADLAG
MULT0/DIV0
MULT1/DIV1
NC
GND for clock output terminals (CLKOUT, CLKOUTB)
GND for PLL
8
GND for phase aligner
6
I
I
I
Decides if the output clock is delayed or advanced with respect to REFCLK. See Table 4.
PLL multiplier and divider select
15
14
19
12
24
23
13
2
PLL multiplier and divider select
Not used
PWRDNB
P0
I
I
I
I
I
I
I
I
I
I
I
Active low power down state, CLKOUT/CLKOUTB goes low
Mode control, see the Function Table
P1
Mode control, see the Function Table
P2
Mode control, see the Function Table
REFCLK
STOPB
Reference input clock
11
9
Active low output disabler, PLL and PA still running, CLKOUT and CLKOUTB goes to a dc value as per Table 3
Supply voltage for phase aligner
V
DD
V
DD
V
DD
V
DD
V
DD
PA
PD
REF
O
10
1
Reference voltage for the DLYCTRL, LEADLAG terminals and STOPB function
Reference voltage for REFCLK
16, 22
3
Supply voltage for the output terminals (CLKOUT, CLKOUTB)
Supply voltage for PLL
P
3
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SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
PLL divider/multiplier selection
Table 1 and Table 2 list the supported REFCLK and BUSCLK (CLKOUT/CLKOUTB) frequencies.
Table 1. Multiplication Ratios (P0:2 = 000 or 100)
REFCLK
(MHZ)
MULTIPLICATION
RATIO
BUSCLK
(MHZ)
MULT0
MULT1
0
0
1
0
1
1
38−125
25−83.3
19−62.5
4
6
8
152−500
150−500
152−500
Table 2. Divider Ratio (P0:2 = 001)
(1)
REFCLK
(MHZ)
DIVISION
RATIO
BUSCLK
(MHZ)
MULT0
MULT1
0
1
1
0
0
1
100−125
75−93
2
3
4
50−62.5
25−31
50−62
12.5−15.5
†
BUSCLK will be undefined until a valid reference clock is available at REFCLK. After applying
REFCLK, the PLL requires stabilization time to achieve phase lock.
Table 3. Clock Output Driver States
STATE
Powerdown
CLK stop
Normal
PWRDNB
STOPB
CLKOUT
CLKOUTB
0
1
1
X
0
1
GND
GND
V
V
O, STOP
O, STOP
As per Function Table
As per Function Table
Table 4. Programmable Delay and Phase Alignment
DLYCTRL
LEADLAG
CLKOUT AND CLKOUTB
†
†
Each rising edge
1
0
Will be advanced by one step size (see Table 5)
Will be delayed by one step size (see Table 5)
Each rising edge
†
nd
For every 32 edge, there are one or two edges the phase aligner does not update. Therefore,
nd
CLKOUT phase is not updated on every 32 edge.
Table 5. Clock Output Driver States
FUNCTIONALITY
Multiply by 4, 6, 8
Divide by 2
STEP SIZE
CLKOUT period/384 (for example, 6.5 ps at 400 MHz)
CLKOUT period/3072 (for example, 6.5 ps at 50 MHz)
CLKOUT period/6144 (for example, 6.5 ps at 25 MHz)
CLKOUT period/12288 (for example, 6.5 ps at 12.5 MHz)
Divide by 3
Divide by 4
NOTE: The frequency of the DLYCTRL terminal must always be equal or less than the
frequency of the LEADLAG terminal.
4
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SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V
DD
Output voltage range, V , at any output terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
O
DD
DD
Input voltage range,V , at any input terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
I
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see Dissipation Rating Table
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40°C to 85°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
‡
T = 85°C
A
POWER RATING
A
PACKAGE
POWER RATING
ABOVE T = 25°C
A
DBQ
1400 mW
11 mW/°C
740 mW
‡
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V (V P, V PA, V O)
DD DD DD DD
3
3.3
3.6
High-level input voltage, V (CMOS)
IH
0.7 × V
V
DD
Low-level input voltage, V (CMOS)
IL
0.3 × V
DD
V
REFCLK low-level input voltage, V
IL
0.3 × V REF
DD
V
REFCLK high-level input voltage, V
IH
0.7 × V REF
DD
V
Input signal low voltage, V (STOPB, DLYCTRL, LEADLAG)
IL
0.3 × V PD
DD
V
Input signal high voltage, V (STOPB, DLYCTRL, LEADLAG)
IH
0.7 × V PD
V
DD
Input reference voltage for (REFCLK) (V REF)
DD
1.235
1.235
V
V
V
DD
Input reference voltage for (DLYCTRL and LEADLAG) (V PD)
DD
V
DD
High-level output current, I
−16
16
mA
mA
°C
OH
Low-level output current, I
OL
Operating free-air temperature, T
−40
85
A
timing requirements
MIN
MAX
33
UNIT
Input frequency of modulation, f
(if driven by SSC CLKIN)
kHz
mod
Modulation index (nonlinear maximum 0.5%)
Input slew rate, SR
0.6%
4
1
40%
19
V/ns
Input duty cycle on REFCLK
60%
125
200
400
75%
Input frequency on REFCLK
MHz
MHz
MHz
Allowable frequency on DLYCTRL
Allowable frequency on LEADLAG
Allowable duty cycle on DLYCTRL and LEADLAG
25%
5
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SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
‡
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
Output voltage during CLK stop
mode
V
See Figure 1
1.1
2
V
O(STOP)
V
V
Output crossing-point voltage
See Figure 1 and Figure 4
See Figure 1
0.5V O−0.2
DD
0.5V O+0.2
DD
V
V
V
OX
Output voltage swing (V
− V
)
1.7
2.9
O
OH
OL
V
Input clamp voltage
V
= 3 V,
I = −18 mA
I
−1.2
IK
DD
See Figure 1, V
= 3 to 3.6 V
2.0
2.2
2.6
0.3
DD
V
OH
High-level output voltage
Low-level output voltage
V
V
V
= 3 V,
I
= −16 mA
DD
See Figure 1, V
OH
= 3 to 3.6 V
0.6
0.5
DD
V
OL
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3 V,
I
= 16 mA
= 1 V
OL
= 3.135 V,
= 3.3 V,
V
V
V
V
V
V
−32
43
−52
−51
O
O
O
O
O
O
= 1.65 V
= 3.135 V
= 1.95 V
= 1.65 V
= 0.4 V
I
High-level output current
Low-level output current
mA
mA
OH
= 3.465 V,
= 3.135 V,
= 3.3 V,
−14.5
61.5
65
−21
I
OL
= 3.465 V,
25.5
36
10
High-impedance-state output
current
I
I
I
P0 = 0, P1 = 1
µA
µA
µA
OZ
High-impedance-state output
current during CLK stop
Stop = 0, V = GND or V
O
100
100
10
OZ(STOP)
OZ(PD)
DD
High-impedance-state output
current in power-down state
PWRDNB = 0,
−10
V
O
= GND or V
DD
REFCLK,
STOPB
V
= 3.6 V,
= 3.6 V,
= 3.6 V,
= 3.6 V,
V = V
I
DD
DD
High-level input
current
I
µA
PWRDNB,
P0:2, MULT/
DIV0:1
IH
IL
V
DD
V
DD
V
DD
V = V
I
10
−10
−10
DD
REFCLK,
STOPB
V = 0
I
Low-level input
current
I
µA
PWRDNB,
P0:2, MULT/
DIV0:1
V = 0
I
High state
Low state
R at I −14.5 mA to −16.5 mA
15
11
35
17
50
35
Output impedance
(single ended)
I
O
Z
O
Ω
R at I 14.5 mA to 16.5 mA
I
O
PWRDNB = 0
PWRDNB = 1
50
µA
mA
pF
V
DD
V
DD
REF,
PD
Reference current
V
= 3.6 V
DD
0.5
C
C
Input capacitance
Output capacitance
V = V
I DD
or GND
or GND
2
3
I
V
= V
pF
O
O DD
REFCLK = 0 MHz to 100 MHz,
PWDNB = 0, STOPB = 1
I
Supply current in power-down state
Supply current in CLK stop state
Supply current in normal state
150
40
µA
mA
mA
DD(PD)
I
BUSCLK configured for 500 MHz
DD(CLKSTOP)
BUSCLK = 500 MHz
P0:2 = 000; load see Figure 1
I
70
DD(NORMAL)
†
‡
V
refers to any of the following; V PA, V PD, V REF, V O, and V P
DD DD DD DD DD
DD
All typical values are at V
= 3.3 V, T = 25°C.
DD
A
6
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ꢒꢎꢈ ꢖ ꢎꢆꢐ ꢐ ꢆꢗꢇ ꢍ ꢁꢍꢇ ꢆꢘ ꢆꢓꢁ ꢒꢕꢆ ꢙꢍ ꢆꢇꢋ ꢖ ꢓ ꢐ ꢍꢓ ꢌ
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
jitter specification over recommended operating free-air temperature range and V
otherwise noted)
(unless
CC
†
PARAMETER
CLKOUT
TEST CONDITIONS
MIN TYP
MAX
UNIT
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Cycle-to-cycle (+)
6
40
50
27
27
155 MHz
ps
ps
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Phase jitter (accumulated, 50 kHz to 80 MHz)
Cycle-to-cycle (+)
5.5
36
36
36
23
23
200 MHz
312 MHz
400 MHz
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Phase jitter (accumulated, 50 kHz to 80 MHz)
Cycle-to-cycle (+)
3
20
18
18
17
17
t
(jitter)
(Multiplication only mode. Phase alignment
and programmable delay features are not
selected (PA bypass). See Figure 2.)
ps
ps
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Phase jitter (accumulated, 50 kHz to 80 MHz)
Cycle-to-cycle (+)
2.3
17
12
12
15
15
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Phase jitter (accumulated, 50 kHz to 80 MHz)
Cycle-to-cycle (+)
2.1
16
8
8
14
14
500 MHz
155 MHz
200 MHz
ps
ps
ps
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Cycle-to-cycle (+)
9
70
50
50
50
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Phase jitter (accumulated, 50 kHz to 80 MHz)
Cycle-to-cycle (+)
7
55
36
36
40
40
t
(jitter)
Cycle-to-cycle (−)
(Multiplication with phase alignment and
programmable delay features selected. See
Figure 2.)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Phase jitter (accumulated, 50 kHz to 80 MHz)
Cycle-to-cycle (+)
4
35
18
18
30
30
312 MHz
400 MHz
ps
ps
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Phase jitter (accumulated, 50 kHz to 80 MHz)
Cycle-to-cycle (+)
3.1
27
13
13
25
25
Cycle-to-cycle (−)
†
All typical values are at V
DD
= 3.3 V, T = 25°C.
A
7
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ꢇ ꢈꢉ ꢊ ꢋ ꢌꢌ ꢍꢎ ꢀ ꢇ ꢈꢀ ꢏ ꢐꢑ ꢇꢌꢋ ꢒ ꢇ ꢋꢍ ꢎ ꢆꢓ ꢁ ꢁꢋ ꢔꢋꢁ ꢍꢎ ꢉ ꢋꢌ ꢕ
ꢒ ꢎꢈꢖꢎ ꢆ ꢐꢐ ꢆ ꢗꢇ ꢍ ꢁꢍ ꢇꢆꢘ ꢆꢓ ꢁ ꢒ ꢕꢆꢙ ꢍ ꢆꢇ ꢋꢖ ꢓꢐ ꢍꢓ ꢌ
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
jitter specification over recommended operating free-air temperature range and V
otherwise noted) (continued)
(unless
CC
†
PARAMETER
CLKOUT
TEST CONDITIONS
MIN TYP
MAX
UNIT
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Phase jitter (accumulated, 50 kHz to 80 MHz)
Cycle-to-cycle (+)
2.9
24
9
9
20
20
t
(jitter)
(Multiplication with phase alignment and
programmable delay features selected.
See Figure 2.)
500 MHz
ps
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Cycle-to-cycle (+)
12
75
55
55
12.5 MHz
15.5 MHz
25 MHz
ps
ps
ps
ps
MULT0:1 = 11
(Divider
ratio = 4)
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Cycle-to-cycle (+)
8
50
38
38
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Cycle-to-cycle (+)
7.5
50
35
35
MULT0:1 = 10
(Divider
t
(jitter)
Cycle-to-cycle (−)
(Divider mode with
Period RMS (1Σ jitter, full frequency band)
Period p-p
Cycle-to-cycle (+)
5.5
30
23
23
ratio = 3)
phase aligner not active:
DLYCTRL =LEADLAG =
0 or 1. See Figure 2.)
31 MHz
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Cycle-to-cycle (+)
8
40
12
30
30
50 MHz
ps
ps
MULT0:1 = 00
(Divider
ratio = 2)
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Cycle-to-cycle (+)
5.5
28
9
24
24
62.5 MHz
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Cycle-to-cycle (+)
12.5
80
55
12.5 MHz
15.5 MHz
25 MHz
ps
ps
ps
ps
MULT0:1 = 11
(Divider
ratio = 4)
Cycle-to-cycle (−)
55
Period RMS (1Σ jitter, full frequency band)
Period p-p
Cycle-to-cycle (+)
8.5
55
38
38
t
(jitter)
(Divider mode with
phase alignment and
programmable delay
features selected. See
Figure 2.)
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Cycle-to-cycle (+)
10
60
35
35
MULT0:1 = 10
(Divider
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Cycle-to-cycle (+)
7
40
23
23
ratio = 3)
31 MHz
Cycle-to-cycle (−)
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉ ꢊ ꢋꢌ ꢌ ꢍꢎ ꢀꢇ ꢈ ꢀꢏ ꢐ ꢑꢇꢌ ꢋꢒ ꢇꢋ ꢍꢎ ꢆꢓꢁ ꢁꢋ ꢔꢋꢁ ꢍꢎ ꢉꢋ ꢌꢕ
ꢒꢎꢈ ꢖ ꢎꢆꢐ ꢐ ꢆꢗꢇ ꢍ ꢁꢍꢇ ꢆꢘ ꢆꢓꢁ ꢒꢕꢆ ꢙꢍ ꢆꢇꢋ ꢖ ꢓ ꢐ ꢍꢓ ꢌ
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
jitter specification over recommended operating free-air temperature range and V
otherwise noted) (continued)
(unless
CC
†
PARAMETER
CLKOUT
TEST CONDITIONS
MIN TYP
MAX
UNIT
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Cycle-to-cycle (+)
9
50
13
35
35
50 MHz
ps
ps
t
(jitter)
(Divider mode with
phase alignment and
programmable delay
features selected. See
Figure 2.)
MULT0:1 = 00
(Divider
ratio = 2)
Cycle-to-cycle (−)
Period RMS (1Σ jitter, full frequency band)
Period p-p
Phase jitter (accumulated, 12 kHz to 20 MHz)
Cycle-to-cycle (+)
6.5
30
10
26
26
62.5 MHz
Cycle-to-cycle (−)
†
All typical values are at V
DD
= 3.3 V, T = 25°C.
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
Output duty cycle
TEST CONDITIONS
See Figure 3
MIN TYP
MAX
UNIT
t
45%
55%
(DC)
Output rise and fall times (measured at 20%−80% of
output voltage)
t , t
r f
See Figure 5 and Figure 1
150
350
ps
†
All typical values are at V
DD
= 3.3 V, T = 25°C.
A
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢆ
ꢇ ꢈꢉ ꢊ ꢋ ꢌꢌ ꢍꢎ ꢀ ꢇ ꢈꢀ ꢏ ꢐꢑ ꢇꢌꢋ ꢒ ꢇ ꢋꢍ ꢎ ꢆꢓ ꢁ ꢁꢋ ꢔꢋꢁ ꢍꢎ ꢉ ꢋꢌ ꢕ
ꢒ ꢎꢈꢖꢎ ꢆ ꢐꢐ ꢆ ꢗꢇ ꢍ ꢁꢍ ꢇꢆꢘ ꢆꢓ ꢁ ꢒ ꢕꢆꢙ ꢍ ꢆꢇ ꢋꢖ ꢓꢐ ꢍꢓ ꢌ
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
state transition latency specifications
TEST
CONDITIONS
†
TYP
PARAMETER
FROM
TO
MIN
MAX
UNIT
Delay time, PWRDNB↑ to CLKOUT/
CLKOUTB output settled (excluding
3
t
)
(DISTLOCK)
t
t
Powerdown Normal See Figure 6
ms
(powerup)
Delay time, PWRDNB↑ to internal PLL and
clock are on and settled
3
3
3
Delay time, power up to CLKOUT/CLKOUTB
output settled
V
DD
Normal See Figure 6
ms
DD
(V powerup)
Delay time, power up to internal PLL and
clock are on and settled
MULT0 and MULT1 change to CLKOUT/
CLKOUTB output resettled (excluding
t
t
t
Normal
CLK Stop
CLK Stop
Normal See Figure 7
Normal See Figure 8
Normal See Figure 8
1
ms
ns
(MULT)
t
)
(DISTLOCK)
STOPB↑ to CLKOUT/CLKOUTB glitch-free
clock edges
10
(CLKON)
(CLKSETL)
STOPB↑ to CLKOUT/CLKOUTB output
settled to within 50 ps of the phase before
STOPB was disabled
20 cycles
STOPB↓ to CLKOUT/CLKOUTB output dis-
abled
CLK
t
t
t
t
Normal
Normal
STOPB
Normal
See Figure 8
Stop
5
1
ns
ms
µs
(CLKOFF)
(powerdown)
(STOP)
Delay time, PWRDNB↓ to the device in the
power-down mode
Power−
See Figure 6
down
Maximum time in CLKSTOP (STOPB = 0)
before reentering normal mode (STOPB = 1)
Normal See Figure 8
100
Minimum time in normal mode (STOPB = 1)
before reentering CLKSTOP (STOPB = 0)
CLK
See Figure 8
stop
100
ms
(ON)
†
All typical values are at V
DD
= 3.3 V, T = 25°C.
A
PARAMETER MEASUREMENT INFORMATION
CLKOUT
50 Ω
VCM
50 Ω
10 pF
CLKOUTB
Figure 1. Test Load and Voltage Definitions (V
, V , V , V
)
O(STOP) OX OH OL
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉ ꢊ ꢋꢌ ꢌ ꢍꢎ ꢀꢇ ꢈ ꢀꢏ ꢐ ꢑꢇꢌ ꢋꢒ ꢇꢋ ꢍꢎ ꢆꢓꢁ ꢁꢋ ꢔꢋꢁ ꢍꢎ ꢉꢋ ꢌꢕ
ꢒꢎꢈ ꢖ ꢎꢆꢐ ꢐ ꢆꢗꢇ ꢍ ꢁꢍꢇ ꢆꢘ ꢆꢓꢁ ꢒꢕꢆ ꢙꢍ ꢆꢇꢋ ꢖ ꢓ ꢐ ꢍꢓ ꢌ
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
CLKOUTB
CLKOUT
t
t
cycle,i
− t
cycle,i+1
Cycle-to-Cycle Jitter = | t
cycle,i cycle,i+r
| Over 1000 Consecutive Cycles
Figure 2. Cycle-to-Cycle Jitter
CLKOUT
CLKOUTB
t
pw+
t
cycle
Duty Cycle = (t )
/t
pw+ cycle
Figure 3. Output Duty Cycle
CLKOUT
V
V
V
X+
X, nom
X−
CLKOUTB
Figure 4. Crossing-Point Voltage
V
V
OH
80%
20%
OL
t
t
f
r
Figure 5. Voltage Waveforms
PWRDNB
t
t
(power down)
(power up)
CLKOUT/
CLKOUTB
Figure 6. PWRDNB Transition Timings
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢆ
ꢇ ꢈꢉ ꢊ ꢋ ꢌꢌ ꢍꢎ ꢀ ꢇ ꢈꢀ ꢏ ꢐꢑ ꢇꢌꢋ ꢒ ꢇ ꢋꢍ ꢎ ꢆꢓ ꢁ ꢁꢋ ꢔꢋꢁ ꢍꢎ ꢉ ꢋꢌ ꢕ
ꢒ ꢎꢈꢖꢎ ꢆ ꢐꢐ ꢆ ꢗꢇ ꢍ ꢁꢍ ꢇꢆꢘ ꢆꢓ ꢁ ꢒ ꢕꢆꢙ ꢍ ꢆꢇ ꢋꢖ ꢓꢐ ꢍꢓ ꢌ
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
PARAMETER MEASUREMENT INFORMATION
MULT0 and/or MULT1
t
(MULT)
CLKOUT/
CLKOUTB
Figure 7. MULT Transition Timings
t
(ON)
t
(STOP)
STOPB
t
t
(CLKOFF)
(CLKSETL)
(see Note A)
t
(CLKON)
(see Note A)
CLKOUT/
CLKOUTB
Output Clock
Not Specified
Glitches OK
Clock Output Settled
Within 50 ps of the
Phase Before Disabled
Clock Enabled
and Glitch Free
NOTE A: V = V
ref
200 mV
O
Figure 8. STOPB Transition Timings
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀ ꢂꢃ ꢄꢅ ꢆ
ꢇ ꢈꢉ ꢊ ꢋꢌ ꢌ ꢍꢎ ꢀꢇ ꢈ ꢀꢏ ꢐ ꢑꢇꢌ ꢋꢒ ꢇꢋ ꢍꢎ ꢆꢓꢁ ꢁꢋ ꢔꢋꢁ ꢍꢎ ꢉꢋ ꢌꢕ
ꢒ
ꢎ
ꢈ
ꢖ
ꢎ
ꢆ
ꢐ
ꢐ
ꢆ
ꢗ
ꢇ
ꢍ
ꢁ
ꢍ
ꢇ
ꢆ
ꢘ
ꢆ
ꢓ
ꢁ
ꢒ
ꢕ
ꢆ
ꢙ
ꢍ
ꢆ
ꢇ
ꢋ
ꢖ
ꢓ
ꢐ
ꢍ
ꢓ
ꢌ
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
Z = 50 Ω ; Length = L1
19.44 MHz
CDCVF2310
Clock Buffer
Z = 50 Ω
CLK
CDC5801
A
Outputs are Phase Aligned
Between the Two Buffers
3.3 V
3.3 V
V
REF
P0
P1
DD
REFCLK
V
DD
P
V
O
3.3 V
DD
CDCVF2310
Clock Buffer
GNDP
GNDO
CLKOUT
NC
GND
Z = 50 Ω
CLK
LEADLAG
20 R
DLYCTRL CLKOUTB
GNDPA GNDO
V
V
PA
PD
V
O
DD
DD
3.3 V
3.3 V
MULT0/DIV0
MULT1/DIV1
P2
DD
3.3 V
STOPB
PWRDNB
Z = 50 Ω ; Length = L1
Figure 9. Using the CDC5801A Device as a Multiplier by 8 and Aligning Two Different Clocks
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢀꢂ ꢃ ꢄ ꢅ ꢆ
ꢇ ꢈꢉ ꢊ ꢋ ꢌꢌ ꢍꢎ ꢀ ꢇ ꢈꢀ ꢏ ꢐꢑ ꢇꢌꢋ ꢒ ꢇ ꢋꢍ ꢎ ꢆꢓ ꢁ ꢁꢋ ꢔꢋꢁ ꢍꢎ ꢉ ꢋꢌ ꢕ
ꢒ ꢎꢈꢖꢎ ꢆ ꢐꢐ ꢆ ꢗꢇ ꢍ ꢁꢍ ꢇꢆꢘ ꢆꢓ ꢁ ꢒ ꢕꢆꢙ ꢍ ꢆꢇ ꢋꢖ ꢓꢐ ꢍꢓ ꢌ
SCAS813A − AUGUST 2005 − REVISED DECEMBER 2005
MECHANICAL DATA
DBQ (R−PDSO−G**)
PLASTIC SMALL−OUTLINE PACKAGE
0.012 (0,30)
0.008 (0,20)
0.025 (0,64)
24
0.005 (0,13)
13
0.157 (3,99) 0.244 (6,20)
0.150 (3,81) 0.228 (5,80)
0.008 (0,20) NOM
Gauge Plane
1
12
A
0.010 (0,25)
0°−8°
0.035 (0,89)
0.016 (0,40)
0.069 (1,75) MAX
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
PINS **
16
20
24
28
DIM
0.197
(5,00)
0.344
(8,74)
0.344
(8,74)
0.394
(10,01)
A MAX
A MIN
0.189
(4,80)
0.337
(8,56)
0.337
(8,56)
0.386
(9,80)
M0−137
VARIATION
D
AB
AD
AE
AF
4073301/F 02/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO−137.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-May-2007
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
(mm)
CDC5801ADBQR
DBQ
24
MLA
330
16
6.5
9.0
2.5
8
16
Q1
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
MLA
Length (mm) Width (mm) Height (mm)
CDC5801ADBQR
DBQ
24
0.0
0.0
0.0
Pack Materials-Page 2
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Products
Amplifiers
Data Converters
DSP
Applications
Audio
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/audio
Automotive
Broadband
Digital Control
Military
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
interface.ti.com
logic.ti.com
Logic
Power Mgmt
Microcontrollers
RFID
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lpw
Telephony
Low Power
Wireless
Video & Imaging
Wireless
www.ti.com/wireless
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相关型号：
CDC5801ADBQG4
Low Jitter Clock Multiplier & Divider w/Programmable Delay & Phase Alignment 24-SSOP -40 to 85
TI
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